Macros
#define	DMA_CH0_AL1_CTRL_ACCESS "RW"

#define	DMA_CH0_AL1_CTRL_BITS _u(0xffffffff)

#define	DMA_CH0_AL1_CTRL_LSB _u(0)

#define	DMA_CH0_AL1_CTRL_MSB _u(31)

#define	DMA_CH0_AL1_CTRL_OFFSET _u(0x00000010)

#define	DMA_CH0_AL1_CTRL_RESET "-"

#define	DMA_CH0_AL1_READ_ADDR_ACCESS "RW"

#define	DMA_CH0_AL1_READ_ADDR_BITS _u(0xffffffff)

#define	DMA_CH0_AL1_READ_ADDR_LSB _u(0)

#define	DMA_CH0_AL1_READ_ADDR_MSB _u(31)

#define	DMA_CH0_AL1_READ_ADDR_OFFSET _u(0x00000014)

#define	DMA_CH0_AL1_READ_ADDR_RESET "-"

#define	DMA_CH0_AL1_TRANS_COUNT_TRIG_ACCESS "RW"

#define	DMA_CH0_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff)

#define	DMA_CH0_AL1_TRANS_COUNT_TRIG_LSB _u(0)

#define	DMA_CH0_AL1_TRANS_COUNT_TRIG_MSB _u(31)

#define	DMA_CH0_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000001c)

#define	DMA_CH0_AL1_TRANS_COUNT_TRIG_RESET "-"

#define	DMA_CH0_AL1_WRITE_ADDR_ACCESS "RW"

#define	DMA_CH0_AL1_WRITE_ADDR_BITS _u(0xffffffff)

#define	DMA_CH0_AL1_WRITE_ADDR_LSB _u(0)

#define	DMA_CH0_AL1_WRITE_ADDR_MSB _u(31)

#define	DMA_CH0_AL1_WRITE_ADDR_OFFSET _u(0x00000018)

#define	DMA_CH0_AL1_WRITE_ADDR_RESET "-"

#define	DMA_CH0_AL2_CTRL_ACCESS "RW"

#define	DMA_CH0_AL2_CTRL_BITS _u(0xffffffff)

#define	DMA_CH0_AL2_CTRL_LSB _u(0)

#define	DMA_CH0_AL2_CTRL_MSB _u(31)

#define	DMA_CH0_AL2_CTRL_OFFSET _u(0x00000020)

#define	DMA_CH0_AL2_CTRL_RESET "-"

#define	DMA_CH0_AL2_READ_ADDR_ACCESS "RW"

#define	DMA_CH0_AL2_READ_ADDR_BITS _u(0xffffffff)

#define	DMA_CH0_AL2_READ_ADDR_LSB _u(0)

#define	DMA_CH0_AL2_READ_ADDR_MSB _u(31)

#define	DMA_CH0_AL2_READ_ADDR_OFFSET _u(0x00000028)

#define	DMA_CH0_AL2_READ_ADDR_RESET "-"

#define	DMA_CH0_AL2_TRANS_COUNT_ACCESS "RW"

#define	DMA_CH0_AL2_TRANS_COUNT_BITS _u(0xffffffff)

#define	DMA_CH0_AL2_TRANS_COUNT_LSB _u(0)

#define	DMA_CH0_AL2_TRANS_COUNT_MSB _u(31)

#define	DMA_CH0_AL2_TRANS_COUNT_OFFSET _u(0x00000024)

#define	DMA_CH0_AL2_TRANS_COUNT_RESET "-"

#define	DMA_CH0_AL2_WRITE_ADDR_TRIG_ACCESS "RW"

#define	DMA_CH0_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff)

#define	DMA_CH0_AL2_WRITE_ADDR_TRIG_LSB _u(0)

#define	DMA_CH0_AL2_WRITE_ADDR_TRIG_MSB _u(31)

#define	DMA_CH0_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x0000002c)

#define	DMA_CH0_AL2_WRITE_ADDR_TRIG_RESET "-"

#define	DMA_CH0_AL3_CTRL_ACCESS "RW"

#define	DMA_CH0_AL3_CTRL_BITS _u(0xffffffff)

#define	DMA_CH0_AL3_CTRL_LSB _u(0)

#define	DMA_CH0_AL3_CTRL_MSB _u(31)

#define	DMA_CH0_AL3_CTRL_OFFSET _u(0x00000030)

#define	DMA_CH0_AL3_CTRL_RESET "-"

#define	DMA_CH0_AL3_READ_ADDR_TRIG_ACCESS "RW"

#define	DMA_CH0_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff)

#define	DMA_CH0_AL3_READ_ADDR_TRIG_LSB _u(0)

#define	DMA_CH0_AL3_READ_ADDR_TRIG_MSB _u(31)

#define	DMA_CH0_AL3_READ_ADDR_TRIG_OFFSET _u(0x0000003c)

#define	DMA_CH0_AL3_READ_ADDR_TRIG_RESET "-"

#define	DMA_CH0_AL3_TRANS_COUNT_ACCESS "RW"

#define	DMA_CH0_AL3_TRANS_COUNT_BITS _u(0xffffffff)

#define	DMA_CH0_AL3_TRANS_COUNT_LSB _u(0)

#define	DMA_CH0_AL3_TRANS_COUNT_MSB _u(31)

#define	DMA_CH0_AL3_TRANS_COUNT_OFFSET _u(0x00000038)

#define	DMA_CH0_AL3_TRANS_COUNT_RESET "-"

#define	DMA_CH0_AL3_WRITE_ADDR_ACCESS "RW"

#define	DMA_CH0_AL3_WRITE_ADDR_BITS _u(0xffffffff)

#define	DMA_CH0_AL3_WRITE_ADDR_LSB _u(0)

#define	DMA_CH0_AL3_WRITE_ADDR_MSB _u(31)

#define	DMA_CH0_AL3_WRITE_ADDR_OFFSET _u(0x00000034)

#define	DMA_CH0_AL3_WRITE_ADDR_RESET "-"

#define	DMA_CH0_CTRL_TRIG_AHB_ERROR_ACCESS "RO"

#define	DMA_CH0_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000)

#define	DMA_CH0_CTRL_TRIG_AHB_ERROR_LSB _u(31)

#define	DMA_CH0_CTRL_TRIG_AHB_ERROR_MSB _u(31)

#define	DMA_CH0_CTRL_TRIG_AHB_ERROR_RESET _u(0x0)

#define	DMA_CH0_CTRL_TRIG_BITS _u(0xe7ffffff)

#define	DMA_CH0_CTRL_TRIG_BSWAP_ACCESS "RW"

#define	DMA_CH0_CTRL_TRIG_BSWAP_BITS _u(0x01000000)

#define	DMA_CH0_CTRL_TRIG_BSWAP_LSB _u(24)

#define	DMA_CH0_CTRL_TRIG_BSWAP_MSB _u(24)

#define	DMA_CH0_CTRL_TRIG_BSWAP_RESET _u(0x0)

#define	DMA_CH0_CTRL_TRIG_BUSY_ACCESS "RO"

#define	DMA_CH0_CTRL_TRIG_BUSY_BITS _u(0x04000000)

#define	DMA_CH0_CTRL_TRIG_BUSY_LSB _u(26)

#define	DMA_CH0_CTRL_TRIG_BUSY_MSB _u(26)

#define	DMA_CH0_CTRL_TRIG_BUSY_RESET _u(0x0)

#define	DMA_CH0_CTRL_TRIG_CHAIN_TO_ACCESS "RW"

#define	DMA_CH0_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000)

#define	DMA_CH0_CTRL_TRIG_CHAIN_TO_LSB _u(13)

#define	DMA_CH0_CTRL_TRIG_CHAIN_TO_MSB _u(16)

#define	DMA_CH0_CTRL_TRIG_CHAIN_TO_RESET _u(0x0)

#define	DMA_CH0_CTRL_TRIG_DATA_SIZE_ACCESS "RW"

#define	DMA_CH0_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c)

#define	DMA_CH0_CTRL_TRIG_DATA_SIZE_LSB _u(2)

#define	DMA_CH0_CTRL_TRIG_DATA_SIZE_MSB _u(3)

#define	DMA_CH0_CTRL_TRIG_DATA_SIZE_RESET _u(0x0)

#define	DMA_CH0_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0)

#define	DMA_CH0_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1)

#define	DMA_CH0_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2)

#define	DMA_CH0_CTRL_TRIG_EN_ACCESS "RW"

#define	DMA_CH0_CTRL_TRIG_EN_BITS _u(0x00000001)

#define	DMA_CH0_CTRL_TRIG_EN_LSB _u(0)

#define	DMA_CH0_CTRL_TRIG_EN_MSB _u(0)

#define	DMA_CH0_CTRL_TRIG_EN_RESET _u(0x0)

#define	DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW"

#define	DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002)

#define	DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1)

#define	DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1)

#define	DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0)

#define	DMA_CH0_CTRL_TRIG_INCR_READ_ACCESS "RW"

#define	DMA_CH0_CTRL_TRIG_INCR_READ_BITS _u(0x00000010)

#define	DMA_CH0_CTRL_TRIG_INCR_READ_LSB _u(4)

#define	DMA_CH0_CTRL_TRIG_INCR_READ_MSB _u(4)

#define	DMA_CH0_CTRL_TRIG_INCR_READ_RESET _u(0x0)

#define	DMA_CH0_CTRL_TRIG_INCR_READ_REV_ACCESS "RW"

#define	DMA_CH0_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020)

#define	DMA_CH0_CTRL_TRIG_INCR_READ_REV_LSB _u(5)

#define	DMA_CH0_CTRL_TRIG_INCR_READ_REV_MSB _u(5)

#define	DMA_CH0_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0)

#define	DMA_CH0_CTRL_TRIG_INCR_WRITE_ACCESS "RW"

#define	DMA_CH0_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040)

#define	DMA_CH0_CTRL_TRIG_INCR_WRITE_LSB _u(6)

#define	DMA_CH0_CTRL_TRIG_INCR_WRITE_MSB _u(6)

#define	DMA_CH0_CTRL_TRIG_INCR_WRITE_RESET _u(0x0)

#define	DMA_CH0_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW"

#define	DMA_CH0_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080)

#define	DMA_CH0_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7)

#define	DMA_CH0_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7)

#define	DMA_CH0_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0)

#define	DMA_CH0_CTRL_TRIG_IRQ_QUIET_ACCESS "RW"

#define	DMA_CH0_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000)

#define	DMA_CH0_CTRL_TRIG_IRQ_QUIET_LSB _u(23)

#define	DMA_CH0_CTRL_TRIG_IRQ_QUIET_MSB _u(23)

#define	DMA_CH0_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0)

#define	DMA_CH0_CTRL_TRIG_OFFSET _u(0x0000000c)

#define	DMA_CH0_CTRL_TRIG_READ_ERROR_ACCESS "WC"

#define	DMA_CH0_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000)

#define	DMA_CH0_CTRL_TRIG_READ_ERROR_LSB _u(30)

#define	DMA_CH0_CTRL_TRIG_READ_ERROR_MSB _u(30)

#define	DMA_CH0_CTRL_TRIG_READ_ERROR_RESET _u(0x0)

#define	DMA_CH0_CTRL_TRIG_RESET _u(0x00000000)

#define	DMA_CH0_CTRL_TRIG_RING_SEL_ACCESS "RW"

#define	DMA_CH0_CTRL_TRIG_RING_SEL_BITS _u(0x00001000)

#define	DMA_CH0_CTRL_TRIG_RING_SEL_LSB _u(12)

#define	DMA_CH0_CTRL_TRIG_RING_SEL_MSB _u(12)

#define	DMA_CH0_CTRL_TRIG_RING_SEL_RESET _u(0x0)

#define	DMA_CH0_CTRL_TRIG_RING_SIZE_ACCESS "RW"

#define	DMA_CH0_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00)

#define	DMA_CH0_CTRL_TRIG_RING_SIZE_LSB _u(8)

#define	DMA_CH0_CTRL_TRIG_RING_SIZE_MSB _u(11)

#define	DMA_CH0_CTRL_TRIG_RING_SIZE_RESET _u(0x0)

#define	DMA_CH0_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0)

#define	DMA_CH0_CTRL_TRIG_SNIFF_EN_ACCESS "RW"

#define	DMA_CH0_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000)

#define	DMA_CH0_CTRL_TRIG_SNIFF_EN_LSB _u(25)

#define	DMA_CH0_CTRL_TRIG_SNIFF_EN_MSB _u(25)

#define	DMA_CH0_CTRL_TRIG_SNIFF_EN_RESET _u(0x0)

#define	DMA_CH0_CTRL_TRIG_TREQ_SEL_ACCESS "RW"

#define	DMA_CH0_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000)

#define	DMA_CH0_CTRL_TRIG_TREQ_SEL_LSB _u(17)

#define	DMA_CH0_CTRL_TRIG_TREQ_SEL_MSB _u(22)

#define	DMA_CH0_CTRL_TRIG_TREQ_SEL_RESET _u(0x00)

#define	DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f)

#define	DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b)

#define	DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c)

#define	DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d)

#define	DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e)

#define	DMA_CH0_CTRL_TRIG_WRITE_ERROR_ACCESS "WC"

#define	DMA_CH0_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000)

#define	DMA_CH0_CTRL_TRIG_WRITE_ERROR_LSB _u(29)

#define	DMA_CH0_CTRL_TRIG_WRITE_ERROR_MSB _u(29)

#define	DMA_CH0_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0)

#define	DMA_CH0_DBG_CTDREQ_ACCESS "WC"

#define	DMA_CH0_DBG_CTDREQ_BITS _u(0x0000003f)

#define	DMA_CH0_DBG_CTDREQ_LSB _u(0)

#define	DMA_CH0_DBG_CTDREQ_MSB _u(5)

#define	DMA_CH0_DBG_CTDREQ_OFFSET _u(0x00000800)

#define	DMA_CH0_DBG_CTDREQ_RESET _u(0x00000000)

#define	DMA_CH0_DBG_TCR_ACCESS "RO"

#define	DMA_CH0_DBG_TCR_BITS _u(0xffffffff)

#define	DMA_CH0_DBG_TCR_LSB _u(0)

#define	DMA_CH0_DBG_TCR_MSB _u(31)

#define	DMA_CH0_DBG_TCR_OFFSET _u(0x00000804)

#define	DMA_CH0_DBG_TCR_RESET _u(0x00000000)

#define	DMA_CH0_READ_ADDR_ACCESS "RW"

#define	DMA_CH0_READ_ADDR_BITS _u(0xffffffff)

#define	DMA_CH0_READ_ADDR_LSB _u(0)

#define	DMA_CH0_READ_ADDR_MSB _u(31)

#define	DMA_CH0_READ_ADDR_OFFSET _u(0x00000000)
	Copyright (c) 2024 Raspberry Pi Ltd.

#define	DMA_CH0_READ_ADDR_RESET _u(0x00000000)

#define	DMA_CH0_TRANS_COUNT_BITS _u(0xffffffff)

#define	DMA_CH0_TRANS_COUNT_COUNT_ACCESS "RW"

#define	DMA_CH0_TRANS_COUNT_COUNT_BITS _u(0x0fffffff)

#define	DMA_CH0_TRANS_COUNT_COUNT_LSB _u(0)

#define	DMA_CH0_TRANS_COUNT_COUNT_MSB _u(27)

#define	DMA_CH0_TRANS_COUNT_COUNT_RESET _u(0x0000000)

#define	DMA_CH0_TRANS_COUNT_MODE_ACCESS "RW"

#define	DMA_CH0_TRANS_COUNT_MODE_BITS _u(0xf0000000)

#define	DMA_CH0_TRANS_COUNT_MODE_LSB _u(28)

#define	DMA_CH0_TRANS_COUNT_MODE_MSB _u(31)

#define	DMA_CH0_TRANS_COUNT_MODE_RESET _u(0x0)

#define	DMA_CH0_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf)

#define	DMA_CH0_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0)

#define	DMA_CH0_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1)

#define	DMA_CH0_TRANS_COUNT_OFFSET _u(0x00000008)

#define	DMA_CH0_TRANS_COUNT_RESET _u(0x00000000)

#define	DMA_CH0_WRITE_ADDR_ACCESS "RW"

#define	DMA_CH0_WRITE_ADDR_BITS _u(0xffffffff)

#define	DMA_CH0_WRITE_ADDR_LSB _u(0)

#define	DMA_CH0_WRITE_ADDR_MSB _u(31)

#define	DMA_CH0_WRITE_ADDR_OFFSET _u(0x00000004)

#define	DMA_CH0_WRITE_ADDR_RESET _u(0x00000000)

#define	DMA_CH10_AL1_CTRL_ACCESS "RW"

#define	DMA_CH10_AL1_CTRL_BITS _u(0xffffffff)

#define	DMA_CH10_AL1_CTRL_LSB _u(0)

#define	DMA_CH10_AL1_CTRL_MSB _u(31)

#define	DMA_CH10_AL1_CTRL_OFFSET _u(0x00000290)

#define	DMA_CH10_AL1_CTRL_RESET "-"

#define	DMA_CH10_AL1_READ_ADDR_ACCESS "RW"

#define	DMA_CH10_AL1_READ_ADDR_BITS _u(0xffffffff)

#define	DMA_CH10_AL1_READ_ADDR_LSB _u(0)

#define	DMA_CH10_AL1_READ_ADDR_MSB _u(31)

#define	DMA_CH10_AL1_READ_ADDR_OFFSET _u(0x00000294)

#define	DMA_CH10_AL1_READ_ADDR_RESET "-"

#define	DMA_CH10_AL1_TRANS_COUNT_TRIG_ACCESS "RW"

#define	DMA_CH10_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff)

#define	DMA_CH10_AL1_TRANS_COUNT_TRIG_LSB _u(0)

#define	DMA_CH10_AL1_TRANS_COUNT_TRIG_MSB _u(31)

#define	DMA_CH10_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000029c)

#define	DMA_CH10_AL1_TRANS_COUNT_TRIG_RESET "-"

#define	DMA_CH10_AL1_WRITE_ADDR_ACCESS "RW"

#define	DMA_CH10_AL1_WRITE_ADDR_BITS _u(0xffffffff)

#define	DMA_CH10_AL1_WRITE_ADDR_LSB _u(0)

#define	DMA_CH10_AL1_WRITE_ADDR_MSB _u(31)

#define	DMA_CH10_AL1_WRITE_ADDR_OFFSET _u(0x00000298)

#define	DMA_CH10_AL1_WRITE_ADDR_RESET "-"

#define	DMA_CH10_AL2_CTRL_ACCESS "RW"

#define	DMA_CH10_AL2_CTRL_BITS _u(0xffffffff)

#define	DMA_CH10_AL2_CTRL_LSB _u(0)

#define	DMA_CH10_AL2_CTRL_MSB _u(31)

#define	DMA_CH10_AL2_CTRL_OFFSET _u(0x000002a0)

#define	DMA_CH10_AL2_CTRL_RESET "-"

#define	DMA_CH10_AL2_READ_ADDR_ACCESS "RW"

#define	DMA_CH10_AL2_READ_ADDR_BITS _u(0xffffffff)

#define	DMA_CH10_AL2_READ_ADDR_LSB _u(0)

#define	DMA_CH10_AL2_READ_ADDR_MSB _u(31)

#define	DMA_CH10_AL2_READ_ADDR_OFFSET _u(0x000002a8)

#define	DMA_CH10_AL2_READ_ADDR_RESET "-"

#define	DMA_CH10_AL2_TRANS_COUNT_ACCESS "RW"

#define	DMA_CH10_AL2_TRANS_COUNT_BITS _u(0xffffffff)

#define	DMA_CH10_AL2_TRANS_COUNT_LSB _u(0)

#define	DMA_CH10_AL2_TRANS_COUNT_MSB _u(31)

#define	DMA_CH10_AL2_TRANS_COUNT_OFFSET _u(0x000002a4)

#define	DMA_CH10_AL2_TRANS_COUNT_RESET "-"

#define	DMA_CH10_AL2_WRITE_ADDR_TRIG_ACCESS "RW"

#define	DMA_CH10_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff)

#define	DMA_CH10_AL2_WRITE_ADDR_TRIG_LSB _u(0)

#define	DMA_CH10_AL2_WRITE_ADDR_TRIG_MSB _u(31)

#define	DMA_CH10_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x000002ac)

#define	DMA_CH10_AL2_WRITE_ADDR_TRIG_RESET "-"

#define	DMA_CH10_AL3_CTRL_ACCESS "RW"

#define	DMA_CH10_AL3_CTRL_BITS _u(0xffffffff)

#define	DMA_CH10_AL3_CTRL_LSB _u(0)

#define	DMA_CH10_AL3_CTRL_MSB _u(31)

#define	DMA_CH10_AL3_CTRL_OFFSET _u(0x000002b0)

#define	DMA_CH10_AL3_CTRL_RESET "-"

#define	DMA_CH10_AL3_READ_ADDR_TRIG_ACCESS "RW"

#define	DMA_CH10_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff)

#define	DMA_CH10_AL3_READ_ADDR_TRIG_LSB _u(0)

#define	DMA_CH10_AL3_READ_ADDR_TRIG_MSB _u(31)

#define	DMA_CH10_AL3_READ_ADDR_TRIG_OFFSET _u(0x000002bc)

#define	DMA_CH10_AL3_READ_ADDR_TRIG_RESET "-"

#define	DMA_CH10_AL3_TRANS_COUNT_ACCESS "RW"

#define	DMA_CH10_AL3_TRANS_COUNT_BITS _u(0xffffffff)

#define	DMA_CH10_AL3_TRANS_COUNT_LSB _u(0)

#define	DMA_CH10_AL3_TRANS_COUNT_MSB _u(31)

#define	DMA_CH10_AL3_TRANS_COUNT_OFFSET _u(0x000002b8)

#define	DMA_CH10_AL3_TRANS_COUNT_RESET "-"

#define	DMA_CH10_AL3_WRITE_ADDR_ACCESS "RW"

#define	DMA_CH10_AL3_WRITE_ADDR_BITS _u(0xffffffff)

#define	DMA_CH10_AL3_WRITE_ADDR_LSB _u(0)

#define	DMA_CH10_AL3_WRITE_ADDR_MSB _u(31)

#define	DMA_CH10_AL3_WRITE_ADDR_OFFSET _u(0x000002b4)

#define	DMA_CH10_AL3_WRITE_ADDR_RESET "-"

#define	DMA_CH10_CTRL_TRIG_AHB_ERROR_ACCESS "RO"

#define	DMA_CH10_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000)

#define	DMA_CH10_CTRL_TRIG_AHB_ERROR_LSB _u(31)

#define	DMA_CH10_CTRL_TRIG_AHB_ERROR_MSB _u(31)

#define	DMA_CH10_CTRL_TRIG_AHB_ERROR_RESET _u(0x0)

#define	DMA_CH10_CTRL_TRIG_BITS _u(0xe7ffffff)

#define	DMA_CH10_CTRL_TRIG_BSWAP_ACCESS "RW"

#define	DMA_CH10_CTRL_TRIG_BSWAP_BITS _u(0x01000000)

#define	DMA_CH10_CTRL_TRIG_BSWAP_LSB _u(24)

#define	DMA_CH10_CTRL_TRIG_BSWAP_MSB _u(24)

#define	DMA_CH10_CTRL_TRIG_BSWAP_RESET _u(0x0)

#define	DMA_CH10_CTRL_TRIG_BUSY_ACCESS "RO"

#define	DMA_CH10_CTRL_TRIG_BUSY_BITS _u(0x04000000)

#define	DMA_CH10_CTRL_TRIG_BUSY_LSB _u(26)

#define	DMA_CH10_CTRL_TRIG_BUSY_MSB _u(26)

#define	DMA_CH10_CTRL_TRIG_BUSY_RESET _u(0x0)

#define	DMA_CH10_CTRL_TRIG_CHAIN_TO_ACCESS "RW"

#define	DMA_CH10_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000)

#define	DMA_CH10_CTRL_TRIG_CHAIN_TO_LSB _u(13)

#define	DMA_CH10_CTRL_TRIG_CHAIN_TO_MSB _u(16)

#define	DMA_CH10_CTRL_TRIG_CHAIN_TO_RESET _u(0x0)

#define	DMA_CH10_CTRL_TRIG_DATA_SIZE_ACCESS "RW"

#define	DMA_CH10_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c)

#define	DMA_CH10_CTRL_TRIG_DATA_SIZE_LSB _u(2)

#define	DMA_CH10_CTRL_TRIG_DATA_SIZE_MSB _u(3)

#define	DMA_CH10_CTRL_TRIG_DATA_SIZE_RESET _u(0x0)

#define	DMA_CH10_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0)

#define	DMA_CH10_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1)

#define	DMA_CH10_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2)

#define	DMA_CH10_CTRL_TRIG_EN_ACCESS "RW"

#define	DMA_CH10_CTRL_TRIG_EN_BITS _u(0x00000001)

#define	DMA_CH10_CTRL_TRIG_EN_LSB _u(0)

#define	DMA_CH10_CTRL_TRIG_EN_MSB _u(0)

#define	DMA_CH10_CTRL_TRIG_EN_RESET _u(0x0)

#define	DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW"

#define	DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002)

#define	DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1)

#define	DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1)

#define	DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0)

#define	DMA_CH10_CTRL_TRIG_INCR_READ_ACCESS "RW"

#define	DMA_CH10_CTRL_TRIG_INCR_READ_BITS _u(0x00000010)

#define	DMA_CH10_CTRL_TRIG_INCR_READ_LSB _u(4)

#define	DMA_CH10_CTRL_TRIG_INCR_READ_MSB _u(4)

#define	DMA_CH10_CTRL_TRIG_INCR_READ_RESET _u(0x0)

#define	DMA_CH10_CTRL_TRIG_INCR_READ_REV_ACCESS "RW"

#define	DMA_CH10_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020)

#define	DMA_CH10_CTRL_TRIG_INCR_READ_REV_LSB _u(5)

#define	DMA_CH10_CTRL_TRIG_INCR_READ_REV_MSB _u(5)

#define	DMA_CH10_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0)

#define	DMA_CH10_CTRL_TRIG_INCR_WRITE_ACCESS "RW"

#define	DMA_CH10_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040)

#define	DMA_CH10_CTRL_TRIG_INCR_WRITE_LSB _u(6)

#define	DMA_CH10_CTRL_TRIG_INCR_WRITE_MSB _u(6)

#define	DMA_CH10_CTRL_TRIG_INCR_WRITE_RESET _u(0x0)

#define	DMA_CH10_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW"

#define	DMA_CH10_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080)

#define	DMA_CH10_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7)

#define	DMA_CH10_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7)

#define	DMA_CH10_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0)

#define	DMA_CH10_CTRL_TRIG_IRQ_QUIET_ACCESS "RW"

#define	DMA_CH10_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000)

#define	DMA_CH10_CTRL_TRIG_IRQ_QUIET_LSB _u(23)

#define	DMA_CH10_CTRL_TRIG_IRQ_QUIET_MSB _u(23)

#define	DMA_CH10_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0)

#define	DMA_CH10_CTRL_TRIG_OFFSET _u(0x0000028c)

#define	DMA_CH10_CTRL_TRIG_READ_ERROR_ACCESS "WC"

#define	DMA_CH10_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000)

#define	DMA_CH10_CTRL_TRIG_READ_ERROR_LSB _u(30)

#define	DMA_CH10_CTRL_TRIG_READ_ERROR_MSB _u(30)

#define	DMA_CH10_CTRL_TRIG_READ_ERROR_RESET _u(0x0)

#define	DMA_CH10_CTRL_TRIG_RESET _u(0x00000000)

#define	DMA_CH10_CTRL_TRIG_RING_SEL_ACCESS "RW"

#define	DMA_CH10_CTRL_TRIG_RING_SEL_BITS _u(0x00001000)

#define	DMA_CH10_CTRL_TRIG_RING_SEL_LSB _u(12)

#define	DMA_CH10_CTRL_TRIG_RING_SEL_MSB _u(12)

#define	DMA_CH10_CTRL_TRIG_RING_SEL_RESET _u(0x0)

#define	DMA_CH10_CTRL_TRIG_RING_SIZE_ACCESS "RW"

#define	DMA_CH10_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00)

#define	DMA_CH10_CTRL_TRIG_RING_SIZE_LSB _u(8)

#define	DMA_CH10_CTRL_TRIG_RING_SIZE_MSB _u(11)

#define	DMA_CH10_CTRL_TRIG_RING_SIZE_RESET _u(0x0)

#define	DMA_CH10_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0)

#define	DMA_CH10_CTRL_TRIG_SNIFF_EN_ACCESS "RW"

#define	DMA_CH10_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000)

#define	DMA_CH10_CTRL_TRIG_SNIFF_EN_LSB _u(25)

#define	DMA_CH10_CTRL_TRIG_SNIFF_EN_MSB _u(25)

#define	DMA_CH10_CTRL_TRIG_SNIFF_EN_RESET _u(0x0)

#define	DMA_CH10_CTRL_TRIG_TREQ_SEL_ACCESS "RW"

#define	DMA_CH10_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000)

#define	DMA_CH10_CTRL_TRIG_TREQ_SEL_LSB _u(17)

#define	DMA_CH10_CTRL_TRIG_TREQ_SEL_MSB _u(22)

#define	DMA_CH10_CTRL_TRIG_TREQ_SEL_RESET _u(0x00)

#define	DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f)

#define	DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b)

#define	DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c)

#define	DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d)

#define	DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e)

#define	DMA_CH10_CTRL_TRIG_WRITE_ERROR_ACCESS "WC"

#define	DMA_CH10_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000)

#define	DMA_CH10_CTRL_TRIG_WRITE_ERROR_LSB _u(29)

#define	DMA_CH10_CTRL_TRIG_WRITE_ERROR_MSB _u(29)

#define	DMA_CH10_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0)

#define	DMA_CH10_DBG_CTDREQ_ACCESS "WC"

#define	DMA_CH10_DBG_CTDREQ_BITS _u(0x0000003f)

#define	DMA_CH10_DBG_CTDREQ_LSB _u(0)

#define	DMA_CH10_DBG_CTDREQ_MSB _u(5)

#define	DMA_CH10_DBG_CTDREQ_OFFSET _u(0x00000a80)

#define	DMA_CH10_DBG_CTDREQ_RESET _u(0x00000000)

#define	DMA_CH10_DBG_TCR_ACCESS "RO"

#define	DMA_CH10_DBG_TCR_BITS _u(0xffffffff)

#define	DMA_CH10_DBG_TCR_LSB _u(0)

#define	DMA_CH10_DBG_TCR_MSB _u(31)

#define	DMA_CH10_DBG_TCR_OFFSET _u(0x00000a84)

#define	DMA_CH10_DBG_TCR_RESET _u(0x00000000)

#define	DMA_CH10_READ_ADDR_ACCESS "RW"

#define	DMA_CH10_READ_ADDR_BITS _u(0xffffffff)

#define	DMA_CH10_READ_ADDR_LSB _u(0)

#define	DMA_CH10_READ_ADDR_MSB _u(31)

#define	DMA_CH10_READ_ADDR_OFFSET _u(0x00000280)

#define	DMA_CH10_READ_ADDR_RESET _u(0x00000000)

#define	DMA_CH10_TRANS_COUNT_BITS _u(0xffffffff)

#define	DMA_CH10_TRANS_COUNT_COUNT_ACCESS "RW"

#define	DMA_CH10_TRANS_COUNT_COUNT_BITS _u(0x0fffffff)

#define	DMA_CH10_TRANS_COUNT_COUNT_LSB _u(0)

#define	DMA_CH10_TRANS_COUNT_COUNT_MSB _u(27)

#define	DMA_CH10_TRANS_COUNT_COUNT_RESET _u(0x0000000)

#define	DMA_CH10_TRANS_COUNT_MODE_ACCESS "RW"

#define	DMA_CH10_TRANS_COUNT_MODE_BITS _u(0xf0000000)

#define	DMA_CH10_TRANS_COUNT_MODE_LSB _u(28)

#define	DMA_CH10_TRANS_COUNT_MODE_MSB _u(31)

#define	DMA_CH10_TRANS_COUNT_MODE_RESET _u(0x0)

#define	DMA_CH10_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf)

#define	DMA_CH10_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0)

#define	DMA_CH10_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1)

#define	DMA_CH10_TRANS_COUNT_OFFSET _u(0x00000288)

#define	DMA_CH10_TRANS_COUNT_RESET _u(0x00000000)

#define	DMA_CH10_WRITE_ADDR_ACCESS "RW"

#define	DMA_CH10_WRITE_ADDR_BITS _u(0xffffffff)

#define	DMA_CH10_WRITE_ADDR_LSB _u(0)

#define	DMA_CH10_WRITE_ADDR_MSB _u(31)

#define	DMA_CH10_WRITE_ADDR_OFFSET _u(0x00000284)

#define	DMA_CH10_WRITE_ADDR_RESET _u(0x00000000)

#define	DMA_CH11_AL1_CTRL_ACCESS "RW"

#define	DMA_CH11_AL1_CTRL_BITS _u(0xffffffff)

#define	DMA_CH11_AL1_CTRL_LSB _u(0)

#define	DMA_CH11_AL1_CTRL_MSB _u(31)

#define	DMA_CH11_AL1_CTRL_OFFSET _u(0x000002d0)

#define	DMA_CH11_AL1_CTRL_RESET "-"

#define	DMA_CH11_AL1_READ_ADDR_ACCESS "RW"

#define	DMA_CH11_AL1_READ_ADDR_BITS _u(0xffffffff)

#define	DMA_CH11_AL1_READ_ADDR_LSB _u(0)

#define	DMA_CH11_AL1_READ_ADDR_MSB _u(31)

#define	DMA_CH11_AL1_READ_ADDR_OFFSET _u(0x000002d4)

#define	DMA_CH11_AL1_READ_ADDR_RESET "-"

#define	DMA_CH11_AL1_TRANS_COUNT_TRIG_ACCESS "RW"

#define	DMA_CH11_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff)

#define	DMA_CH11_AL1_TRANS_COUNT_TRIG_LSB _u(0)

#define	DMA_CH11_AL1_TRANS_COUNT_TRIG_MSB _u(31)

#define	DMA_CH11_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x000002dc)

#define	DMA_CH11_AL1_TRANS_COUNT_TRIG_RESET "-"

#define	DMA_CH11_AL1_WRITE_ADDR_ACCESS "RW"

#define	DMA_CH11_AL1_WRITE_ADDR_BITS _u(0xffffffff)

#define	DMA_CH11_AL1_WRITE_ADDR_LSB _u(0)

#define	DMA_CH11_AL1_WRITE_ADDR_MSB _u(31)

#define	DMA_CH11_AL1_WRITE_ADDR_OFFSET _u(0x000002d8)

#define	DMA_CH11_AL1_WRITE_ADDR_RESET "-"

#define	DMA_CH11_AL2_CTRL_ACCESS "RW"

#define	DMA_CH11_AL2_CTRL_BITS _u(0xffffffff)

#define	DMA_CH11_AL2_CTRL_LSB _u(0)

#define	DMA_CH11_AL2_CTRL_MSB _u(31)

#define	DMA_CH11_AL2_CTRL_OFFSET _u(0x000002e0)

#define	DMA_CH11_AL2_CTRL_RESET "-"

#define	DMA_CH11_AL2_READ_ADDR_ACCESS "RW"

#define	DMA_CH11_AL2_READ_ADDR_BITS _u(0xffffffff)

#define	DMA_CH11_AL2_READ_ADDR_LSB _u(0)

#define	DMA_CH11_AL2_READ_ADDR_MSB _u(31)

#define	DMA_CH11_AL2_READ_ADDR_OFFSET _u(0x000002e8)

#define	DMA_CH11_AL2_READ_ADDR_RESET "-"

#define	DMA_CH11_AL2_TRANS_COUNT_ACCESS "RW"

#define	DMA_CH11_AL2_TRANS_COUNT_BITS _u(0xffffffff)

#define	DMA_CH11_AL2_TRANS_COUNT_LSB _u(0)

#define	DMA_CH11_AL2_TRANS_COUNT_MSB _u(31)

#define	DMA_CH11_AL2_TRANS_COUNT_OFFSET _u(0x000002e4)

#define	DMA_CH11_AL2_TRANS_COUNT_RESET "-"

#define	DMA_CH11_AL2_WRITE_ADDR_TRIG_ACCESS "RW"

#define	DMA_CH11_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff)

#define	DMA_CH11_AL2_WRITE_ADDR_TRIG_LSB _u(0)

#define	DMA_CH11_AL2_WRITE_ADDR_TRIG_MSB _u(31)

#define	DMA_CH11_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x000002ec)

#define	DMA_CH11_AL2_WRITE_ADDR_TRIG_RESET "-"

#define	DMA_CH11_AL3_CTRL_ACCESS "RW"

#define	DMA_CH11_AL3_CTRL_BITS _u(0xffffffff)

#define	DMA_CH11_AL3_CTRL_LSB _u(0)

#define	DMA_CH11_AL3_CTRL_MSB _u(31)

#define	DMA_CH11_AL3_CTRL_OFFSET _u(0x000002f0)

#define	DMA_CH11_AL3_CTRL_RESET "-"

#define	DMA_CH11_AL3_READ_ADDR_TRIG_ACCESS "RW"

#define	DMA_CH11_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff)

#define	DMA_CH11_AL3_READ_ADDR_TRIG_LSB _u(0)

#define	DMA_CH11_AL3_READ_ADDR_TRIG_MSB _u(31)

#define	DMA_CH11_AL3_READ_ADDR_TRIG_OFFSET _u(0x000002fc)

#define	DMA_CH11_AL3_READ_ADDR_TRIG_RESET "-"

#define	DMA_CH11_AL3_TRANS_COUNT_ACCESS "RW"

#define	DMA_CH11_AL3_TRANS_COUNT_BITS _u(0xffffffff)

#define	DMA_CH11_AL3_TRANS_COUNT_LSB _u(0)

#define	DMA_CH11_AL3_TRANS_COUNT_MSB _u(31)

#define	DMA_CH11_AL3_TRANS_COUNT_OFFSET _u(0x000002f8)

#define	DMA_CH11_AL3_TRANS_COUNT_RESET "-"

#define	DMA_CH11_AL3_WRITE_ADDR_ACCESS "RW"

#define	DMA_CH11_AL3_WRITE_ADDR_BITS _u(0xffffffff)

#define	DMA_CH11_AL3_WRITE_ADDR_LSB _u(0)

#define	DMA_CH11_AL3_WRITE_ADDR_MSB _u(31)

#define	DMA_CH11_AL3_WRITE_ADDR_OFFSET _u(0x000002f4)

#define	DMA_CH11_AL3_WRITE_ADDR_RESET "-"

#define	DMA_CH11_CTRL_TRIG_AHB_ERROR_ACCESS "RO"

#define	DMA_CH11_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000)

#define	DMA_CH11_CTRL_TRIG_AHB_ERROR_LSB _u(31)

#define	DMA_CH11_CTRL_TRIG_AHB_ERROR_MSB _u(31)

#define	DMA_CH11_CTRL_TRIG_AHB_ERROR_RESET _u(0x0)

#define	DMA_CH11_CTRL_TRIG_BITS _u(0xe7ffffff)

#define	DMA_CH11_CTRL_TRIG_BSWAP_ACCESS "RW"

#define	DMA_CH11_CTRL_TRIG_BSWAP_BITS _u(0x01000000)

#define	DMA_CH11_CTRL_TRIG_BSWAP_LSB _u(24)

#define	DMA_CH11_CTRL_TRIG_BSWAP_MSB _u(24)

#define	DMA_CH11_CTRL_TRIG_BSWAP_RESET _u(0x0)

#define	DMA_CH11_CTRL_TRIG_BUSY_ACCESS "RO"

#define	DMA_CH11_CTRL_TRIG_BUSY_BITS _u(0x04000000)

#define	DMA_CH11_CTRL_TRIG_BUSY_LSB _u(26)

#define	DMA_CH11_CTRL_TRIG_BUSY_MSB _u(26)

#define	DMA_CH11_CTRL_TRIG_BUSY_RESET _u(0x0)

#define	DMA_CH11_CTRL_TRIG_CHAIN_TO_ACCESS "RW"

#define	DMA_CH11_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000)

#define	DMA_CH11_CTRL_TRIG_CHAIN_TO_LSB _u(13)

#define	DMA_CH11_CTRL_TRIG_CHAIN_TO_MSB _u(16)

#define	DMA_CH11_CTRL_TRIG_CHAIN_TO_RESET _u(0x0)

#define	DMA_CH11_CTRL_TRIG_DATA_SIZE_ACCESS "RW"

#define	DMA_CH11_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c)

#define	DMA_CH11_CTRL_TRIG_DATA_SIZE_LSB _u(2)

#define	DMA_CH11_CTRL_TRIG_DATA_SIZE_MSB _u(3)

#define	DMA_CH11_CTRL_TRIG_DATA_SIZE_RESET _u(0x0)

#define	DMA_CH11_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0)

#define	DMA_CH11_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1)

#define	DMA_CH11_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2)

#define	DMA_CH11_CTRL_TRIG_EN_ACCESS "RW"

#define	DMA_CH11_CTRL_TRIG_EN_BITS _u(0x00000001)

#define	DMA_CH11_CTRL_TRIG_EN_LSB _u(0)

#define	DMA_CH11_CTRL_TRIG_EN_MSB _u(0)

#define	DMA_CH11_CTRL_TRIG_EN_RESET _u(0x0)

#define	DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW"

#define	DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002)

#define	DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1)

#define	DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1)

#define	DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0)

#define	DMA_CH11_CTRL_TRIG_INCR_READ_ACCESS "RW"

#define	DMA_CH11_CTRL_TRIG_INCR_READ_BITS _u(0x00000010)

#define	DMA_CH11_CTRL_TRIG_INCR_READ_LSB _u(4)

#define	DMA_CH11_CTRL_TRIG_INCR_READ_MSB _u(4)

#define	DMA_CH11_CTRL_TRIG_INCR_READ_RESET _u(0x0)

#define	DMA_CH11_CTRL_TRIG_INCR_READ_REV_ACCESS "RW"

#define	DMA_CH11_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020)

#define	DMA_CH11_CTRL_TRIG_INCR_READ_REV_LSB _u(5)

#define	DMA_CH11_CTRL_TRIG_INCR_READ_REV_MSB _u(5)

#define	DMA_CH11_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0)

#define	DMA_CH11_CTRL_TRIG_INCR_WRITE_ACCESS "RW"

#define	DMA_CH11_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040)

#define	DMA_CH11_CTRL_TRIG_INCR_WRITE_LSB _u(6)

#define	DMA_CH11_CTRL_TRIG_INCR_WRITE_MSB _u(6)

#define	DMA_CH11_CTRL_TRIG_INCR_WRITE_RESET _u(0x0)

#define	DMA_CH11_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW"

#define	DMA_CH11_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080)

#define	DMA_CH11_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7)

#define	DMA_CH11_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7)

#define	DMA_CH11_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0)

#define	DMA_CH11_CTRL_TRIG_IRQ_QUIET_ACCESS "RW"

#define	DMA_CH11_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000)

#define	DMA_CH11_CTRL_TRIG_IRQ_QUIET_LSB _u(23)

#define	DMA_CH11_CTRL_TRIG_IRQ_QUIET_MSB _u(23)

#define	DMA_CH11_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0)

#define	DMA_CH11_CTRL_TRIG_OFFSET _u(0x000002cc)

#define	DMA_CH11_CTRL_TRIG_READ_ERROR_ACCESS "WC"

#define	DMA_CH11_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000)

#define	DMA_CH11_CTRL_TRIG_READ_ERROR_LSB _u(30)

#define	DMA_CH11_CTRL_TRIG_READ_ERROR_MSB _u(30)

#define	DMA_CH11_CTRL_TRIG_READ_ERROR_RESET _u(0x0)

#define	DMA_CH11_CTRL_TRIG_RESET _u(0x00000000)

#define	DMA_CH11_CTRL_TRIG_RING_SEL_ACCESS "RW"

#define	DMA_CH11_CTRL_TRIG_RING_SEL_BITS _u(0x00001000)

#define	DMA_CH11_CTRL_TRIG_RING_SEL_LSB _u(12)

#define	DMA_CH11_CTRL_TRIG_RING_SEL_MSB _u(12)

#define	DMA_CH11_CTRL_TRIG_RING_SEL_RESET _u(0x0)

#define	DMA_CH11_CTRL_TRIG_RING_SIZE_ACCESS "RW"

#define	DMA_CH11_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00)

#define	DMA_CH11_CTRL_TRIG_RING_SIZE_LSB _u(8)

#define	DMA_CH11_CTRL_TRIG_RING_SIZE_MSB _u(11)

#define	DMA_CH11_CTRL_TRIG_RING_SIZE_RESET _u(0x0)

#define	DMA_CH11_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0)

#define	DMA_CH11_CTRL_TRIG_SNIFF_EN_ACCESS "RW"

#define	DMA_CH11_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000)

#define	DMA_CH11_CTRL_TRIG_SNIFF_EN_LSB _u(25)

#define	DMA_CH11_CTRL_TRIG_SNIFF_EN_MSB _u(25)

#define	DMA_CH11_CTRL_TRIG_SNIFF_EN_RESET _u(0x0)

#define	DMA_CH11_CTRL_TRIG_TREQ_SEL_ACCESS "RW"

#define	DMA_CH11_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000)

#define	DMA_CH11_CTRL_TRIG_TREQ_SEL_LSB _u(17)

#define	DMA_CH11_CTRL_TRIG_TREQ_SEL_MSB _u(22)

#define	DMA_CH11_CTRL_TRIG_TREQ_SEL_RESET _u(0x00)

#define	DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f)

#define	DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b)

#define	DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c)

#define	DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d)

#define	DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e)

#define	DMA_CH11_CTRL_TRIG_WRITE_ERROR_ACCESS "WC"

#define	DMA_CH11_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000)

#define	DMA_CH11_CTRL_TRIG_WRITE_ERROR_LSB _u(29)

#define	DMA_CH11_CTRL_TRIG_WRITE_ERROR_MSB _u(29)

#define	DMA_CH11_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0)

#define	DMA_CH11_DBG_CTDREQ_ACCESS "WC"

#define	DMA_CH11_DBG_CTDREQ_BITS _u(0x0000003f)

#define	DMA_CH11_DBG_CTDREQ_LSB _u(0)

#define	DMA_CH11_DBG_CTDREQ_MSB _u(5)

#define	DMA_CH11_DBG_CTDREQ_OFFSET _u(0x00000ac0)

#define	DMA_CH11_DBG_CTDREQ_RESET _u(0x00000000)

#define	DMA_CH11_DBG_TCR_ACCESS "RO"

#define	DMA_CH11_DBG_TCR_BITS _u(0xffffffff)

#define	DMA_CH11_DBG_TCR_LSB _u(0)

#define	DMA_CH11_DBG_TCR_MSB _u(31)

#define	DMA_CH11_DBG_TCR_OFFSET _u(0x00000ac4)

#define	DMA_CH11_DBG_TCR_RESET _u(0x00000000)

#define	DMA_CH11_READ_ADDR_ACCESS "RW"

#define	DMA_CH11_READ_ADDR_BITS _u(0xffffffff)

#define	DMA_CH11_READ_ADDR_LSB _u(0)

#define	DMA_CH11_READ_ADDR_MSB _u(31)

#define	DMA_CH11_READ_ADDR_OFFSET _u(0x000002c0)

#define	DMA_CH11_READ_ADDR_RESET _u(0x00000000)

#define	DMA_CH11_TRANS_COUNT_BITS _u(0xffffffff)

#define	DMA_CH11_TRANS_COUNT_COUNT_ACCESS "RW"

#define	DMA_CH11_TRANS_COUNT_COUNT_BITS _u(0x0fffffff)

#define	DMA_CH11_TRANS_COUNT_COUNT_LSB _u(0)

#define	DMA_CH11_TRANS_COUNT_COUNT_MSB _u(27)

#define	DMA_CH11_TRANS_COUNT_COUNT_RESET _u(0x0000000)

#define	DMA_CH11_TRANS_COUNT_MODE_ACCESS "RW"

#define	DMA_CH11_TRANS_COUNT_MODE_BITS _u(0xf0000000)

#define	DMA_CH11_TRANS_COUNT_MODE_LSB _u(28)

#define	DMA_CH11_TRANS_COUNT_MODE_MSB _u(31)

#define	DMA_CH11_TRANS_COUNT_MODE_RESET _u(0x0)

#define	DMA_CH11_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf)

#define	DMA_CH11_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0)

#define	DMA_CH11_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1)

#define	DMA_CH11_TRANS_COUNT_OFFSET _u(0x000002c8)

#define	DMA_CH11_TRANS_COUNT_RESET _u(0x00000000)

#define	DMA_CH11_WRITE_ADDR_ACCESS "RW"

#define	DMA_CH11_WRITE_ADDR_BITS _u(0xffffffff)

#define	DMA_CH11_WRITE_ADDR_LSB _u(0)

#define	DMA_CH11_WRITE_ADDR_MSB _u(31)

#define	DMA_CH11_WRITE_ADDR_OFFSET _u(0x000002c4)

#define	DMA_CH11_WRITE_ADDR_RESET _u(0x00000000)

#define	DMA_CH12_AL1_CTRL_ACCESS "RW"

#define	DMA_CH12_AL1_CTRL_BITS _u(0xffffffff)

#define	DMA_CH12_AL1_CTRL_LSB _u(0)

#define	DMA_CH12_AL1_CTRL_MSB _u(31)

#define	DMA_CH12_AL1_CTRL_OFFSET _u(0x00000310)

#define	DMA_CH12_AL1_CTRL_RESET "-"

#define	DMA_CH12_AL1_READ_ADDR_ACCESS "RW"

#define	DMA_CH12_AL1_READ_ADDR_BITS _u(0xffffffff)

#define	DMA_CH12_AL1_READ_ADDR_LSB _u(0)

#define	DMA_CH12_AL1_READ_ADDR_MSB _u(31)

#define	DMA_CH12_AL1_READ_ADDR_OFFSET _u(0x00000314)

#define	DMA_CH12_AL1_READ_ADDR_RESET "-"

#define	DMA_CH12_AL1_TRANS_COUNT_TRIG_ACCESS "RW"

#define	DMA_CH12_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff)

#define	DMA_CH12_AL1_TRANS_COUNT_TRIG_LSB _u(0)

#define	DMA_CH12_AL1_TRANS_COUNT_TRIG_MSB _u(31)

#define	DMA_CH12_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000031c)

#define	DMA_CH12_AL1_TRANS_COUNT_TRIG_RESET "-"

#define	DMA_CH12_AL1_WRITE_ADDR_ACCESS "RW"

#define	DMA_CH12_AL1_WRITE_ADDR_BITS _u(0xffffffff)

#define	DMA_CH12_AL1_WRITE_ADDR_LSB _u(0)

#define	DMA_CH12_AL1_WRITE_ADDR_MSB _u(31)

#define	DMA_CH12_AL1_WRITE_ADDR_OFFSET _u(0x00000318)

#define	DMA_CH12_AL1_WRITE_ADDR_RESET "-"

#define	DMA_CH12_AL2_CTRL_ACCESS "RW"

#define	DMA_CH12_AL2_CTRL_BITS _u(0xffffffff)

#define	DMA_CH12_AL2_CTRL_LSB _u(0)

#define	DMA_CH12_AL2_CTRL_MSB _u(31)

#define	DMA_CH12_AL2_CTRL_OFFSET _u(0x00000320)

#define	DMA_CH12_AL2_CTRL_RESET "-"

#define	DMA_CH12_AL2_READ_ADDR_ACCESS "RW"

#define	DMA_CH12_AL2_READ_ADDR_BITS _u(0xffffffff)

#define	DMA_CH12_AL2_READ_ADDR_LSB _u(0)

#define	DMA_CH12_AL2_READ_ADDR_MSB _u(31)

#define	DMA_CH12_AL2_READ_ADDR_OFFSET _u(0x00000328)

#define	DMA_CH12_AL2_READ_ADDR_RESET "-"

#define	DMA_CH12_AL2_TRANS_COUNT_ACCESS "RW"

#define	DMA_CH12_AL2_TRANS_COUNT_BITS _u(0xffffffff)

#define	DMA_CH12_AL2_TRANS_COUNT_LSB _u(0)

#define	DMA_CH12_AL2_TRANS_COUNT_MSB _u(31)

#define	DMA_CH12_AL2_TRANS_COUNT_OFFSET _u(0x00000324)

#define	DMA_CH12_AL2_TRANS_COUNT_RESET "-"

#define	DMA_CH12_AL2_WRITE_ADDR_TRIG_ACCESS "RW"

#define	DMA_CH12_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff)

#define	DMA_CH12_AL2_WRITE_ADDR_TRIG_LSB _u(0)

#define	DMA_CH12_AL2_WRITE_ADDR_TRIG_MSB _u(31)

#define	DMA_CH12_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x0000032c)

#define	DMA_CH12_AL2_WRITE_ADDR_TRIG_RESET "-"

#define	DMA_CH12_AL3_CTRL_ACCESS "RW"

#define	DMA_CH12_AL3_CTRL_BITS _u(0xffffffff)

#define	DMA_CH12_AL3_CTRL_LSB _u(0)

#define	DMA_CH12_AL3_CTRL_MSB _u(31)

#define	DMA_CH12_AL3_CTRL_OFFSET _u(0x00000330)

#define	DMA_CH12_AL3_CTRL_RESET "-"

#define	DMA_CH12_AL3_READ_ADDR_TRIG_ACCESS "RW"

#define	DMA_CH12_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff)

#define	DMA_CH12_AL3_READ_ADDR_TRIG_LSB _u(0)

#define	DMA_CH12_AL3_READ_ADDR_TRIG_MSB _u(31)

#define	DMA_CH12_AL3_READ_ADDR_TRIG_OFFSET _u(0x0000033c)

#define	DMA_CH12_AL3_READ_ADDR_TRIG_RESET "-"

#define	DMA_CH12_AL3_TRANS_COUNT_ACCESS "RW"

#define	DMA_CH12_AL3_TRANS_COUNT_BITS _u(0xffffffff)

#define	DMA_CH12_AL3_TRANS_COUNT_LSB _u(0)

#define	DMA_CH12_AL3_TRANS_COUNT_MSB _u(31)

#define	DMA_CH12_AL3_TRANS_COUNT_OFFSET _u(0x00000338)

#define	DMA_CH12_AL3_TRANS_COUNT_RESET "-"

#define	DMA_CH12_AL3_WRITE_ADDR_ACCESS "RW"

#define	DMA_CH12_AL3_WRITE_ADDR_BITS _u(0xffffffff)

#define	DMA_CH12_AL3_WRITE_ADDR_LSB _u(0)

#define	DMA_CH12_AL3_WRITE_ADDR_MSB _u(31)

#define	DMA_CH12_AL3_WRITE_ADDR_OFFSET _u(0x00000334)

#define	DMA_CH12_AL3_WRITE_ADDR_RESET "-"

#define	DMA_CH12_CTRL_TRIG_AHB_ERROR_ACCESS "RO"

#define	DMA_CH12_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000)

#define	DMA_CH12_CTRL_TRIG_AHB_ERROR_LSB _u(31)

#define	DMA_CH12_CTRL_TRIG_AHB_ERROR_MSB _u(31)

#define	DMA_CH12_CTRL_TRIG_AHB_ERROR_RESET _u(0x0)

#define	DMA_CH12_CTRL_TRIG_BITS _u(0xe7ffffff)

#define	DMA_CH12_CTRL_TRIG_BSWAP_ACCESS "RW"

#define	DMA_CH12_CTRL_TRIG_BSWAP_BITS _u(0x01000000)

#define	DMA_CH12_CTRL_TRIG_BSWAP_LSB _u(24)

#define	DMA_CH12_CTRL_TRIG_BSWAP_MSB _u(24)

#define	DMA_CH12_CTRL_TRIG_BSWAP_RESET _u(0x0)

#define	DMA_CH12_CTRL_TRIG_BUSY_ACCESS "RO"

#define	DMA_CH12_CTRL_TRIG_BUSY_BITS _u(0x04000000)

#define	DMA_CH12_CTRL_TRIG_BUSY_LSB _u(26)

#define	DMA_CH12_CTRL_TRIG_BUSY_MSB _u(26)

#define	DMA_CH12_CTRL_TRIG_BUSY_RESET _u(0x0)

#define	DMA_CH12_CTRL_TRIG_CHAIN_TO_ACCESS "RW"

#define	DMA_CH12_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000)

#define	DMA_CH12_CTRL_TRIG_CHAIN_TO_LSB _u(13)

#define	DMA_CH12_CTRL_TRIG_CHAIN_TO_MSB _u(16)

#define	DMA_CH12_CTRL_TRIG_CHAIN_TO_RESET _u(0x0)

#define	DMA_CH12_CTRL_TRIG_DATA_SIZE_ACCESS "RW"

#define	DMA_CH12_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c)

#define	DMA_CH12_CTRL_TRIG_DATA_SIZE_LSB _u(2)

#define	DMA_CH12_CTRL_TRIG_DATA_SIZE_MSB _u(3)

#define	DMA_CH12_CTRL_TRIG_DATA_SIZE_RESET _u(0x0)

#define	DMA_CH12_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0)

#define	DMA_CH12_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1)

#define	DMA_CH12_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2)

#define	DMA_CH12_CTRL_TRIG_EN_ACCESS "RW"

#define	DMA_CH12_CTRL_TRIG_EN_BITS _u(0x00000001)

#define	DMA_CH12_CTRL_TRIG_EN_LSB _u(0)

#define	DMA_CH12_CTRL_TRIG_EN_MSB _u(0)

#define	DMA_CH12_CTRL_TRIG_EN_RESET _u(0x0)

#define	DMA_CH12_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW"

#define	DMA_CH12_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002)

#define	DMA_CH12_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1)

#define	DMA_CH12_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1)

#define	DMA_CH12_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0)

#define	DMA_CH12_CTRL_TRIG_INCR_READ_ACCESS "RW"

#define	DMA_CH12_CTRL_TRIG_INCR_READ_BITS _u(0x00000010)

#define	DMA_CH12_CTRL_TRIG_INCR_READ_LSB _u(4)

#define	DMA_CH12_CTRL_TRIG_INCR_READ_MSB _u(4)

#define	DMA_CH12_CTRL_TRIG_INCR_READ_RESET _u(0x0)

#define	DMA_CH12_CTRL_TRIG_INCR_READ_REV_ACCESS "RW"

#define	DMA_CH12_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020)

#define	DMA_CH12_CTRL_TRIG_INCR_READ_REV_LSB _u(5)

#define	DMA_CH12_CTRL_TRIG_INCR_READ_REV_MSB _u(5)

#define	DMA_CH12_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0)

#define	DMA_CH12_CTRL_TRIG_INCR_WRITE_ACCESS "RW"

#define	DMA_CH12_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040)

#define	DMA_CH12_CTRL_TRIG_INCR_WRITE_LSB _u(6)

#define	DMA_CH12_CTRL_TRIG_INCR_WRITE_MSB _u(6)

#define	DMA_CH12_CTRL_TRIG_INCR_WRITE_RESET _u(0x0)

#define	DMA_CH12_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW"

#define	DMA_CH12_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080)

#define	DMA_CH12_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7)

#define	DMA_CH12_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7)

#define	DMA_CH12_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0)

#define	DMA_CH12_CTRL_TRIG_IRQ_QUIET_ACCESS "RW"

#define	DMA_CH12_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000)

#define	DMA_CH12_CTRL_TRIG_IRQ_QUIET_LSB _u(23)

#define	DMA_CH12_CTRL_TRIG_IRQ_QUIET_MSB _u(23)

#define	DMA_CH12_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0)

#define	DMA_CH12_CTRL_TRIG_OFFSET _u(0x0000030c)

#define	DMA_CH12_CTRL_TRIG_READ_ERROR_ACCESS "WC"

#define	DMA_CH12_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000)

#define	DMA_CH12_CTRL_TRIG_READ_ERROR_LSB _u(30)

#define	DMA_CH12_CTRL_TRIG_READ_ERROR_MSB _u(30)

#define	DMA_CH12_CTRL_TRIG_READ_ERROR_RESET _u(0x0)

#define	DMA_CH12_CTRL_TRIG_RESET _u(0x00000000)

#define	DMA_CH12_CTRL_TRIG_RING_SEL_ACCESS "RW"

#define	DMA_CH12_CTRL_TRIG_RING_SEL_BITS _u(0x00001000)

#define	DMA_CH12_CTRL_TRIG_RING_SEL_LSB _u(12)

#define	DMA_CH12_CTRL_TRIG_RING_SEL_MSB _u(12)

#define	DMA_CH12_CTRL_TRIG_RING_SEL_RESET _u(0x0)

#define	DMA_CH12_CTRL_TRIG_RING_SIZE_ACCESS "RW"

#define	DMA_CH12_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00)

#define	DMA_CH12_CTRL_TRIG_RING_SIZE_LSB _u(8)

#define	DMA_CH12_CTRL_TRIG_RING_SIZE_MSB _u(11)

#define	DMA_CH12_CTRL_TRIG_RING_SIZE_RESET _u(0x0)

#define	DMA_CH12_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0)

#define	DMA_CH12_CTRL_TRIG_SNIFF_EN_ACCESS "RW"

#define	DMA_CH12_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000)

#define	DMA_CH12_CTRL_TRIG_SNIFF_EN_LSB _u(25)

#define	DMA_CH12_CTRL_TRIG_SNIFF_EN_MSB _u(25)

#define	DMA_CH12_CTRL_TRIG_SNIFF_EN_RESET _u(0x0)

#define	DMA_CH12_CTRL_TRIG_TREQ_SEL_ACCESS "RW"

#define	DMA_CH12_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000)

#define	DMA_CH12_CTRL_TRIG_TREQ_SEL_LSB _u(17)

#define	DMA_CH12_CTRL_TRIG_TREQ_SEL_MSB _u(22)

#define	DMA_CH12_CTRL_TRIG_TREQ_SEL_RESET _u(0x00)

#define	DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f)

#define	DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b)

#define	DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c)

#define	DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d)

#define	DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e)

#define	DMA_CH12_CTRL_TRIG_WRITE_ERROR_ACCESS "WC"

#define	DMA_CH12_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000)

#define	DMA_CH12_CTRL_TRIG_WRITE_ERROR_LSB _u(29)

#define	DMA_CH12_CTRL_TRIG_WRITE_ERROR_MSB _u(29)

#define	DMA_CH12_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0)

#define	DMA_CH12_DBG_CTDREQ_ACCESS "WC"

#define	DMA_CH12_DBG_CTDREQ_BITS _u(0x0000003f)

#define	DMA_CH12_DBG_CTDREQ_LSB _u(0)

#define	DMA_CH12_DBG_CTDREQ_MSB _u(5)

#define	DMA_CH12_DBG_CTDREQ_OFFSET _u(0x00000b00)

#define	DMA_CH12_DBG_CTDREQ_RESET _u(0x00000000)

#define	DMA_CH12_DBG_TCR_ACCESS "RO"

#define	DMA_CH12_DBG_TCR_BITS _u(0xffffffff)

#define	DMA_CH12_DBG_TCR_LSB _u(0)

#define	DMA_CH12_DBG_TCR_MSB _u(31)

#define	DMA_CH12_DBG_TCR_OFFSET _u(0x00000b04)

#define	DMA_CH12_DBG_TCR_RESET _u(0x00000000)

#define	DMA_CH12_READ_ADDR_ACCESS "RW"

#define	DMA_CH12_READ_ADDR_BITS _u(0xffffffff)

#define	DMA_CH12_READ_ADDR_LSB _u(0)

#define	DMA_CH12_READ_ADDR_MSB _u(31)

#define	DMA_CH12_READ_ADDR_OFFSET _u(0x00000300)

#define	DMA_CH12_READ_ADDR_RESET _u(0x00000000)

#define	DMA_CH12_TRANS_COUNT_BITS _u(0xffffffff)

#define	DMA_CH12_TRANS_COUNT_COUNT_ACCESS "RW"

#define	DMA_CH12_TRANS_COUNT_COUNT_BITS _u(0x0fffffff)

#define	DMA_CH12_TRANS_COUNT_COUNT_LSB _u(0)

#define	DMA_CH12_TRANS_COUNT_COUNT_MSB _u(27)

#define	DMA_CH12_TRANS_COUNT_COUNT_RESET _u(0x0000000)

#define	DMA_CH12_TRANS_COUNT_MODE_ACCESS "RW"

#define	DMA_CH12_TRANS_COUNT_MODE_BITS _u(0xf0000000)

#define	DMA_CH12_TRANS_COUNT_MODE_LSB _u(28)

#define	DMA_CH12_TRANS_COUNT_MODE_MSB _u(31)

#define	DMA_CH12_TRANS_COUNT_MODE_RESET _u(0x0)

#define	DMA_CH12_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf)

#define	DMA_CH12_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0)

#define	DMA_CH12_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1)

#define	DMA_CH12_TRANS_COUNT_OFFSET _u(0x00000308)

#define	DMA_CH12_TRANS_COUNT_RESET _u(0x00000000)

#define	DMA_CH12_WRITE_ADDR_ACCESS "RW"

#define	DMA_CH12_WRITE_ADDR_BITS _u(0xffffffff)

#define	DMA_CH12_WRITE_ADDR_LSB _u(0)

#define	DMA_CH12_WRITE_ADDR_MSB _u(31)

#define	DMA_CH12_WRITE_ADDR_OFFSET _u(0x00000304)

#define	DMA_CH12_WRITE_ADDR_RESET _u(0x00000000)

#define	DMA_CH13_AL1_CTRL_ACCESS "RW"

#define	DMA_CH13_AL1_CTRL_BITS _u(0xffffffff)

#define	DMA_CH13_AL1_CTRL_LSB _u(0)

#define	DMA_CH13_AL1_CTRL_MSB _u(31)

#define	DMA_CH13_AL1_CTRL_OFFSET _u(0x00000350)

#define	DMA_CH13_AL1_CTRL_RESET "-"

#define	DMA_CH13_AL1_READ_ADDR_ACCESS "RW"

#define	DMA_CH13_AL1_READ_ADDR_BITS _u(0xffffffff)

#define	DMA_CH13_AL1_READ_ADDR_LSB _u(0)

#define	DMA_CH13_AL1_READ_ADDR_MSB _u(31)

#define	DMA_CH13_AL1_READ_ADDR_OFFSET _u(0x00000354)

#define	DMA_CH13_AL1_READ_ADDR_RESET "-"

#define	DMA_CH13_AL1_TRANS_COUNT_TRIG_ACCESS "RW"

#define	DMA_CH13_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff)

#define	DMA_CH13_AL1_TRANS_COUNT_TRIG_LSB _u(0)

#define	DMA_CH13_AL1_TRANS_COUNT_TRIG_MSB _u(31)

#define	DMA_CH13_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000035c)

#define	DMA_CH13_AL1_TRANS_COUNT_TRIG_RESET "-"

#define	DMA_CH13_AL1_WRITE_ADDR_ACCESS "RW"

#define	DMA_CH13_AL1_WRITE_ADDR_BITS _u(0xffffffff)

#define	DMA_CH13_AL1_WRITE_ADDR_LSB _u(0)

#define	DMA_CH13_AL1_WRITE_ADDR_MSB _u(31)

#define	DMA_CH13_AL1_WRITE_ADDR_OFFSET _u(0x00000358)

#define	DMA_CH13_AL1_WRITE_ADDR_RESET "-"

#define	DMA_CH13_AL2_CTRL_ACCESS "RW"

#define	DMA_CH13_AL2_CTRL_BITS _u(0xffffffff)

#define	DMA_CH13_AL2_CTRL_LSB _u(0)

#define	DMA_CH13_AL2_CTRL_MSB _u(31)

#define	DMA_CH13_AL2_CTRL_OFFSET _u(0x00000360)

#define	DMA_CH13_AL2_CTRL_RESET "-"

#define	DMA_CH13_AL2_READ_ADDR_ACCESS "RW"

#define	DMA_CH13_AL2_READ_ADDR_BITS _u(0xffffffff)

#define	DMA_CH13_AL2_READ_ADDR_LSB _u(0)

#define	DMA_CH13_AL2_READ_ADDR_MSB _u(31)

#define	DMA_CH13_AL2_READ_ADDR_OFFSET _u(0x00000368)

#define	DMA_CH13_AL2_READ_ADDR_RESET "-"

#define	DMA_CH13_AL2_TRANS_COUNT_ACCESS "RW"

#define	DMA_CH13_AL2_TRANS_COUNT_BITS _u(0xffffffff)

#define	DMA_CH13_AL2_TRANS_COUNT_LSB _u(0)

#define	DMA_CH13_AL2_TRANS_COUNT_MSB _u(31)

#define	DMA_CH13_AL2_TRANS_COUNT_OFFSET _u(0x00000364)

#define	DMA_CH13_AL2_TRANS_COUNT_RESET "-"

#define	DMA_CH13_AL2_WRITE_ADDR_TRIG_ACCESS "RW"

#define	DMA_CH13_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff)

#define	DMA_CH13_AL2_WRITE_ADDR_TRIG_LSB _u(0)

#define	DMA_CH13_AL2_WRITE_ADDR_TRIG_MSB _u(31)

#define	DMA_CH13_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x0000036c)

#define	DMA_CH13_AL2_WRITE_ADDR_TRIG_RESET "-"

#define	DMA_CH13_AL3_CTRL_ACCESS "RW"

#define	DMA_CH13_AL3_CTRL_BITS _u(0xffffffff)

#define	DMA_CH13_AL3_CTRL_LSB _u(0)

#define	DMA_CH13_AL3_CTRL_MSB _u(31)

#define	DMA_CH13_AL3_CTRL_OFFSET _u(0x00000370)

#define	DMA_CH13_AL3_CTRL_RESET "-"

#define	DMA_CH13_AL3_READ_ADDR_TRIG_ACCESS "RW"

#define	DMA_CH13_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff)

#define	DMA_CH13_AL3_READ_ADDR_TRIG_LSB _u(0)

#define	DMA_CH13_AL3_READ_ADDR_TRIG_MSB _u(31)

#define	DMA_CH13_AL3_READ_ADDR_TRIG_OFFSET _u(0x0000037c)

#define	DMA_CH13_AL3_READ_ADDR_TRIG_RESET "-"

#define	DMA_CH13_AL3_TRANS_COUNT_ACCESS "RW"

#define	DMA_CH13_AL3_TRANS_COUNT_BITS _u(0xffffffff)

#define	DMA_CH13_AL3_TRANS_COUNT_LSB _u(0)

#define	DMA_CH13_AL3_TRANS_COUNT_MSB _u(31)

#define	DMA_CH13_AL3_TRANS_COUNT_OFFSET _u(0x00000378)

#define	DMA_CH13_AL3_TRANS_COUNT_RESET "-"

#define	DMA_CH13_AL3_WRITE_ADDR_ACCESS "RW"

#define	DMA_CH13_AL3_WRITE_ADDR_BITS _u(0xffffffff)

#define	DMA_CH13_AL3_WRITE_ADDR_LSB _u(0)

#define	DMA_CH13_AL3_WRITE_ADDR_MSB _u(31)

#define	DMA_CH13_AL3_WRITE_ADDR_OFFSET _u(0x00000374)

#define	DMA_CH13_AL3_WRITE_ADDR_RESET "-"

#define	DMA_CH13_CTRL_TRIG_AHB_ERROR_ACCESS "RO"

#define	DMA_CH13_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000)

#define	DMA_CH13_CTRL_TRIG_AHB_ERROR_LSB _u(31)

#define	DMA_CH13_CTRL_TRIG_AHB_ERROR_MSB _u(31)

#define	DMA_CH13_CTRL_TRIG_AHB_ERROR_RESET _u(0x0)

#define	DMA_CH13_CTRL_TRIG_BITS _u(0xe7ffffff)

#define	DMA_CH13_CTRL_TRIG_BSWAP_ACCESS "RW"

#define	DMA_CH13_CTRL_TRIG_BSWAP_BITS _u(0x01000000)

#define	DMA_CH13_CTRL_TRIG_BSWAP_LSB _u(24)

#define	DMA_CH13_CTRL_TRIG_BSWAP_MSB _u(24)

#define	DMA_CH13_CTRL_TRIG_BSWAP_RESET _u(0x0)

#define	DMA_CH13_CTRL_TRIG_BUSY_ACCESS "RO"

#define	DMA_CH13_CTRL_TRIG_BUSY_BITS _u(0x04000000)

#define	DMA_CH13_CTRL_TRIG_BUSY_LSB _u(26)

#define	DMA_CH13_CTRL_TRIG_BUSY_MSB _u(26)

#define	DMA_CH13_CTRL_TRIG_BUSY_RESET _u(0x0)

#define	DMA_CH13_CTRL_TRIG_CHAIN_TO_ACCESS "RW"

#define	DMA_CH13_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000)

#define	DMA_CH13_CTRL_TRIG_CHAIN_TO_LSB _u(13)

#define	DMA_CH13_CTRL_TRIG_CHAIN_TO_MSB _u(16)

#define	DMA_CH13_CTRL_TRIG_CHAIN_TO_RESET _u(0x0)

#define	DMA_CH13_CTRL_TRIG_DATA_SIZE_ACCESS "RW"

#define	DMA_CH13_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c)

#define	DMA_CH13_CTRL_TRIG_DATA_SIZE_LSB _u(2)

#define	DMA_CH13_CTRL_TRIG_DATA_SIZE_MSB _u(3)

#define	DMA_CH13_CTRL_TRIG_DATA_SIZE_RESET _u(0x0)

#define	DMA_CH13_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0)

#define	DMA_CH13_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1)

#define	DMA_CH13_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2)

#define	DMA_CH13_CTRL_TRIG_EN_ACCESS "RW"

#define	DMA_CH13_CTRL_TRIG_EN_BITS _u(0x00000001)

#define	DMA_CH13_CTRL_TRIG_EN_LSB _u(0)

#define	DMA_CH13_CTRL_TRIG_EN_MSB _u(0)

#define	DMA_CH13_CTRL_TRIG_EN_RESET _u(0x0)

#define	DMA_CH13_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW"

#define	DMA_CH13_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002)

#define	DMA_CH13_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1)

#define	DMA_CH13_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1)

#define	DMA_CH13_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0)

#define	DMA_CH13_CTRL_TRIG_INCR_READ_ACCESS "RW"

#define	DMA_CH13_CTRL_TRIG_INCR_READ_BITS _u(0x00000010)

#define	DMA_CH13_CTRL_TRIG_INCR_READ_LSB _u(4)

#define	DMA_CH13_CTRL_TRIG_INCR_READ_MSB _u(4)

#define	DMA_CH13_CTRL_TRIG_INCR_READ_RESET _u(0x0)

#define	DMA_CH13_CTRL_TRIG_INCR_READ_REV_ACCESS "RW"

#define	DMA_CH13_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020)

#define	DMA_CH13_CTRL_TRIG_INCR_READ_REV_LSB _u(5)

#define	DMA_CH13_CTRL_TRIG_INCR_READ_REV_MSB _u(5)

#define	DMA_CH13_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0)

#define	DMA_CH13_CTRL_TRIG_INCR_WRITE_ACCESS "RW"

#define	DMA_CH13_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040)

#define	DMA_CH13_CTRL_TRIG_INCR_WRITE_LSB _u(6)

#define	DMA_CH13_CTRL_TRIG_INCR_WRITE_MSB _u(6)

#define	DMA_CH13_CTRL_TRIG_INCR_WRITE_RESET _u(0x0)

#define	DMA_CH13_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW"

#define	DMA_CH13_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080)

#define	DMA_CH13_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7)

#define	DMA_CH13_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7)

#define	DMA_CH13_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0)

#define	DMA_CH13_CTRL_TRIG_IRQ_QUIET_ACCESS "RW"

#define	DMA_CH13_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000)

#define	DMA_CH13_CTRL_TRIG_IRQ_QUIET_LSB _u(23)

#define	DMA_CH13_CTRL_TRIG_IRQ_QUIET_MSB _u(23)

#define	DMA_CH13_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0)

#define	DMA_CH13_CTRL_TRIG_OFFSET _u(0x0000034c)

#define	DMA_CH13_CTRL_TRIG_READ_ERROR_ACCESS "WC"

#define	DMA_CH13_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000)

#define	DMA_CH13_CTRL_TRIG_READ_ERROR_LSB _u(30)

#define	DMA_CH13_CTRL_TRIG_READ_ERROR_MSB _u(30)

#define	DMA_CH13_CTRL_TRIG_READ_ERROR_RESET _u(0x0)

#define	DMA_CH13_CTRL_TRIG_RESET _u(0x00000000)

#define	DMA_CH13_CTRL_TRIG_RING_SEL_ACCESS "RW"

#define	DMA_CH13_CTRL_TRIG_RING_SEL_BITS _u(0x00001000)

#define	DMA_CH13_CTRL_TRIG_RING_SEL_LSB _u(12)

#define	DMA_CH13_CTRL_TRIG_RING_SEL_MSB _u(12)

#define	DMA_CH13_CTRL_TRIG_RING_SEL_RESET _u(0x0)

#define	DMA_CH13_CTRL_TRIG_RING_SIZE_ACCESS "RW"

#define	DMA_CH13_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00)

#define	DMA_CH13_CTRL_TRIG_RING_SIZE_LSB _u(8)

#define	DMA_CH13_CTRL_TRIG_RING_SIZE_MSB _u(11)

#define	DMA_CH13_CTRL_TRIG_RING_SIZE_RESET _u(0x0)

#define	DMA_CH13_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0)

#define	DMA_CH13_CTRL_TRIG_SNIFF_EN_ACCESS "RW"

#define	DMA_CH13_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000)

#define	DMA_CH13_CTRL_TRIG_SNIFF_EN_LSB _u(25)

#define	DMA_CH13_CTRL_TRIG_SNIFF_EN_MSB _u(25)

#define	DMA_CH13_CTRL_TRIG_SNIFF_EN_RESET _u(0x0)

#define	DMA_CH13_CTRL_TRIG_TREQ_SEL_ACCESS "RW"

#define	DMA_CH13_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000)

#define	DMA_CH13_CTRL_TRIG_TREQ_SEL_LSB _u(17)

#define	DMA_CH13_CTRL_TRIG_TREQ_SEL_MSB _u(22)

#define	DMA_CH13_CTRL_TRIG_TREQ_SEL_RESET _u(0x00)

#define	DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f)

#define	DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b)

#define	DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c)

#define	DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d)

#define	DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e)

#define	DMA_CH13_CTRL_TRIG_WRITE_ERROR_ACCESS "WC"

#define	DMA_CH13_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000)

#define	DMA_CH13_CTRL_TRIG_WRITE_ERROR_LSB _u(29)

#define	DMA_CH13_CTRL_TRIG_WRITE_ERROR_MSB _u(29)

#define	DMA_CH13_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0)

#define	DMA_CH13_DBG_CTDREQ_ACCESS "WC"

#define	DMA_CH13_DBG_CTDREQ_BITS _u(0x0000003f)

#define	DMA_CH13_DBG_CTDREQ_LSB _u(0)

#define	DMA_CH13_DBG_CTDREQ_MSB _u(5)

#define	DMA_CH13_DBG_CTDREQ_OFFSET _u(0x00000b40)

#define	DMA_CH13_DBG_CTDREQ_RESET _u(0x00000000)

#define	DMA_CH13_DBG_TCR_ACCESS "RO"

#define	DMA_CH13_DBG_TCR_BITS _u(0xffffffff)

#define	DMA_CH13_DBG_TCR_LSB _u(0)

#define	DMA_CH13_DBG_TCR_MSB _u(31)

#define	DMA_CH13_DBG_TCR_OFFSET _u(0x00000b44)

#define	DMA_CH13_DBG_TCR_RESET _u(0x00000000)

#define	DMA_CH13_READ_ADDR_ACCESS "RW"

#define	DMA_CH13_READ_ADDR_BITS _u(0xffffffff)

#define	DMA_CH13_READ_ADDR_LSB _u(0)

#define	DMA_CH13_READ_ADDR_MSB _u(31)

#define	DMA_CH13_READ_ADDR_OFFSET _u(0x00000340)

#define	DMA_CH13_READ_ADDR_RESET _u(0x00000000)

#define	DMA_CH13_TRANS_COUNT_BITS _u(0xffffffff)

#define	DMA_CH13_TRANS_COUNT_COUNT_ACCESS "RW"

#define	DMA_CH13_TRANS_COUNT_COUNT_BITS _u(0x0fffffff)

#define	DMA_CH13_TRANS_COUNT_COUNT_LSB _u(0)

#define	DMA_CH13_TRANS_COUNT_COUNT_MSB _u(27)

#define	DMA_CH13_TRANS_COUNT_COUNT_RESET _u(0x0000000)

#define	DMA_CH13_TRANS_COUNT_MODE_ACCESS "RW"

#define	DMA_CH13_TRANS_COUNT_MODE_BITS _u(0xf0000000)

#define	DMA_CH13_TRANS_COUNT_MODE_LSB _u(28)

#define	DMA_CH13_TRANS_COUNT_MODE_MSB _u(31)

#define	DMA_CH13_TRANS_COUNT_MODE_RESET _u(0x0)

#define	DMA_CH13_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf)

#define	DMA_CH13_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0)

#define	DMA_CH13_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1)

#define	DMA_CH13_TRANS_COUNT_OFFSET _u(0x00000348)

#define	DMA_CH13_TRANS_COUNT_RESET _u(0x00000000)

#define	DMA_CH13_WRITE_ADDR_ACCESS "RW"

#define	DMA_CH13_WRITE_ADDR_BITS _u(0xffffffff)

#define	DMA_CH13_WRITE_ADDR_LSB _u(0)

#define	DMA_CH13_WRITE_ADDR_MSB _u(31)

#define	DMA_CH13_WRITE_ADDR_OFFSET _u(0x00000344)

#define	DMA_CH13_WRITE_ADDR_RESET _u(0x00000000)

#define	DMA_CH14_AL1_CTRL_ACCESS "RW"

#define	DMA_CH14_AL1_CTRL_BITS _u(0xffffffff)

#define	DMA_CH14_AL1_CTRL_LSB _u(0)

#define	DMA_CH14_AL1_CTRL_MSB _u(31)

#define	DMA_CH14_AL1_CTRL_OFFSET _u(0x00000390)

#define	DMA_CH14_AL1_CTRL_RESET "-"

#define	DMA_CH14_AL1_READ_ADDR_ACCESS "RW"

#define	DMA_CH14_AL1_READ_ADDR_BITS _u(0xffffffff)

#define	DMA_CH14_AL1_READ_ADDR_LSB _u(0)

#define	DMA_CH14_AL1_READ_ADDR_MSB _u(31)

#define	DMA_CH14_AL1_READ_ADDR_OFFSET _u(0x00000394)

#define	DMA_CH14_AL1_READ_ADDR_RESET "-"

#define	DMA_CH14_AL1_TRANS_COUNT_TRIG_ACCESS "RW"

#define	DMA_CH14_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff)

#define	DMA_CH14_AL1_TRANS_COUNT_TRIG_LSB _u(0)

#define	DMA_CH14_AL1_TRANS_COUNT_TRIG_MSB _u(31)

#define	DMA_CH14_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000039c)

#define	DMA_CH14_AL1_TRANS_COUNT_TRIG_RESET "-"

#define	DMA_CH14_AL1_WRITE_ADDR_ACCESS "RW"

#define	DMA_CH14_AL1_WRITE_ADDR_BITS _u(0xffffffff)

#define	DMA_CH14_AL1_WRITE_ADDR_LSB _u(0)

#define	DMA_CH14_AL1_WRITE_ADDR_MSB _u(31)

#define	DMA_CH14_AL1_WRITE_ADDR_OFFSET _u(0x00000398)

#define	DMA_CH14_AL1_WRITE_ADDR_RESET "-"

#define	DMA_CH14_AL2_CTRL_ACCESS "RW"

#define	DMA_CH14_AL2_CTRL_BITS _u(0xffffffff)

#define	DMA_CH14_AL2_CTRL_LSB _u(0)

#define	DMA_CH14_AL2_CTRL_MSB _u(31)

#define	DMA_CH14_AL2_CTRL_OFFSET _u(0x000003a0)

#define	DMA_CH14_AL2_CTRL_RESET "-"

#define	DMA_CH14_AL2_READ_ADDR_ACCESS "RW"

#define	DMA_CH14_AL2_READ_ADDR_BITS _u(0xffffffff)

#define	DMA_CH14_AL2_READ_ADDR_LSB _u(0)

#define	DMA_CH14_AL2_READ_ADDR_MSB _u(31)

#define	DMA_CH14_AL2_READ_ADDR_OFFSET _u(0x000003a8)

#define	DMA_CH14_AL2_READ_ADDR_RESET "-"

#define	DMA_CH14_AL2_TRANS_COUNT_ACCESS "RW"

#define	DMA_CH14_AL2_TRANS_COUNT_BITS _u(0xffffffff)

#define	DMA_CH14_AL2_TRANS_COUNT_LSB _u(0)

#define	DMA_CH14_AL2_TRANS_COUNT_MSB _u(31)

#define	DMA_CH14_AL2_TRANS_COUNT_OFFSET _u(0x000003a4)

#define	DMA_CH14_AL2_TRANS_COUNT_RESET "-"

#define	DMA_CH14_AL2_WRITE_ADDR_TRIG_ACCESS "RW"

#define	DMA_CH14_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff)

#define	DMA_CH14_AL2_WRITE_ADDR_TRIG_LSB _u(0)

#define	DMA_CH14_AL2_WRITE_ADDR_TRIG_MSB _u(31)

#define	DMA_CH14_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x000003ac)

#define	DMA_CH14_AL2_WRITE_ADDR_TRIG_RESET "-"

#define	DMA_CH14_AL3_CTRL_ACCESS "RW"

#define	DMA_CH14_AL3_CTRL_BITS _u(0xffffffff)

#define	DMA_CH14_AL3_CTRL_LSB _u(0)

#define	DMA_CH14_AL3_CTRL_MSB _u(31)

#define	DMA_CH14_AL3_CTRL_OFFSET _u(0x000003b0)

#define	DMA_CH14_AL3_CTRL_RESET "-"

#define	DMA_CH14_AL3_READ_ADDR_TRIG_ACCESS "RW"

#define	DMA_CH14_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff)

#define	DMA_CH14_AL3_READ_ADDR_TRIG_LSB _u(0)

#define	DMA_CH14_AL3_READ_ADDR_TRIG_MSB _u(31)

#define	DMA_CH14_AL3_READ_ADDR_TRIG_OFFSET _u(0x000003bc)

#define	DMA_CH14_AL3_READ_ADDR_TRIG_RESET "-"

#define	DMA_CH14_AL3_TRANS_COUNT_ACCESS "RW"

#define	DMA_CH14_AL3_TRANS_COUNT_BITS _u(0xffffffff)

#define	DMA_CH14_AL3_TRANS_COUNT_LSB _u(0)

#define	DMA_CH14_AL3_TRANS_COUNT_MSB _u(31)

#define	DMA_CH14_AL3_TRANS_COUNT_OFFSET _u(0x000003b8)

#define	DMA_CH14_AL3_TRANS_COUNT_RESET "-"

#define	DMA_CH14_AL3_WRITE_ADDR_ACCESS "RW"

#define	DMA_CH14_AL3_WRITE_ADDR_BITS _u(0xffffffff)

#define	DMA_CH14_AL3_WRITE_ADDR_LSB _u(0)

#define	DMA_CH14_AL3_WRITE_ADDR_MSB _u(31)

#define	DMA_CH14_AL3_WRITE_ADDR_OFFSET _u(0x000003b4)

#define	DMA_CH14_AL3_WRITE_ADDR_RESET "-"

#define	DMA_CH14_CTRL_TRIG_AHB_ERROR_ACCESS "RO"

#define	DMA_CH14_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000)

#define	DMA_CH14_CTRL_TRIG_AHB_ERROR_LSB _u(31)

#define	DMA_CH14_CTRL_TRIG_AHB_ERROR_MSB _u(31)

#define	DMA_CH14_CTRL_TRIG_AHB_ERROR_RESET _u(0x0)

#define	DMA_CH14_CTRL_TRIG_BITS _u(0xe7ffffff)

#define	DMA_CH14_CTRL_TRIG_BSWAP_ACCESS "RW"

#define	DMA_CH14_CTRL_TRIG_BSWAP_BITS _u(0x01000000)

#define	DMA_CH14_CTRL_TRIG_BSWAP_LSB _u(24)

#define	DMA_CH14_CTRL_TRIG_BSWAP_MSB _u(24)

#define	DMA_CH14_CTRL_TRIG_BSWAP_RESET _u(0x0)

#define	DMA_CH14_CTRL_TRIG_BUSY_ACCESS "RO"

#define	DMA_CH14_CTRL_TRIG_BUSY_BITS _u(0x04000000)

#define	DMA_CH14_CTRL_TRIG_BUSY_LSB _u(26)

#define	DMA_CH14_CTRL_TRIG_BUSY_MSB _u(26)

#define	DMA_CH14_CTRL_TRIG_BUSY_RESET _u(0x0)

#define	DMA_CH14_CTRL_TRIG_CHAIN_TO_ACCESS "RW"

#define	DMA_CH14_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000)

#define	DMA_CH14_CTRL_TRIG_CHAIN_TO_LSB _u(13)

#define	DMA_CH14_CTRL_TRIG_CHAIN_TO_MSB _u(16)

#define	DMA_CH14_CTRL_TRIG_CHAIN_TO_RESET _u(0x0)

#define	DMA_CH14_CTRL_TRIG_DATA_SIZE_ACCESS "RW"

#define	DMA_CH14_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c)

#define	DMA_CH14_CTRL_TRIG_DATA_SIZE_LSB _u(2)

#define	DMA_CH14_CTRL_TRIG_DATA_SIZE_MSB _u(3)

#define	DMA_CH14_CTRL_TRIG_DATA_SIZE_RESET _u(0x0)

#define	DMA_CH14_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0)

#define	DMA_CH14_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1)

#define	DMA_CH14_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2)

#define	DMA_CH14_CTRL_TRIG_EN_ACCESS "RW"

#define	DMA_CH14_CTRL_TRIG_EN_BITS _u(0x00000001)

#define	DMA_CH14_CTRL_TRIG_EN_LSB _u(0)

#define	DMA_CH14_CTRL_TRIG_EN_MSB _u(0)

#define	DMA_CH14_CTRL_TRIG_EN_RESET _u(0x0)

#define	DMA_CH14_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW"

#define	DMA_CH14_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002)

#define	DMA_CH14_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1)

#define	DMA_CH14_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1)

#define	DMA_CH14_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0)

#define	DMA_CH14_CTRL_TRIG_INCR_READ_ACCESS "RW"

#define	DMA_CH14_CTRL_TRIG_INCR_READ_BITS _u(0x00000010)

#define	DMA_CH14_CTRL_TRIG_INCR_READ_LSB _u(4)

#define	DMA_CH14_CTRL_TRIG_INCR_READ_MSB _u(4)

#define	DMA_CH14_CTRL_TRIG_INCR_READ_RESET _u(0x0)

#define	DMA_CH14_CTRL_TRIG_INCR_READ_REV_ACCESS "RW"

#define	DMA_CH14_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020)

#define	DMA_CH14_CTRL_TRIG_INCR_READ_REV_LSB _u(5)

#define	DMA_CH14_CTRL_TRIG_INCR_READ_REV_MSB _u(5)

#define	DMA_CH14_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0)

#define	DMA_CH14_CTRL_TRIG_INCR_WRITE_ACCESS "RW"

#define	DMA_CH14_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040)

#define	DMA_CH14_CTRL_TRIG_INCR_WRITE_LSB _u(6)

#define	DMA_CH14_CTRL_TRIG_INCR_WRITE_MSB _u(6)

#define	DMA_CH14_CTRL_TRIG_INCR_WRITE_RESET _u(0x0)

#define	DMA_CH14_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW"

#define	DMA_CH14_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080)

#define	DMA_CH14_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7)

#define	DMA_CH14_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7)

#define	DMA_CH14_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0)

#define	DMA_CH14_CTRL_TRIG_IRQ_QUIET_ACCESS "RW"

#define	DMA_CH14_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000)

#define	DMA_CH14_CTRL_TRIG_IRQ_QUIET_LSB _u(23)

#define	DMA_CH14_CTRL_TRIG_IRQ_QUIET_MSB _u(23)

#define	DMA_CH14_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0)

#define	DMA_CH14_CTRL_TRIG_OFFSET _u(0x0000038c)

#define	DMA_CH14_CTRL_TRIG_READ_ERROR_ACCESS "WC"

#define	DMA_CH14_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000)

#define	DMA_CH14_CTRL_TRIG_READ_ERROR_LSB _u(30)

#define	DMA_CH14_CTRL_TRIG_READ_ERROR_MSB _u(30)

#define	DMA_CH14_CTRL_TRIG_READ_ERROR_RESET _u(0x0)

#define	DMA_CH14_CTRL_TRIG_RESET _u(0x00000000)

#define	DMA_CH14_CTRL_TRIG_RING_SEL_ACCESS "RW"

#define	DMA_CH14_CTRL_TRIG_RING_SEL_BITS _u(0x00001000)

#define	DMA_CH14_CTRL_TRIG_RING_SEL_LSB _u(12)

#define	DMA_CH14_CTRL_TRIG_RING_SEL_MSB _u(12)

#define	DMA_CH14_CTRL_TRIG_RING_SEL_RESET _u(0x0)

#define	DMA_CH14_CTRL_TRIG_RING_SIZE_ACCESS "RW"

#define	DMA_CH14_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00)

#define	DMA_CH14_CTRL_TRIG_RING_SIZE_LSB _u(8)

#define	DMA_CH14_CTRL_TRIG_RING_SIZE_MSB _u(11)

#define	DMA_CH14_CTRL_TRIG_RING_SIZE_RESET _u(0x0)

#define	DMA_CH14_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0)

#define	DMA_CH14_CTRL_TRIG_SNIFF_EN_ACCESS "RW"

#define	DMA_CH14_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000)

#define	DMA_CH14_CTRL_TRIG_SNIFF_EN_LSB _u(25)

#define	DMA_CH14_CTRL_TRIG_SNIFF_EN_MSB _u(25)

#define	DMA_CH14_CTRL_TRIG_SNIFF_EN_RESET _u(0x0)

#define	DMA_CH14_CTRL_TRIG_TREQ_SEL_ACCESS "RW"

#define	DMA_CH14_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000)

#define	DMA_CH14_CTRL_TRIG_TREQ_SEL_LSB _u(17)

#define	DMA_CH14_CTRL_TRIG_TREQ_SEL_MSB _u(22)

#define	DMA_CH14_CTRL_TRIG_TREQ_SEL_RESET _u(0x00)

#define	DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f)

#define	DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b)

#define	DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c)

#define	DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d)

#define	DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e)

#define	DMA_CH14_CTRL_TRIG_WRITE_ERROR_ACCESS "WC"

#define	DMA_CH14_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000)

#define	DMA_CH14_CTRL_TRIG_WRITE_ERROR_LSB _u(29)

#define	DMA_CH14_CTRL_TRIG_WRITE_ERROR_MSB _u(29)

#define	DMA_CH14_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0)

#define	DMA_CH14_DBG_CTDREQ_ACCESS "WC"

#define	DMA_CH14_DBG_CTDREQ_BITS _u(0x0000003f)

#define	DMA_CH14_DBG_CTDREQ_LSB _u(0)

#define	DMA_CH14_DBG_CTDREQ_MSB _u(5)

#define	DMA_CH14_DBG_CTDREQ_OFFSET _u(0x00000b80)

#define	DMA_CH14_DBG_CTDREQ_RESET _u(0x00000000)

#define	DMA_CH14_DBG_TCR_ACCESS "RO"

#define	DMA_CH14_DBG_TCR_BITS _u(0xffffffff)

#define	DMA_CH14_DBG_TCR_LSB _u(0)

#define	DMA_CH14_DBG_TCR_MSB _u(31)

#define	DMA_CH14_DBG_TCR_OFFSET _u(0x00000b84)

#define	DMA_CH14_DBG_TCR_RESET _u(0x00000000)

#define	DMA_CH14_READ_ADDR_ACCESS "RW"

#define	DMA_CH14_READ_ADDR_BITS _u(0xffffffff)

#define	DMA_CH14_READ_ADDR_LSB _u(0)

#define	DMA_CH14_READ_ADDR_MSB _u(31)

#define	DMA_CH14_READ_ADDR_OFFSET _u(0x00000380)

#define	DMA_CH14_READ_ADDR_RESET _u(0x00000000)

#define	DMA_CH14_TRANS_COUNT_BITS _u(0xffffffff)

#define	DMA_CH14_TRANS_COUNT_COUNT_ACCESS "RW"

#define	DMA_CH14_TRANS_COUNT_COUNT_BITS _u(0x0fffffff)

#define	DMA_CH14_TRANS_COUNT_COUNT_LSB _u(0)

#define	DMA_CH14_TRANS_COUNT_COUNT_MSB _u(27)

#define	DMA_CH14_TRANS_COUNT_COUNT_RESET _u(0x0000000)

#define	DMA_CH14_TRANS_COUNT_MODE_ACCESS "RW"

#define	DMA_CH14_TRANS_COUNT_MODE_BITS _u(0xf0000000)

#define	DMA_CH14_TRANS_COUNT_MODE_LSB _u(28)

#define	DMA_CH14_TRANS_COUNT_MODE_MSB _u(31)

#define	DMA_CH14_TRANS_COUNT_MODE_RESET _u(0x0)

#define	DMA_CH14_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf)

#define	DMA_CH14_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0)

#define	DMA_CH14_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1)

#define	DMA_CH14_TRANS_COUNT_OFFSET _u(0x00000388)

#define	DMA_CH14_TRANS_COUNT_RESET _u(0x00000000)

#define	DMA_CH14_WRITE_ADDR_ACCESS "RW"

#define	DMA_CH14_WRITE_ADDR_BITS _u(0xffffffff)

#define	DMA_CH14_WRITE_ADDR_LSB _u(0)

#define	DMA_CH14_WRITE_ADDR_MSB _u(31)

#define	DMA_CH14_WRITE_ADDR_OFFSET _u(0x00000384)

#define	DMA_CH14_WRITE_ADDR_RESET _u(0x00000000)

#define	DMA_CH15_AL1_CTRL_ACCESS "RW"

#define	DMA_CH15_AL1_CTRL_BITS _u(0xffffffff)

#define	DMA_CH15_AL1_CTRL_LSB _u(0)

#define	DMA_CH15_AL1_CTRL_MSB _u(31)

#define	DMA_CH15_AL1_CTRL_OFFSET _u(0x000003d0)

#define	DMA_CH15_AL1_CTRL_RESET "-"

#define	DMA_CH15_AL1_READ_ADDR_ACCESS "RW"

#define	DMA_CH15_AL1_READ_ADDR_BITS _u(0xffffffff)

#define	DMA_CH15_AL1_READ_ADDR_LSB _u(0)

#define	DMA_CH15_AL1_READ_ADDR_MSB _u(31)

#define	DMA_CH15_AL1_READ_ADDR_OFFSET _u(0x000003d4)

#define	DMA_CH15_AL1_READ_ADDR_RESET "-"

#define	DMA_CH15_AL1_TRANS_COUNT_TRIG_ACCESS "RW"

#define	DMA_CH15_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff)

#define	DMA_CH15_AL1_TRANS_COUNT_TRIG_LSB _u(0)

#define	DMA_CH15_AL1_TRANS_COUNT_TRIG_MSB _u(31)

#define	DMA_CH15_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x000003dc)

#define	DMA_CH15_AL1_TRANS_COUNT_TRIG_RESET "-"

#define	DMA_CH15_AL1_WRITE_ADDR_ACCESS "RW"

#define	DMA_CH15_AL1_WRITE_ADDR_BITS _u(0xffffffff)

#define	DMA_CH15_AL1_WRITE_ADDR_LSB _u(0)

#define	DMA_CH15_AL1_WRITE_ADDR_MSB _u(31)

#define	DMA_CH15_AL1_WRITE_ADDR_OFFSET _u(0x000003d8)

#define	DMA_CH15_AL1_WRITE_ADDR_RESET "-"

#define	DMA_CH15_AL2_CTRL_ACCESS "RW"

#define	DMA_CH15_AL2_CTRL_BITS _u(0xffffffff)

#define	DMA_CH15_AL2_CTRL_LSB _u(0)

#define	DMA_CH15_AL2_CTRL_MSB _u(31)

#define	DMA_CH15_AL2_CTRL_OFFSET _u(0x000003e0)

#define	DMA_CH15_AL2_CTRL_RESET "-"

#define	DMA_CH15_AL2_READ_ADDR_ACCESS "RW"

#define	DMA_CH15_AL2_READ_ADDR_BITS _u(0xffffffff)

#define	DMA_CH15_AL2_READ_ADDR_LSB _u(0)

#define	DMA_CH15_AL2_READ_ADDR_MSB _u(31)

#define	DMA_CH15_AL2_READ_ADDR_OFFSET _u(0x000003e8)

#define	DMA_CH15_AL2_READ_ADDR_RESET "-"

#define	DMA_CH15_AL2_TRANS_COUNT_ACCESS "RW"

#define	DMA_CH15_AL2_TRANS_COUNT_BITS _u(0xffffffff)

#define	DMA_CH15_AL2_TRANS_COUNT_LSB _u(0)

#define	DMA_CH15_AL2_TRANS_COUNT_MSB _u(31)

#define	DMA_CH15_AL2_TRANS_COUNT_OFFSET _u(0x000003e4)

#define	DMA_CH15_AL2_TRANS_COUNT_RESET "-"

#define	DMA_CH15_AL2_WRITE_ADDR_TRIG_ACCESS "RW"

#define	DMA_CH15_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff)

#define	DMA_CH15_AL2_WRITE_ADDR_TRIG_LSB _u(0)

#define	DMA_CH15_AL2_WRITE_ADDR_TRIG_MSB _u(31)

#define	DMA_CH15_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x000003ec)

#define	DMA_CH15_AL2_WRITE_ADDR_TRIG_RESET "-"

#define	DMA_CH15_AL3_CTRL_ACCESS "RW"

#define	DMA_CH15_AL3_CTRL_BITS _u(0xffffffff)

#define	DMA_CH15_AL3_CTRL_LSB _u(0)

#define	DMA_CH15_AL3_CTRL_MSB _u(31)

#define	DMA_CH15_AL3_CTRL_OFFSET _u(0x000003f0)

#define	DMA_CH15_AL3_CTRL_RESET "-"

#define	DMA_CH15_AL3_READ_ADDR_TRIG_ACCESS "RW"

#define	DMA_CH15_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff)

#define	DMA_CH15_AL3_READ_ADDR_TRIG_LSB _u(0)

#define	DMA_CH15_AL3_READ_ADDR_TRIG_MSB _u(31)

#define	DMA_CH15_AL3_READ_ADDR_TRIG_OFFSET _u(0x000003fc)

#define	DMA_CH15_AL3_READ_ADDR_TRIG_RESET "-"

#define	DMA_CH15_AL3_TRANS_COUNT_ACCESS "RW"

#define	DMA_CH15_AL3_TRANS_COUNT_BITS _u(0xffffffff)

#define	DMA_CH15_AL3_TRANS_COUNT_LSB _u(0)

#define	DMA_CH15_AL3_TRANS_COUNT_MSB _u(31)

#define	DMA_CH15_AL3_TRANS_COUNT_OFFSET _u(0x000003f8)

#define	DMA_CH15_AL3_TRANS_COUNT_RESET "-"

#define	DMA_CH15_AL3_WRITE_ADDR_ACCESS "RW"

#define	DMA_CH15_AL3_WRITE_ADDR_BITS _u(0xffffffff)

#define	DMA_CH15_AL3_WRITE_ADDR_LSB _u(0)

#define	DMA_CH15_AL3_WRITE_ADDR_MSB _u(31)

#define	DMA_CH15_AL3_WRITE_ADDR_OFFSET _u(0x000003f4)

#define	DMA_CH15_AL3_WRITE_ADDR_RESET "-"

#define	DMA_CH15_CTRL_TRIG_AHB_ERROR_ACCESS "RO"

#define	DMA_CH15_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000)

#define	DMA_CH15_CTRL_TRIG_AHB_ERROR_LSB _u(31)

#define	DMA_CH15_CTRL_TRIG_AHB_ERROR_MSB _u(31)

#define	DMA_CH15_CTRL_TRIG_AHB_ERROR_RESET _u(0x0)

#define	DMA_CH15_CTRL_TRIG_BITS _u(0xe7ffffff)

#define	DMA_CH15_CTRL_TRIG_BSWAP_ACCESS "RW"

#define	DMA_CH15_CTRL_TRIG_BSWAP_BITS _u(0x01000000)

#define	DMA_CH15_CTRL_TRIG_BSWAP_LSB _u(24)

#define	DMA_CH15_CTRL_TRIG_BSWAP_MSB _u(24)

#define	DMA_CH15_CTRL_TRIG_BSWAP_RESET _u(0x0)

#define	DMA_CH15_CTRL_TRIG_BUSY_ACCESS "RO"

#define	DMA_CH15_CTRL_TRIG_BUSY_BITS _u(0x04000000)

#define	DMA_CH15_CTRL_TRIG_BUSY_LSB _u(26)

#define	DMA_CH15_CTRL_TRIG_BUSY_MSB _u(26)

#define	DMA_CH15_CTRL_TRIG_BUSY_RESET _u(0x0)

#define	DMA_CH15_CTRL_TRIG_CHAIN_TO_ACCESS "RW"

#define	DMA_CH15_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000)

#define	DMA_CH15_CTRL_TRIG_CHAIN_TO_LSB _u(13)

#define	DMA_CH15_CTRL_TRIG_CHAIN_TO_MSB _u(16)

#define	DMA_CH15_CTRL_TRIG_CHAIN_TO_RESET _u(0x0)

#define	DMA_CH15_CTRL_TRIG_DATA_SIZE_ACCESS "RW"

#define	DMA_CH15_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c)

#define	DMA_CH15_CTRL_TRIG_DATA_SIZE_LSB _u(2)

#define	DMA_CH15_CTRL_TRIG_DATA_SIZE_MSB _u(3)

#define	DMA_CH15_CTRL_TRIG_DATA_SIZE_RESET _u(0x0)

#define	DMA_CH15_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0)

#define	DMA_CH15_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1)

#define	DMA_CH15_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2)

#define	DMA_CH15_CTRL_TRIG_EN_ACCESS "RW"

#define	DMA_CH15_CTRL_TRIG_EN_BITS _u(0x00000001)

#define	DMA_CH15_CTRL_TRIG_EN_LSB _u(0)

#define	DMA_CH15_CTRL_TRIG_EN_MSB _u(0)

#define	DMA_CH15_CTRL_TRIG_EN_RESET _u(0x0)

#define	DMA_CH15_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW"

#define	DMA_CH15_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002)

#define	DMA_CH15_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1)

#define	DMA_CH15_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1)

#define	DMA_CH15_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0)

#define	DMA_CH15_CTRL_TRIG_INCR_READ_ACCESS "RW"

#define	DMA_CH15_CTRL_TRIG_INCR_READ_BITS _u(0x00000010)

#define	DMA_CH15_CTRL_TRIG_INCR_READ_LSB _u(4)

#define	DMA_CH15_CTRL_TRIG_INCR_READ_MSB _u(4)

#define	DMA_CH15_CTRL_TRIG_INCR_READ_RESET _u(0x0)

#define	DMA_CH15_CTRL_TRIG_INCR_READ_REV_ACCESS "RW"

#define	DMA_CH15_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020)

#define	DMA_CH15_CTRL_TRIG_INCR_READ_REV_LSB _u(5)

#define	DMA_CH15_CTRL_TRIG_INCR_READ_REV_MSB _u(5)

#define	DMA_CH15_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0)

#define	DMA_CH15_CTRL_TRIG_INCR_WRITE_ACCESS "RW"

#define	DMA_CH15_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040)

#define	DMA_CH15_CTRL_TRIG_INCR_WRITE_LSB _u(6)

#define	DMA_CH15_CTRL_TRIG_INCR_WRITE_MSB _u(6)

#define	DMA_CH15_CTRL_TRIG_INCR_WRITE_RESET _u(0x0)

#define	DMA_CH15_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW"

#define	DMA_CH15_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080)

#define	DMA_CH15_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7)

#define	DMA_CH15_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7)

#define	DMA_CH15_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0)

#define	DMA_CH15_CTRL_TRIG_IRQ_QUIET_ACCESS "RW"

#define	DMA_CH15_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000)

#define	DMA_CH15_CTRL_TRIG_IRQ_QUIET_LSB _u(23)

#define	DMA_CH15_CTRL_TRIG_IRQ_QUIET_MSB _u(23)

#define	DMA_CH15_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0)

#define	DMA_CH15_CTRL_TRIG_OFFSET _u(0x000003cc)

#define	DMA_CH15_CTRL_TRIG_READ_ERROR_ACCESS "WC"

#define	DMA_CH15_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000)

#define	DMA_CH15_CTRL_TRIG_READ_ERROR_LSB _u(30)

#define	DMA_CH15_CTRL_TRIG_READ_ERROR_MSB _u(30)

#define	DMA_CH15_CTRL_TRIG_READ_ERROR_RESET _u(0x0)

#define	DMA_CH15_CTRL_TRIG_RESET _u(0x00000000)

#define	DMA_CH15_CTRL_TRIG_RING_SEL_ACCESS "RW"

#define	DMA_CH15_CTRL_TRIG_RING_SEL_BITS _u(0x00001000)

#define	DMA_CH15_CTRL_TRIG_RING_SEL_LSB _u(12)

#define	DMA_CH15_CTRL_TRIG_RING_SEL_MSB _u(12)

#define	DMA_CH15_CTRL_TRIG_RING_SEL_RESET _u(0x0)

#define	DMA_CH15_CTRL_TRIG_RING_SIZE_ACCESS "RW"

#define	DMA_CH15_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00)

#define	DMA_CH15_CTRL_TRIG_RING_SIZE_LSB _u(8)

#define	DMA_CH15_CTRL_TRIG_RING_SIZE_MSB _u(11)

#define	DMA_CH15_CTRL_TRIG_RING_SIZE_RESET _u(0x0)

#define	DMA_CH15_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0)

#define	DMA_CH15_CTRL_TRIG_SNIFF_EN_ACCESS "RW"

#define	DMA_CH15_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000)

#define	DMA_CH15_CTRL_TRIG_SNIFF_EN_LSB _u(25)

#define	DMA_CH15_CTRL_TRIG_SNIFF_EN_MSB _u(25)

#define	DMA_CH15_CTRL_TRIG_SNIFF_EN_RESET _u(0x0)

#define	DMA_CH15_CTRL_TRIG_TREQ_SEL_ACCESS "RW"

#define	DMA_CH15_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000)

#define	DMA_CH15_CTRL_TRIG_TREQ_SEL_LSB _u(17)

#define	DMA_CH15_CTRL_TRIG_TREQ_SEL_MSB _u(22)

#define	DMA_CH15_CTRL_TRIG_TREQ_SEL_RESET _u(0x00)

#define	DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f)

#define	DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b)

#define	DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c)

#define	DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d)

#define	DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e)

#define	DMA_CH15_CTRL_TRIG_WRITE_ERROR_ACCESS "WC"

#define	DMA_CH15_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000)

#define	DMA_CH15_CTRL_TRIG_WRITE_ERROR_LSB _u(29)

#define	DMA_CH15_CTRL_TRIG_WRITE_ERROR_MSB _u(29)

#define	DMA_CH15_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0)

#define	DMA_CH15_DBG_CTDREQ_ACCESS "WC"

#define	DMA_CH15_DBG_CTDREQ_BITS _u(0x0000003f)

#define	DMA_CH15_DBG_CTDREQ_LSB _u(0)

#define	DMA_CH15_DBG_CTDREQ_MSB _u(5)

#define	DMA_CH15_DBG_CTDREQ_OFFSET _u(0x00000bc0)

#define	DMA_CH15_DBG_CTDREQ_RESET _u(0x00000000)

#define	DMA_CH15_DBG_TCR_ACCESS "RO"

#define	DMA_CH15_DBG_TCR_BITS _u(0xffffffff)

#define	DMA_CH15_DBG_TCR_LSB _u(0)

#define	DMA_CH15_DBG_TCR_MSB _u(31)

#define	DMA_CH15_DBG_TCR_OFFSET _u(0x00000bc4)

#define	DMA_CH15_DBG_TCR_RESET _u(0x00000000)

#define	DMA_CH15_READ_ADDR_ACCESS "RW"

#define	DMA_CH15_READ_ADDR_BITS _u(0xffffffff)

#define	DMA_CH15_READ_ADDR_LSB _u(0)

#define	DMA_CH15_READ_ADDR_MSB _u(31)

#define	DMA_CH15_READ_ADDR_OFFSET _u(0x000003c0)

#define	DMA_CH15_READ_ADDR_RESET _u(0x00000000)

#define	DMA_CH15_TRANS_COUNT_BITS _u(0xffffffff)

#define	DMA_CH15_TRANS_COUNT_COUNT_ACCESS "RW"

#define	DMA_CH15_TRANS_COUNT_COUNT_BITS _u(0x0fffffff)

#define	DMA_CH15_TRANS_COUNT_COUNT_LSB _u(0)

#define	DMA_CH15_TRANS_COUNT_COUNT_MSB _u(27)

#define	DMA_CH15_TRANS_COUNT_COUNT_RESET _u(0x0000000)

#define	DMA_CH15_TRANS_COUNT_MODE_ACCESS "RW"

#define	DMA_CH15_TRANS_COUNT_MODE_BITS _u(0xf0000000)

#define	DMA_CH15_TRANS_COUNT_MODE_LSB _u(28)

#define	DMA_CH15_TRANS_COUNT_MODE_MSB _u(31)

#define	DMA_CH15_TRANS_COUNT_MODE_RESET _u(0x0)

#define	DMA_CH15_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf)

#define	DMA_CH15_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0)

#define	DMA_CH15_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1)

#define	DMA_CH15_TRANS_COUNT_OFFSET _u(0x000003c8)

#define	DMA_CH15_TRANS_COUNT_RESET _u(0x00000000)

#define	DMA_CH15_WRITE_ADDR_ACCESS "RW"

#define	DMA_CH15_WRITE_ADDR_BITS _u(0xffffffff)

#define	DMA_CH15_WRITE_ADDR_LSB _u(0)

#define	DMA_CH15_WRITE_ADDR_MSB _u(31)

#define	DMA_CH15_WRITE_ADDR_OFFSET _u(0x000003c4)

#define	DMA_CH15_WRITE_ADDR_RESET _u(0x00000000)

#define	DMA_CH1_AL1_CTRL_ACCESS "RW"

#define	DMA_CH1_AL1_CTRL_BITS _u(0xffffffff)

#define	DMA_CH1_AL1_CTRL_LSB _u(0)

#define	DMA_CH1_AL1_CTRL_MSB _u(31)

#define	DMA_CH1_AL1_CTRL_OFFSET _u(0x00000050)

#define	DMA_CH1_AL1_CTRL_RESET "-"

#define	DMA_CH1_AL1_READ_ADDR_ACCESS "RW"

#define	DMA_CH1_AL1_READ_ADDR_BITS _u(0xffffffff)

#define	DMA_CH1_AL1_READ_ADDR_LSB _u(0)

#define	DMA_CH1_AL1_READ_ADDR_MSB _u(31)

#define	DMA_CH1_AL1_READ_ADDR_OFFSET _u(0x00000054)

#define	DMA_CH1_AL1_READ_ADDR_RESET "-"

#define	DMA_CH1_AL1_TRANS_COUNT_TRIG_ACCESS "RW"

#define	DMA_CH1_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff)

#define	DMA_CH1_AL1_TRANS_COUNT_TRIG_LSB _u(0)

#define	DMA_CH1_AL1_TRANS_COUNT_TRIG_MSB _u(31)

#define	DMA_CH1_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000005c)

#define	DMA_CH1_AL1_TRANS_COUNT_TRIG_RESET "-"

#define	DMA_CH1_AL1_WRITE_ADDR_ACCESS "RW"

#define	DMA_CH1_AL1_WRITE_ADDR_BITS _u(0xffffffff)

#define	DMA_CH1_AL1_WRITE_ADDR_LSB _u(0)

#define	DMA_CH1_AL1_WRITE_ADDR_MSB _u(31)

#define	DMA_CH1_AL1_WRITE_ADDR_OFFSET _u(0x00000058)

#define	DMA_CH1_AL1_WRITE_ADDR_RESET "-"

#define	DMA_CH1_AL2_CTRL_ACCESS "RW"

#define	DMA_CH1_AL2_CTRL_BITS _u(0xffffffff)

#define	DMA_CH1_AL2_CTRL_LSB _u(0)

#define	DMA_CH1_AL2_CTRL_MSB _u(31)

#define	DMA_CH1_AL2_CTRL_OFFSET _u(0x00000060)

#define	DMA_CH1_AL2_CTRL_RESET "-"

#define	DMA_CH1_AL2_READ_ADDR_ACCESS "RW"

#define	DMA_CH1_AL2_READ_ADDR_BITS _u(0xffffffff)

#define	DMA_CH1_AL2_READ_ADDR_LSB _u(0)

#define	DMA_CH1_AL2_READ_ADDR_MSB _u(31)

#define	DMA_CH1_AL2_READ_ADDR_OFFSET _u(0x00000068)

#define	DMA_CH1_AL2_READ_ADDR_RESET "-"

#define	DMA_CH1_AL2_TRANS_COUNT_ACCESS "RW"

#define	DMA_CH1_AL2_TRANS_COUNT_BITS _u(0xffffffff)

#define	DMA_CH1_AL2_TRANS_COUNT_LSB _u(0)

#define	DMA_CH1_AL2_TRANS_COUNT_MSB _u(31)

#define	DMA_CH1_AL2_TRANS_COUNT_OFFSET _u(0x00000064)

#define	DMA_CH1_AL2_TRANS_COUNT_RESET "-"

#define	DMA_CH1_AL2_WRITE_ADDR_TRIG_ACCESS "RW"

#define	DMA_CH1_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff)

#define	DMA_CH1_AL2_WRITE_ADDR_TRIG_LSB _u(0)

#define	DMA_CH1_AL2_WRITE_ADDR_TRIG_MSB _u(31)

#define	DMA_CH1_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x0000006c)

#define	DMA_CH1_AL2_WRITE_ADDR_TRIG_RESET "-"

#define	DMA_CH1_AL3_CTRL_ACCESS "RW"

#define	DMA_CH1_AL3_CTRL_BITS _u(0xffffffff)

#define	DMA_CH1_AL3_CTRL_LSB _u(0)

#define	DMA_CH1_AL3_CTRL_MSB _u(31)

#define	DMA_CH1_AL3_CTRL_OFFSET _u(0x00000070)

#define	DMA_CH1_AL3_CTRL_RESET "-"

#define	DMA_CH1_AL3_READ_ADDR_TRIG_ACCESS "RW"

#define	DMA_CH1_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff)

#define	DMA_CH1_AL3_READ_ADDR_TRIG_LSB _u(0)

#define	DMA_CH1_AL3_READ_ADDR_TRIG_MSB _u(31)

#define	DMA_CH1_AL3_READ_ADDR_TRIG_OFFSET _u(0x0000007c)

#define	DMA_CH1_AL3_READ_ADDR_TRIG_RESET "-"

#define	DMA_CH1_AL3_TRANS_COUNT_ACCESS "RW"

#define	DMA_CH1_AL3_TRANS_COUNT_BITS _u(0xffffffff)

#define	DMA_CH1_AL3_TRANS_COUNT_LSB _u(0)

#define	DMA_CH1_AL3_TRANS_COUNT_MSB _u(31)

#define	DMA_CH1_AL3_TRANS_COUNT_OFFSET _u(0x00000078)

#define	DMA_CH1_AL3_TRANS_COUNT_RESET "-"

#define	DMA_CH1_AL3_WRITE_ADDR_ACCESS "RW"

#define	DMA_CH1_AL3_WRITE_ADDR_BITS _u(0xffffffff)

#define	DMA_CH1_AL3_WRITE_ADDR_LSB _u(0)

#define	DMA_CH1_AL3_WRITE_ADDR_MSB _u(31)

#define	DMA_CH1_AL3_WRITE_ADDR_OFFSET _u(0x00000074)

#define	DMA_CH1_AL3_WRITE_ADDR_RESET "-"

#define	DMA_CH1_CTRL_TRIG_AHB_ERROR_ACCESS "RO"

#define	DMA_CH1_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000)

#define	DMA_CH1_CTRL_TRIG_AHB_ERROR_LSB _u(31)

#define	DMA_CH1_CTRL_TRIG_AHB_ERROR_MSB _u(31)

#define	DMA_CH1_CTRL_TRIG_AHB_ERROR_RESET _u(0x0)

#define	DMA_CH1_CTRL_TRIG_BITS _u(0xe7ffffff)

#define	DMA_CH1_CTRL_TRIG_BSWAP_ACCESS "RW"

#define	DMA_CH1_CTRL_TRIG_BSWAP_BITS _u(0x01000000)

#define	DMA_CH1_CTRL_TRIG_BSWAP_LSB _u(24)

#define	DMA_CH1_CTRL_TRIG_BSWAP_MSB _u(24)

#define	DMA_CH1_CTRL_TRIG_BSWAP_RESET _u(0x0)

#define	DMA_CH1_CTRL_TRIG_BUSY_ACCESS "RO"

#define	DMA_CH1_CTRL_TRIG_BUSY_BITS _u(0x04000000)

#define	DMA_CH1_CTRL_TRIG_BUSY_LSB _u(26)

#define	DMA_CH1_CTRL_TRIG_BUSY_MSB _u(26)

#define	DMA_CH1_CTRL_TRIG_BUSY_RESET _u(0x0)

#define	DMA_CH1_CTRL_TRIG_CHAIN_TO_ACCESS "RW"

#define	DMA_CH1_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000)

#define	DMA_CH1_CTRL_TRIG_CHAIN_TO_LSB _u(13)

#define	DMA_CH1_CTRL_TRIG_CHAIN_TO_MSB _u(16)

#define	DMA_CH1_CTRL_TRIG_CHAIN_TO_RESET _u(0x0)

#define	DMA_CH1_CTRL_TRIG_DATA_SIZE_ACCESS "RW"

#define	DMA_CH1_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c)

#define	DMA_CH1_CTRL_TRIG_DATA_SIZE_LSB _u(2)

#define	DMA_CH1_CTRL_TRIG_DATA_SIZE_MSB _u(3)

#define	DMA_CH1_CTRL_TRIG_DATA_SIZE_RESET _u(0x0)

#define	DMA_CH1_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0)

#define	DMA_CH1_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1)

#define	DMA_CH1_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2)

#define	DMA_CH1_CTRL_TRIG_EN_ACCESS "RW"

#define	DMA_CH1_CTRL_TRIG_EN_BITS _u(0x00000001)

#define	DMA_CH1_CTRL_TRIG_EN_LSB _u(0)

#define	DMA_CH1_CTRL_TRIG_EN_MSB _u(0)

#define	DMA_CH1_CTRL_TRIG_EN_RESET _u(0x0)

#define	DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW"

#define	DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002)

#define	DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1)

#define	DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1)

#define	DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0)

#define	DMA_CH1_CTRL_TRIG_INCR_READ_ACCESS "RW"

#define	DMA_CH1_CTRL_TRIG_INCR_READ_BITS _u(0x00000010)

#define	DMA_CH1_CTRL_TRIG_INCR_READ_LSB _u(4)

#define	DMA_CH1_CTRL_TRIG_INCR_READ_MSB _u(4)

#define	DMA_CH1_CTRL_TRIG_INCR_READ_RESET _u(0x0)

#define	DMA_CH1_CTRL_TRIG_INCR_READ_REV_ACCESS "RW"

#define	DMA_CH1_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020)

#define	DMA_CH1_CTRL_TRIG_INCR_READ_REV_LSB _u(5)

#define	DMA_CH1_CTRL_TRIG_INCR_READ_REV_MSB _u(5)

#define	DMA_CH1_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0)

#define	DMA_CH1_CTRL_TRIG_INCR_WRITE_ACCESS "RW"

#define	DMA_CH1_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040)

#define	DMA_CH1_CTRL_TRIG_INCR_WRITE_LSB _u(6)

#define	DMA_CH1_CTRL_TRIG_INCR_WRITE_MSB _u(6)

#define	DMA_CH1_CTRL_TRIG_INCR_WRITE_RESET _u(0x0)

#define	DMA_CH1_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW"

#define	DMA_CH1_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080)

#define	DMA_CH1_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7)

#define	DMA_CH1_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7)

#define	DMA_CH1_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0)

#define	DMA_CH1_CTRL_TRIG_IRQ_QUIET_ACCESS "RW"

#define	DMA_CH1_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000)

#define	DMA_CH1_CTRL_TRIG_IRQ_QUIET_LSB _u(23)

#define	DMA_CH1_CTRL_TRIG_IRQ_QUIET_MSB _u(23)

#define	DMA_CH1_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0)

#define	DMA_CH1_CTRL_TRIG_OFFSET _u(0x0000004c)

#define	DMA_CH1_CTRL_TRIG_READ_ERROR_ACCESS "WC"

#define	DMA_CH1_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000)

#define	DMA_CH1_CTRL_TRIG_READ_ERROR_LSB _u(30)

#define	DMA_CH1_CTRL_TRIG_READ_ERROR_MSB _u(30)

#define	DMA_CH1_CTRL_TRIG_READ_ERROR_RESET _u(0x0)

#define	DMA_CH1_CTRL_TRIG_RESET _u(0x00000000)

#define	DMA_CH1_CTRL_TRIG_RING_SEL_ACCESS "RW"

#define	DMA_CH1_CTRL_TRIG_RING_SEL_BITS _u(0x00001000)

#define	DMA_CH1_CTRL_TRIG_RING_SEL_LSB _u(12)

#define	DMA_CH1_CTRL_TRIG_RING_SEL_MSB _u(12)

#define	DMA_CH1_CTRL_TRIG_RING_SEL_RESET _u(0x0)

#define	DMA_CH1_CTRL_TRIG_RING_SIZE_ACCESS "RW"

#define	DMA_CH1_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00)

#define	DMA_CH1_CTRL_TRIG_RING_SIZE_LSB _u(8)

#define	DMA_CH1_CTRL_TRIG_RING_SIZE_MSB _u(11)

#define	DMA_CH1_CTRL_TRIG_RING_SIZE_RESET _u(0x0)

#define	DMA_CH1_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0)

#define	DMA_CH1_CTRL_TRIG_SNIFF_EN_ACCESS "RW"

#define	DMA_CH1_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000)

#define	DMA_CH1_CTRL_TRIG_SNIFF_EN_LSB _u(25)

#define	DMA_CH1_CTRL_TRIG_SNIFF_EN_MSB _u(25)

#define	DMA_CH1_CTRL_TRIG_SNIFF_EN_RESET _u(0x0)

#define	DMA_CH1_CTRL_TRIG_TREQ_SEL_ACCESS "RW"

#define	DMA_CH1_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000)

#define	DMA_CH1_CTRL_TRIG_TREQ_SEL_LSB _u(17)

#define	DMA_CH1_CTRL_TRIG_TREQ_SEL_MSB _u(22)

#define	DMA_CH1_CTRL_TRIG_TREQ_SEL_RESET _u(0x00)

#define	DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f)

#define	DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b)

#define	DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c)

#define	DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d)

#define	DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e)

#define	DMA_CH1_CTRL_TRIG_WRITE_ERROR_ACCESS "WC"

#define	DMA_CH1_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000)

#define	DMA_CH1_CTRL_TRIG_WRITE_ERROR_LSB _u(29)

#define	DMA_CH1_CTRL_TRIG_WRITE_ERROR_MSB _u(29)

#define	DMA_CH1_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0)

#define	DMA_CH1_DBG_CTDREQ_ACCESS "WC"

#define	DMA_CH1_DBG_CTDREQ_BITS _u(0x0000003f)

#define	DMA_CH1_DBG_CTDREQ_LSB _u(0)

#define	DMA_CH1_DBG_CTDREQ_MSB _u(5)

#define	DMA_CH1_DBG_CTDREQ_OFFSET _u(0x00000840)

#define	DMA_CH1_DBG_CTDREQ_RESET _u(0x00000000)

#define	DMA_CH1_DBG_TCR_ACCESS "RO"

#define	DMA_CH1_DBG_TCR_BITS _u(0xffffffff)

#define	DMA_CH1_DBG_TCR_LSB _u(0)

#define	DMA_CH1_DBG_TCR_MSB _u(31)

#define	DMA_CH1_DBG_TCR_OFFSET _u(0x00000844)

#define	DMA_CH1_DBG_TCR_RESET _u(0x00000000)

#define	DMA_CH1_READ_ADDR_ACCESS "RW"

#define	DMA_CH1_READ_ADDR_BITS _u(0xffffffff)

#define	DMA_CH1_READ_ADDR_LSB _u(0)

#define	DMA_CH1_READ_ADDR_MSB _u(31)

#define	DMA_CH1_READ_ADDR_OFFSET _u(0x00000040)

#define	DMA_CH1_READ_ADDR_RESET _u(0x00000000)

#define	DMA_CH1_TRANS_COUNT_BITS _u(0xffffffff)

#define	DMA_CH1_TRANS_COUNT_COUNT_ACCESS "RW"

#define	DMA_CH1_TRANS_COUNT_COUNT_BITS _u(0x0fffffff)

#define	DMA_CH1_TRANS_COUNT_COUNT_LSB _u(0)

#define	DMA_CH1_TRANS_COUNT_COUNT_MSB _u(27)

#define	DMA_CH1_TRANS_COUNT_COUNT_RESET _u(0x0000000)

#define	DMA_CH1_TRANS_COUNT_MODE_ACCESS "RW"

#define	DMA_CH1_TRANS_COUNT_MODE_BITS _u(0xf0000000)

#define	DMA_CH1_TRANS_COUNT_MODE_LSB _u(28)

#define	DMA_CH1_TRANS_COUNT_MODE_MSB _u(31)

#define	DMA_CH1_TRANS_COUNT_MODE_RESET _u(0x0)

#define	DMA_CH1_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf)

#define	DMA_CH1_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0)

#define	DMA_CH1_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1)

#define	DMA_CH1_TRANS_COUNT_OFFSET _u(0x00000048)

#define	DMA_CH1_TRANS_COUNT_RESET _u(0x00000000)

#define	DMA_CH1_WRITE_ADDR_ACCESS "RW"

#define	DMA_CH1_WRITE_ADDR_BITS _u(0xffffffff)

#define	DMA_CH1_WRITE_ADDR_LSB _u(0)

#define	DMA_CH1_WRITE_ADDR_MSB _u(31)

#define	DMA_CH1_WRITE_ADDR_OFFSET _u(0x00000044)

#define	DMA_CH1_WRITE_ADDR_RESET _u(0x00000000)

#define	DMA_CH2_AL1_CTRL_ACCESS "RW"

#define	DMA_CH2_AL1_CTRL_BITS _u(0xffffffff)

#define	DMA_CH2_AL1_CTRL_LSB _u(0)

#define	DMA_CH2_AL1_CTRL_MSB _u(31)

#define	DMA_CH2_AL1_CTRL_OFFSET _u(0x00000090)

#define	DMA_CH2_AL1_CTRL_RESET "-"

#define	DMA_CH2_AL1_READ_ADDR_ACCESS "RW"

#define	DMA_CH2_AL1_READ_ADDR_BITS _u(0xffffffff)

#define	DMA_CH2_AL1_READ_ADDR_LSB _u(0)

#define	DMA_CH2_AL1_READ_ADDR_MSB _u(31)

#define	DMA_CH2_AL1_READ_ADDR_OFFSET _u(0x00000094)

#define	DMA_CH2_AL1_READ_ADDR_RESET "-"

#define	DMA_CH2_AL1_TRANS_COUNT_TRIG_ACCESS "RW"

#define	DMA_CH2_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff)

#define	DMA_CH2_AL1_TRANS_COUNT_TRIG_LSB _u(0)

#define	DMA_CH2_AL1_TRANS_COUNT_TRIG_MSB _u(31)

#define	DMA_CH2_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000009c)

#define	DMA_CH2_AL1_TRANS_COUNT_TRIG_RESET "-"

#define	DMA_CH2_AL1_WRITE_ADDR_ACCESS "RW"

#define	DMA_CH2_AL1_WRITE_ADDR_BITS _u(0xffffffff)

#define	DMA_CH2_AL1_WRITE_ADDR_LSB _u(0)

#define	DMA_CH2_AL1_WRITE_ADDR_MSB _u(31)

#define	DMA_CH2_AL1_WRITE_ADDR_OFFSET _u(0x00000098)

#define	DMA_CH2_AL1_WRITE_ADDR_RESET "-"

#define	DMA_CH2_AL2_CTRL_ACCESS "RW"

#define	DMA_CH2_AL2_CTRL_BITS _u(0xffffffff)

#define	DMA_CH2_AL2_CTRL_LSB _u(0)

#define	DMA_CH2_AL2_CTRL_MSB _u(31)

#define	DMA_CH2_AL2_CTRL_OFFSET _u(0x000000a0)

#define	DMA_CH2_AL2_CTRL_RESET "-"

#define	DMA_CH2_AL2_READ_ADDR_ACCESS "RW"

#define	DMA_CH2_AL2_READ_ADDR_BITS _u(0xffffffff)

#define	DMA_CH2_AL2_READ_ADDR_LSB _u(0)

#define	DMA_CH2_AL2_READ_ADDR_MSB _u(31)

#define	DMA_CH2_AL2_READ_ADDR_OFFSET _u(0x000000a8)

#define	DMA_CH2_AL2_READ_ADDR_RESET "-"

#define	DMA_CH2_AL2_TRANS_COUNT_ACCESS "RW"

#define	DMA_CH2_AL2_TRANS_COUNT_BITS _u(0xffffffff)

#define	DMA_CH2_AL2_TRANS_COUNT_LSB _u(0)

#define	DMA_CH2_AL2_TRANS_COUNT_MSB _u(31)

#define	DMA_CH2_AL2_TRANS_COUNT_OFFSET _u(0x000000a4)

#define	DMA_CH2_AL2_TRANS_COUNT_RESET "-"

#define	DMA_CH2_AL2_WRITE_ADDR_TRIG_ACCESS "RW"

#define	DMA_CH2_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff)

#define	DMA_CH2_AL2_WRITE_ADDR_TRIG_LSB _u(0)

#define	DMA_CH2_AL2_WRITE_ADDR_TRIG_MSB _u(31)

#define	DMA_CH2_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x000000ac)

#define	DMA_CH2_AL2_WRITE_ADDR_TRIG_RESET "-"

#define	DMA_CH2_AL3_CTRL_ACCESS "RW"

#define	DMA_CH2_AL3_CTRL_BITS _u(0xffffffff)

#define	DMA_CH2_AL3_CTRL_LSB _u(0)

#define	DMA_CH2_AL3_CTRL_MSB _u(31)

#define	DMA_CH2_AL3_CTRL_OFFSET _u(0x000000b0)

#define	DMA_CH2_AL3_CTRL_RESET "-"

#define	DMA_CH2_AL3_READ_ADDR_TRIG_ACCESS "RW"

#define	DMA_CH2_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff)

#define	DMA_CH2_AL3_READ_ADDR_TRIG_LSB _u(0)

#define	DMA_CH2_AL3_READ_ADDR_TRIG_MSB _u(31)

#define	DMA_CH2_AL3_READ_ADDR_TRIG_OFFSET _u(0x000000bc)

#define	DMA_CH2_AL3_READ_ADDR_TRIG_RESET "-"

#define	DMA_CH2_AL3_TRANS_COUNT_ACCESS "RW"

#define	DMA_CH2_AL3_TRANS_COUNT_BITS _u(0xffffffff)

#define	DMA_CH2_AL3_TRANS_COUNT_LSB _u(0)

#define	DMA_CH2_AL3_TRANS_COUNT_MSB _u(31)

#define	DMA_CH2_AL3_TRANS_COUNT_OFFSET _u(0x000000b8)

#define	DMA_CH2_AL3_TRANS_COUNT_RESET "-"

#define	DMA_CH2_AL3_WRITE_ADDR_ACCESS "RW"

#define	DMA_CH2_AL3_WRITE_ADDR_BITS _u(0xffffffff)

#define	DMA_CH2_AL3_WRITE_ADDR_LSB _u(0)

#define	DMA_CH2_AL3_WRITE_ADDR_MSB _u(31)

#define	DMA_CH2_AL3_WRITE_ADDR_OFFSET _u(0x000000b4)

#define	DMA_CH2_AL3_WRITE_ADDR_RESET "-"

#define	DMA_CH2_CTRL_TRIG_AHB_ERROR_ACCESS "RO"

#define	DMA_CH2_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000)

#define	DMA_CH2_CTRL_TRIG_AHB_ERROR_LSB _u(31)

#define	DMA_CH2_CTRL_TRIG_AHB_ERROR_MSB _u(31)

#define	DMA_CH2_CTRL_TRIG_AHB_ERROR_RESET _u(0x0)

#define	DMA_CH2_CTRL_TRIG_BITS _u(0xe7ffffff)

#define	DMA_CH2_CTRL_TRIG_BSWAP_ACCESS "RW"

#define	DMA_CH2_CTRL_TRIG_BSWAP_BITS _u(0x01000000)

#define	DMA_CH2_CTRL_TRIG_BSWAP_LSB _u(24)

#define	DMA_CH2_CTRL_TRIG_BSWAP_MSB _u(24)

#define	DMA_CH2_CTRL_TRIG_BSWAP_RESET _u(0x0)

#define	DMA_CH2_CTRL_TRIG_BUSY_ACCESS "RO"

#define	DMA_CH2_CTRL_TRIG_BUSY_BITS _u(0x04000000)

#define	DMA_CH2_CTRL_TRIG_BUSY_LSB _u(26)

#define	DMA_CH2_CTRL_TRIG_BUSY_MSB _u(26)

#define	DMA_CH2_CTRL_TRIG_BUSY_RESET _u(0x0)

#define	DMA_CH2_CTRL_TRIG_CHAIN_TO_ACCESS "RW"

#define	DMA_CH2_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000)

#define	DMA_CH2_CTRL_TRIG_CHAIN_TO_LSB _u(13)

#define	DMA_CH2_CTRL_TRIG_CHAIN_TO_MSB _u(16)

#define	DMA_CH2_CTRL_TRIG_CHAIN_TO_RESET _u(0x0)

#define	DMA_CH2_CTRL_TRIG_DATA_SIZE_ACCESS "RW"

#define	DMA_CH2_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c)

#define	DMA_CH2_CTRL_TRIG_DATA_SIZE_LSB _u(2)

#define	DMA_CH2_CTRL_TRIG_DATA_SIZE_MSB _u(3)

#define	DMA_CH2_CTRL_TRIG_DATA_SIZE_RESET _u(0x0)

#define	DMA_CH2_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0)

#define	DMA_CH2_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1)

#define	DMA_CH2_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2)

#define	DMA_CH2_CTRL_TRIG_EN_ACCESS "RW"

#define	DMA_CH2_CTRL_TRIG_EN_BITS _u(0x00000001)

#define	DMA_CH2_CTRL_TRIG_EN_LSB _u(0)

#define	DMA_CH2_CTRL_TRIG_EN_MSB _u(0)

#define	DMA_CH2_CTRL_TRIG_EN_RESET _u(0x0)

#define	DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW"

#define	DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002)

#define	DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1)

#define	DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1)

#define	DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0)

#define	DMA_CH2_CTRL_TRIG_INCR_READ_ACCESS "RW"

#define	DMA_CH2_CTRL_TRIG_INCR_READ_BITS _u(0x00000010)

#define	DMA_CH2_CTRL_TRIG_INCR_READ_LSB _u(4)

#define	DMA_CH2_CTRL_TRIG_INCR_READ_MSB _u(4)

#define	DMA_CH2_CTRL_TRIG_INCR_READ_RESET _u(0x0)

#define	DMA_CH2_CTRL_TRIG_INCR_READ_REV_ACCESS "RW"

#define	DMA_CH2_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020)

#define	DMA_CH2_CTRL_TRIG_INCR_READ_REV_LSB _u(5)

#define	DMA_CH2_CTRL_TRIG_INCR_READ_REV_MSB _u(5)

#define	DMA_CH2_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0)

#define	DMA_CH2_CTRL_TRIG_INCR_WRITE_ACCESS "RW"

#define	DMA_CH2_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040)

#define	DMA_CH2_CTRL_TRIG_INCR_WRITE_LSB _u(6)

#define	DMA_CH2_CTRL_TRIG_INCR_WRITE_MSB _u(6)

#define	DMA_CH2_CTRL_TRIG_INCR_WRITE_RESET _u(0x0)

#define	DMA_CH2_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW"

#define	DMA_CH2_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080)

#define	DMA_CH2_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7)

#define	DMA_CH2_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7)

#define	DMA_CH2_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0)

#define	DMA_CH2_CTRL_TRIG_IRQ_QUIET_ACCESS "RW"

#define	DMA_CH2_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000)

#define	DMA_CH2_CTRL_TRIG_IRQ_QUIET_LSB _u(23)

#define	DMA_CH2_CTRL_TRIG_IRQ_QUIET_MSB _u(23)

#define	DMA_CH2_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0)

#define	DMA_CH2_CTRL_TRIG_OFFSET _u(0x0000008c)

#define	DMA_CH2_CTRL_TRIG_READ_ERROR_ACCESS "WC"

#define	DMA_CH2_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000)

#define	DMA_CH2_CTRL_TRIG_READ_ERROR_LSB _u(30)

#define	DMA_CH2_CTRL_TRIG_READ_ERROR_MSB _u(30)

#define	DMA_CH2_CTRL_TRIG_READ_ERROR_RESET _u(0x0)

#define	DMA_CH2_CTRL_TRIG_RESET _u(0x00000000)

#define	DMA_CH2_CTRL_TRIG_RING_SEL_ACCESS "RW"

#define	DMA_CH2_CTRL_TRIG_RING_SEL_BITS _u(0x00001000)

#define	DMA_CH2_CTRL_TRIG_RING_SEL_LSB _u(12)

#define	DMA_CH2_CTRL_TRIG_RING_SEL_MSB _u(12)

#define	DMA_CH2_CTRL_TRIG_RING_SEL_RESET _u(0x0)

#define	DMA_CH2_CTRL_TRIG_RING_SIZE_ACCESS "RW"

#define	DMA_CH2_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00)

#define	DMA_CH2_CTRL_TRIG_RING_SIZE_LSB _u(8)

#define	DMA_CH2_CTRL_TRIG_RING_SIZE_MSB _u(11)

#define	DMA_CH2_CTRL_TRIG_RING_SIZE_RESET _u(0x0)

#define	DMA_CH2_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0)

#define	DMA_CH2_CTRL_TRIG_SNIFF_EN_ACCESS "RW"

#define	DMA_CH2_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000)

#define	DMA_CH2_CTRL_TRIG_SNIFF_EN_LSB _u(25)

#define	DMA_CH2_CTRL_TRIG_SNIFF_EN_MSB _u(25)

#define	DMA_CH2_CTRL_TRIG_SNIFF_EN_RESET _u(0x0)

#define	DMA_CH2_CTRL_TRIG_TREQ_SEL_ACCESS "RW"

#define	DMA_CH2_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000)

#define	DMA_CH2_CTRL_TRIG_TREQ_SEL_LSB _u(17)

#define	DMA_CH2_CTRL_TRIG_TREQ_SEL_MSB _u(22)

#define	DMA_CH2_CTRL_TRIG_TREQ_SEL_RESET _u(0x00)

#define	DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f)

#define	DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b)

#define	DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c)

#define	DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d)

#define	DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e)

#define	DMA_CH2_CTRL_TRIG_WRITE_ERROR_ACCESS "WC"

#define	DMA_CH2_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000)

#define	DMA_CH2_CTRL_TRIG_WRITE_ERROR_LSB _u(29)

#define	DMA_CH2_CTRL_TRIG_WRITE_ERROR_MSB _u(29)

#define	DMA_CH2_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0)

#define	DMA_CH2_DBG_CTDREQ_ACCESS "WC"

#define	DMA_CH2_DBG_CTDREQ_BITS _u(0x0000003f)

#define	DMA_CH2_DBG_CTDREQ_LSB _u(0)

#define	DMA_CH2_DBG_CTDREQ_MSB _u(5)

#define	DMA_CH2_DBG_CTDREQ_OFFSET _u(0x00000880)

#define	DMA_CH2_DBG_CTDREQ_RESET _u(0x00000000)

#define	DMA_CH2_DBG_TCR_ACCESS "RO"

#define	DMA_CH2_DBG_TCR_BITS _u(0xffffffff)

#define	DMA_CH2_DBG_TCR_LSB _u(0)

#define	DMA_CH2_DBG_TCR_MSB _u(31)

#define	DMA_CH2_DBG_TCR_OFFSET _u(0x00000884)

#define	DMA_CH2_DBG_TCR_RESET _u(0x00000000)

#define	DMA_CH2_READ_ADDR_ACCESS "RW"

#define	DMA_CH2_READ_ADDR_BITS _u(0xffffffff)

#define	DMA_CH2_READ_ADDR_LSB _u(0)

#define	DMA_CH2_READ_ADDR_MSB _u(31)

#define	DMA_CH2_READ_ADDR_OFFSET _u(0x00000080)

#define	DMA_CH2_READ_ADDR_RESET _u(0x00000000)

#define	DMA_CH2_TRANS_COUNT_BITS _u(0xffffffff)

#define	DMA_CH2_TRANS_COUNT_COUNT_ACCESS "RW"

#define	DMA_CH2_TRANS_COUNT_COUNT_BITS _u(0x0fffffff)

#define	DMA_CH2_TRANS_COUNT_COUNT_LSB _u(0)

#define	DMA_CH2_TRANS_COUNT_COUNT_MSB _u(27)

#define	DMA_CH2_TRANS_COUNT_COUNT_RESET _u(0x0000000)

#define	DMA_CH2_TRANS_COUNT_MODE_ACCESS "RW"

#define	DMA_CH2_TRANS_COUNT_MODE_BITS _u(0xf0000000)

#define	DMA_CH2_TRANS_COUNT_MODE_LSB _u(28)

#define	DMA_CH2_TRANS_COUNT_MODE_MSB _u(31)

#define	DMA_CH2_TRANS_COUNT_MODE_RESET _u(0x0)

#define	DMA_CH2_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf)

#define	DMA_CH2_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0)

#define	DMA_CH2_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1)

#define	DMA_CH2_TRANS_COUNT_OFFSET _u(0x00000088)

#define	DMA_CH2_TRANS_COUNT_RESET _u(0x00000000)

#define	DMA_CH2_WRITE_ADDR_ACCESS "RW"

#define	DMA_CH2_WRITE_ADDR_BITS _u(0xffffffff)

#define	DMA_CH2_WRITE_ADDR_LSB _u(0)

#define	DMA_CH2_WRITE_ADDR_MSB _u(31)

#define	DMA_CH2_WRITE_ADDR_OFFSET _u(0x00000084)

#define	DMA_CH2_WRITE_ADDR_RESET _u(0x00000000)

#define	DMA_CH3_AL1_CTRL_ACCESS "RW"

#define	DMA_CH3_AL1_CTRL_BITS _u(0xffffffff)

#define	DMA_CH3_AL1_CTRL_LSB _u(0)

#define	DMA_CH3_AL1_CTRL_MSB _u(31)

#define	DMA_CH3_AL1_CTRL_OFFSET _u(0x000000d0)

#define	DMA_CH3_AL1_CTRL_RESET "-"

#define	DMA_CH3_AL1_READ_ADDR_ACCESS "RW"

#define	DMA_CH3_AL1_READ_ADDR_BITS _u(0xffffffff)

#define	DMA_CH3_AL1_READ_ADDR_LSB _u(0)

#define	DMA_CH3_AL1_READ_ADDR_MSB _u(31)

#define	DMA_CH3_AL1_READ_ADDR_OFFSET _u(0x000000d4)

#define	DMA_CH3_AL1_READ_ADDR_RESET "-"

#define	DMA_CH3_AL1_TRANS_COUNT_TRIG_ACCESS "RW"

#define	DMA_CH3_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff)

#define	DMA_CH3_AL1_TRANS_COUNT_TRIG_LSB _u(0)

#define	DMA_CH3_AL1_TRANS_COUNT_TRIG_MSB _u(31)

#define	DMA_CH3_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x000000dc)

#define	DMA_CH3_AL1_TRANS_COUNT_TRIG_RESET "-"

#define	DMA_CH3_AL1_WRITE_ADDR_ACCESS "RW"

#define	DMA_CH3_AL1_WRITE_ADDR_BITS _u(0xffffffff)

#define	DMA_CH3_AL1_WRITE_ADDR_LSB _u(0)

#define	DMA_CH3_AL1_WRITE_ADDR_MSB _u(31)

#define	DMA_CH3_AL1_WRITE_ADDR_OFFSET _u(0x000000d8)

#define	DMA_CH3_AL1_WRITE_ADDR_RESET "-"

#define	DMA_CH3_AL2_CTRL_ACCESS "RW"

#define	DMA_CH3_AL2_CTRL_BITS _u(0xffffffff)

#define	DMA_CH3_AL2_CTRL_LSB _u(0)

#define	DMA_CH3_AL2_CTRL_MSB _u(31)

#define	DMA_CH3_AL2_CTRL_OFFSET _u(0x000000e0)

#define	DMA_CH3_AL2_CTRL_RESET "-"

#define	DMA_CH3_AL2_READ_ADDR_ACCESS "RW"

#define	DMA_CH3_AL2_READ_ADDR_BITS _u(0xffffffff)

#define	DMA_CH3_AL2_READ_ADDR_LSB _u(0)

#define	DMA_CH3_AL2_READ_ADDR_MSB _u(31)

#define	DMA_CH3_AL2_READ_ADDR_OFFSET _u(0x000000e8)

#define	DMA_CH3_AL2_READ_ADDR_RESET "-"

#define	DMA_CH3_AL2_TRANS_COUNT_ACCESS "RW"

#define	DMA_CH3_AL2_TRANS_COUNT_BITS _u(0xffffffff)

#define	DMA_CH3_AL2_TRANS_COUNT_LSB _u(0)

#define	DMA_CH3_AL2_TRANS_COUNT_MSB _u(31)

#define	DMA_CH3_AL2_TRANS_COUNT_OFFSET _u(0x000000e4)

#define	DMA_CH3_AL2_TRANS_COUNT_RESET "-"

#define	DMA_CH3_AL2_WRITE_ADDR_TRIG_ACCESS "RW"

#define	DMA_CH3_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff)

#define	DMA_CH3_AL2_WRITE_ADDR_TRIG_LSB _u(0)

#define	DMA_CH3_AL2_WRITE_ADDR_TRIG_MSB _u(31)

#define	DMA_CH3_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x000000ec)

#define	DMA_CH3_AL2_WRITE_ADDR_TRIG_RESET "-"

#define	DMA_CH3_AL3_CTRL_ACCESS "RW"

#define	DMA_CH3_AL3_CTRL_BITS _u(0xffffffff)

#define	DMA_CH3_AL3_CTRL_LSB _u(0)

#define	DMA_CH3_AL3_CTRL_MSB _u(31)

#define	DMA_CH3_AL3_CTRL_OFFSET _u(0x000000f0)

#define	DMA_CH3_AL3_CTRL_RESET "-"

#define	DMA_CH3_AL3_READ_ADDR_TRIG_ACCESS "RW"

#define	DMA_CH3_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff)

#define	DMA_CH3_AL3_READ_ADDR_TRIG_LSB _u(0)

#define	DMA_CH3_AL3_READ_ADDR_TRIG_MSB _u(31)

#define	DMA_CH3_AL3_READ_ADDR_TRIG_OFFSET _u(0x000000fc)

#define	DMA_CH3_AL3_READ_ADDR_TRIG_RESET "-"

#define	DMA_CH3_AL3_TRANS_COUNT_ACCESS "RW"

#define	DMA_CH3_AL3_TRANS_COUNT_BITS _u(0xffffffff)

#define	DMA_CH3_AL3_TRANS_COUNT_LSB _u(0)

#define	DMA_CH3_AL3_TRANS_COUNT_MSB _u(31)

#define	DMA_CH3_AL3_TRANS_COUNT_OFFSET _u(0x000000f8)

#define	DMA_CH3_AL3_TRANS_COUNT_RESET "-"

#define	DMA_CH3_AL3_WRITE_ADDR_ACCESS "RW"

#define	DMA_CH3_AL3_WRITE_ADDR_BITS _u(0xffffffff)

#define	DMA_CH3_AL3_WRITE_ADDR_LSB _u(0)

#define	DMA_CH3_AL3_WRITE_ADDR_MSB _u(31)

#define	DMA_CH3_AL3_WRITE_ADDR_OFFSET _u(0x000000f4)

#define	DMA_CH3_AL3_WRITE_ADDR_RESET "-"

#define	DMA_CH3_CTRL_TRIG_AHB_ERROR_ACCESS "RO"

#define	DMA_CH3_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000)

#define	DMA_CH3_CTRL_TRIG_AHB_ERROR_LSB _u(31)

#define	DMA_CH3_CTRL_TRIG_AHB_ERROR_MSB _u(31)

#define	DMA_CH3_CTRL_TRIG_AHB_ERROR_RESET _u(0x0)

#define	DMA_CH3_CTRL_TRIG_BITS _u(0xe7ffffff)

#define	DMA_CH3_CTRL_TRIG_BSWAP_ACCESS "RW"

#define	DMA_CH3_CTRL_TRIG_BSWAP_BITS _u(0x01000000)

#define	DMA_CH3_CTRL_TRIG_BSWAP_LSB _u(24)

#define	DMA_CH3_CTRL_TRIG_BSWAP_MSB _u(24)

#define	DMA_CH3_CTRL_TRIG_BSWAP_RESET _u(0x0)

#define	DMA_CH3_CTRL_TRIG_BUSY_ACCESS "RO"

#define	DMA_CH3_CTRL_TRIG_BUSY_BITS _u(0x04000000)

#define	DMA_CH3_CTRL_TRIG_BUSY_LSB _u(26)

#define	DMA_CH3_CTRL_TRIG_BUSY_MSB _u(26)

#define	DMA_CH3_CTRL_TRIG_BUSY_RESET _u(0x0)

#define	DMA_CH3_CTRL_TRIG_CHAIN_TO_ACCESS "RW"

#define	DMA_CH3_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000)

#define	DMA_CH3_CTRL_TRIG_CHAIN_TO_LSB _u(13)

#define	DMA_CH3_CTRL_TRIG_CHAIN_TO_MSB _u(16)

#define	DMA_CH3_CTRL_TRIG_CHAIN_TO_RESET _u(0x0)

#define	DMA_CH3_CTRL_TRIG_DATA_SIZE_ACCESS "RW"

#define	DMA_CH3_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c)

#define	DMA_CH3_CTRL_TRIG_DATA_SIZE_LSB _u(2)

#define	DMA_CH3_CTRL_TRIG_DATA_SIZE_MSB _u(3)

#define	DMA_CH3_CTRL_TRIG_DATA_SIZE_RESET _u(0x0)

#define	DMA_CH3_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0)

#define	DMA_CH3_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1)

#define	DMA_CH3_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2)

#define	DMA_CH3_CTRL_TRIG_EN_ACCESS "RW"

#define	DMA_CH3_CTRL_TRIG_EN_BITS _u(0x00000001)

#define	DMA_CH3_CTRL_TRIG_EN_LSB _u(0)

#define	DMA_CH3_CTRL_TRIG_EN_MSB _u(0)

#define	DMA_CH3_CTRL_TRIG_EN_RESET _u(0x0)

#define	DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW"

#define	DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002)

#define	DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1)

#define	DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1)

#define	DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0)

#define	DMA_CH3_CTRL_TRIG_INCR_READ_ACCESS "RW"

#define	DMA_CH3_CTRL_TRIG_INCR_READ_BITS _u(0x00000010)

#define	DMA_CH3_CTRL_TRIG_INCR_READ_LSB _u(4)

#define	DMA_CH3_CTRL_TRIG_INCR_READ_MSB _u(4)

#define	DMA_CH3_CTRL_TRIG_INCR_READ_RESET _u(0x0)

#define	DMA_CH3_CTRL_TRIG_INCR_READ_REV_ACCESS "RW"

#define	DMA_CH3_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020)

#define	DMA_CH3_CTRL_TRIG_INCR_READ_REV_LSB _u(5)

#define	DMA_CH3_CTRL_TRIG_INCR_READ_REV_MSB _u(5)

#define	DMA_CH3_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0)

#define	DMA_CH3_CTRL_TRIG_INCR_WRITE_ACCESS "RW"

#define	DMA_CH3_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040)

#define	DMA_CH3_CTRL_TRIG_INCR_WRITE_LSB _u(6)

#define	DMA_CH3_CTRL_TRIG_INCR_WRITE_MSB _u(6)

#define	DMA_CH3_CTRL_TRIG_INCR_WRITE_RESET _u(0x0)

#define	DMA_CH3_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW"

#define	DMA_CH3_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080)

#define	DMA_CH3_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7)

#define	DMA_CH3_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7)

#define	DMA_CH3_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0)

#define	DMA_CH3_CTRL_TRIG_IRQ_QUIET_ACCESS "RW"

#define	DMA_CH3_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000)

#define	DMA_CH3_CTRL_TRIG_IRQ_QUIET_LSB _u(23)

#define	DMA_CH3_CTRL_TRIG_IRQ_QUIET_MSB _u(23)

#define	DMA_CH3_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0)

#define	DMA_CH3_CTRL_TRIG_OFFSET _u(0x000000cc)

#define	DMA_CH3_CTRL_TRIG_READ_ERROR_ACCESS "WC"

#define	DMA_CH3_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000)

#define	DMA_CH3_CTRL_TRIG_READ_ERROR_LSB _u(30)

#define	DMA_CH3_CTRL_TRIG_READ_ERROR_MSB _u(30)

#define	DMA_CH3_CTRL_TRIG_READ_ERROR_RESET _u(0x0)

#define	DMA_CH3_CTRL_TRIG_RESET _u(0x00000000)

#define	DMA_CH3_CTRL_TRIG_RING_SEL_ACCESS "RW"

#define	DMA_CH3_CTRL_TRIG_RING_SEL_BITS _u(0x00001000)

#define	DMA_CH3_CTRL_TRIG_RING_SEL_LSB _u(12)

#define	DMA_CH3_CTRL_TRIG_RING_SEL_MSB _u(12)

#define	DMA_CH3_CTRL_TRIG_RING_SEL_RESET _u(0x0)

#define	DMA_CH3_CTRL_TRIG_RING_SIZE_ACCESS "RW"

#define	DMA_CH3_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00)

#define	DMA_CH3_CTRL_TRIG_RING_SIZE_LSB _u(8)

#define	DMA_CH3_CTRL_TRIG_RING_SIZE_MSB _u(11)

#define	DMA_CH3_CTRL_TRIG_RING_SIZE_RESET _u(0x0)

#define	DMA_CH3_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0)

#define	DMA_CH3_CTRL_TRIG_SNIFF_EN_ACCESS "RW"

#define	DMA_CH3_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000)

#define	DMA_CH3_CTRL_TRIG_SNIFF_EN_LSB _u(25)

#define	DMA_CH3_CTRL_TRIG_SNIFF_EN_MSB _u(25)

#define	DMA_CH3_CTRL_TRIG_SNIFF_EN_RESET _u(0x0)

#define	DMA_CH3_CTRL_TRIG_TREQ_SEL_ACCESS "RW"

#define	DMA_CH3_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000)

#define	DMA_CH3_CTRL_TRIG_TREQ_SEL_LSB _u(17)

#define	DMA_CH3_CTRL_TRIG_TREQ_SEL_MSB _u(22)

#define	DMA_CH3_CTRL_TRIG_TREQ_SEL_RESET _u(0x00)

#define	DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f)

#define	DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b)

#define	DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c)

#define	DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d)

#define	DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e)

#define	DMA_CH3_CTRL_TRIG_WRITE_ERROR_ACCESS "WC"

#define	DMA_CH3_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000)

#define	DMA_CH3_CTRL_TRIG_WRITE_ERROR_LSB _u(29)

#define	DMA_CH3_CTRL_TRIG_WRITE_ERROR_MSB _u(29)

#define	DMA_CH3_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0)

#define	DMA_CH3_DBG_CTDREQ_ACCESS "WC"

#define	DMA_CH3_DBG_CTDREQ_BITS _u(0x0000003f)

#define	DMA_CH3_DBG_CTDREQ_LSB _u(0)

#define	DMA_CH3_DBG_CTDREQ_MSB _u(5)

#define	DMA_CH3_DBG_CTDREQ_OFFSET _u(0x000008c0)

#define	DMA_CH3_DBG_CTDREQ_RESET _u(0x00000000)

#define	DMA_CH3_DBG_TCR_ACCESS "RO"

#define	DMA_CH3_DBG_TCR_BITS _u(0xffffffff)

#define	DMA_CH3_DBG_TCR_LSB _u(0)

#define	DMA_CH3_DBG_TCR_MSB _u(31)

#define	DMA_CH3_DBG_TCR_OFFSET _u(0x000008c4)

#define	DMA_CH3_DBG_TCR_RESET _u(0x00000000)

#define	DMA_CH3_READ_ADDR_ACCESS "RW"

#define	DMA_CH3_READ_ADDR_BITS _u(0xffffffff)

#define	DMA_CH3_READ_ADDR_LSB _u(0)

#define	DMA_CH3_READ_ADDR_MSB _u(31)

#define	DMA_CH3_READ_ADDR_OFFSET _u(0x000000c0)

#define	DMA_CH3_READ_ADDR_RESET _u(0x00000000)

#define	DMA_CH3_TRANS_COUNT_BITS _u(0xffffffff)

#define	DMA_CH3_TRANS_COUNT_COUNT_ACCESS "RW"

#define	DMA_CH3_TRANS_COUNT_COUNT_BITS _u(0x0fffffff)

#define	DMA_CH3_TRANS_COUNT_COUNT_LSB _u(0)

#define	DMA_CH3_TRANS_COUNT_COUNT_MSB _u(27)

#define	DMA_CH3_TRANS_COUNT_COUNT_RESET _u(0x0000000)

#define	DMA_CH3_TRANS_COUNT_MODE_ACCESS "RW"

#define	DMA_CH3_TRANS_COUNT_MODE_BITS _u(0xf0000000)

#define	DMA_CH3_TRANS_COUNT_MODE_LSB _u(28)

#define	DMA_CH3_TRANS_COUNT_MODE_MSB _u(31)

#define	DMA_CH3_TRANS_COUNT_MODE_RESET _u(0x0)

#define	DMA_CH3_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf)

#define	DMA_CH3_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0)

#define	DMA_CH3_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1)

#define	DMA_CH3_TRANS_COUNT_OFFSET _u(0x000000c8)

#define	DMA_CH3_TRANS_COUNT_RESET _u(0x00000000)

#define	DMA_CH3_WRITE_ADDR_ACCESS "RW"

#define	DMA_CH3_WRITE_ADDR_BITS _u(0xffffffff)

#define	DMA_CH3_WRITE_ADDR_LSB _u(0)

#define	DMA_CH3_WRITE_ADDR_MSB _u(31)

#define	DMA_CH3_WRITE_ADDR_OFFSET _u(0x000000c4)

#define	DMA_CH3_WRITE_ADDR_RESET _u(0x00000000)

#define	DMA_CH4_AL1_CTRL_ACCESS "RW"

#define	DMA_CH4_AL1_CTRL_BITS _u(0xffffffff)

#define	DMA_CH4_AL1_CTRL_LSB _u(0)

#define	DMA_CH4_AL1_CTRL_MSB _u(31)

#define	DMA_CH4_AL1_CTRL_OFFSET _u(0x00000110)

#define	DMA_CH4_AL1_CTRL_RESET "-"

#define	DMA_CH4_AL1_READ_ADDR_ACCESS "RW"

#define	DMA_CH4_AL1_READ_ADDR_BITS _u(0xffffffff)

#define	DMA_CH4_AL1_READ_ADDR_LSB _u(0)

#define	DMA_CH4_AL1_READ_ADDR_MSB _u(31)

#define	DMA_CH4_AL1_READ_ADDR_OFFSET _u(0x00000114)

#define	DMA_CH4_AL1_READ_ADDR_RESET "-"

#define	DMA_CH4_AL1_TRANS_COUNT_TRIG_ACCESS "RW"

#define	DMA_CH4_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff)

#define	DMA_CH4_AL1_TRANS_COUNT_TRIG_LSB _u(0)

#define	DMA_CH4_AL1_TRANS_COUNT_TRIG_MSB _u(31)

#define	DMA_CH4_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000011c)

#define	DMA_CH4_AL1_TRANS_COUNT_TRIG_RESET "-"

#define	DMA_CH4_AL1_WRITE_ADDR_ACCESS "RW"

#define	DMA_CH4_AL1_WRITE_ADDR_BITS _u(0xffffffff)

#define	DMA_CH4_AL1_WRITE_ADDR_LSB _u(0)

#define	DMA_CH4_AL1_WRITE_ADDR_MSB _u(31)

#define	DMA_CH4_AL1_WRITE_ADDR_OFFSET _u(0x00000118)

#define	DMA_CH4_AL1_WRITE_ADDR_RESET "-"

#define	DMA_CH4_AL2_CTRL_ACCESS "RW"

#define	DMA_CH4_AL2_CTRL_BITS _u(0xffffffff)

#define	DMA_CH4_AL2_CTRL_LSB _u(0)

#define	DMA_CH4_AL2_CTRL_MSB _u(31)

#define	DMA_CH4_AL2_CTRL_OFFSET _u(0x00000120)

#define	DMA_CH4_AL2_CTRL_RESET "-"

#define	DMA_CH4_AL2_READ_ADDR_ACCESS "RW"

#define	DMA_CH4_AL2_READ_ADDR_BITS _u(0xffffffff)

#define	DMA_CH4_AL2_READ_ADDR_LSB _u(0)

#define	DMA_CH4_AL2_READ_ADDR_MSB _u(31)

#define	DMA_CH4_AL2_READ_ADDR_OFFSET _u(0x00000128)

#define	DMA_CH4_AL2_READ_ADDR_RESET "-"

#define	DMA_CH4_AL2_TRANS_COUNT_ACCESS "RW"

#define	DMA_CH4_AL2_TRANS_COUNT_BITS _u(0xffffffff)

#define	DMA_CH4_AL2_TRANS_COUNT_LSB _u(0)

#define	DMA_CH4_AL2_TRANS_COUNT_MSB _u(31)

#define	DMA_CH4_AL2_TRANS_COUNT_OFFSET _u(0x00000124)

#define	DMA_CH4_AL2_TRANS_COUNT_RESET "-"

#define	DMA_CH4_AL2_WRITE_ADDR_TRIG_ACCESS "RW"

#define	DMA_CH4_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff)

#define	DMA_CH4_AL2_WRITE_ADDR_TRIG_LSB _u(0)

#define	DMA_CH4_AL2_WRITE_ADDR_TRIG_MSB _u(31)

#define	DMA_CH4_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x0000012c)

#define	DMA_CH4_AL2_WRITE_ADDR_TRIG_RESET "-"

#define	DMA_CH4_AL3_CTRL_ACCESS "RW"

#define	DMA_CH4_AL3_CTRL_BITS _u(0xffffffff)

#define	DMA_CH4_AL3_CTRL_LSB _u(0)

#define	DMA_CH4_AL3_CTRL_MSB _u(31)

#define	DMA_CH4_AL3_CTRL_OFFSET _u(0x00000130)

#define	DMA_CH4_AL3_CTRL_RESET "-"

#define	DMA_CH4_AL3_READ_ADDR_TRIG_ACCESS "RW"

#define	DMA_CH4_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff)

#define	DMA_CH4_AL3_READ_ADDR_TRIG_LSB _u(0)

#define	DMA_CH4_AL3_READ_ADDR_TRIG_MSB _u(31)

#define	DMA_CH4_AL3_READ_ADDR_TRIG_OFFSET _u(0x0000013c)

#define	DMA_CH4_AL3_READ_ADDR_TRIG_RESET "-"

#define	DMA_CH4_AL3_TRANS_COUNT_ACCESS "RW"

#define	DMA_CH4_AL3_TRANS_COUNT_BITS _u(0xffffffff)

#define	DMA_CH4_AL3_TRANS_COUNT_LSB _u(0)

#define	DMA_CH4_AL3_TRANS_COUNT_MSB _u(31)

#define	DMA_CH4_AL3_TRANS_COUNT_OFFSET _u(0x00000138)

#define	DMA_CH4_AL3_TRANS_COUNT_RESET "-"

#define	DMA_CH4_AL3_WRITE_ADDR_ACCESS "RW"

#define	DMA_CH4_AL3_WRITE_ADDR_BITS _u(0xffffffff)

#define	DMA_CH4_AL3_WRITE_ADDR_LSB _u(0)

#define	DMA_CH4_AL3_WRITE_ADDR_MSB _u(31)

#define	DMA_CH4_AL3_WRITE_ADDR_OFFSET _u(0x00000134)

#define	DMA_CH4_AL3_WRITE_ADDR_RESET "-"

#define	DMA_CH4_CTRL_TRIG_AHB_ERROR_ACCESS "RO"

#define	DMA_CH4_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000)

#define	DMA_CH4_CTRL_TRIG_AHB_ERROR_LSB _u(31)

#define	DMA_CH4_CTRL_TRIG_AHB_ERROR_MSB _u(31)

#define	DMA_CH4_CTRL_TRIG_AHB_ERROR_RESET _u(0x0)

#define	DMA_CH4_CTRL_TRIG_BITS _u(0xe7ffffff)

#define	DMA_CH4_CTRL_TRIG_BSWAP_ACCESS "RW"

#define	DMA_CH4_CTRL_TRIG_BSWAP_BITS _u(0x01000000)

#define	DMA_CH4_CTRL_TRIG_BSWAP_LSB _u(24)

#define	DMA_CH4_CTRL_TRIG_BSWAP_MSB _u(24)

#define	DMA_CH4_CTRL_TRIG_BSWAP_RESET _u(0x0)

#define	DMA_CH4_CTRL_TRIG_BUSY_ACCESS "RO"

#define	DMA_CH4_CTRL_TRIG_BUSY_BITS _u(0x04000000)

#define	DMA_CH4_CTRL_TRIG_BUSY_LSB _u(26)

#define	DMA_CH4_CTRL_TRIG_BUSY_MSB _u(26)

#define	DMA_CH4_CTRL_TRIG_BUSY_RESET _u(0x0)

#define	DMA_CH4_CTRL_TRIG_CHAIN_TO_ACCESS "RW"

#define	DMA_CH4_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000)

#define	DMA_CH4_CTRL_TRIG_CHAIN_TO_LSB _u(13)

#define	DMA_CH4_CTRL_TRIG_CHAIN_TO_MSB _u(16)

#define	DMA_CH4_CTRL_TRIG_CHAIN_TO_RESET _u(0x0)

#define	DMA_CH4_CTRL_TRIG_DATA_SIZE_ACCESS "RW"

#define	DMA_CH4_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c)

#define	DMA_CH4_CTRL_TRIG_DATA_SIZE_LSB _u(2)

#define	DMA_CH4_CTRL_TRIG_DATA_SIZE_MSB _u(3)

#define	DMA_CH4_CTRL_TRIG_DATA_SIZE_RESET _u(0x0)

#define	DMA_CH4_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0)

#define	DMA_CH4_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1)

#define	DMA_CH4_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2)

#define	DMA_CH4_CTRL_TRIG_EN_ACCESS "RW"

#define	DMA_CH4_CTRL_TRIG_EN_BITS _u(0x00000001)

#define	DMA_CH4_CTRL_TRIG_EN_LSB _u(0)

#define	DMA_CH4_CTRL_TRIG_EN_MSB _u(0)

#define	DMA_CH4_CTRL_TRIG_EN_RESET _u(0x0)

#define	DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW"

#define	DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002)

#define	DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1)

#define	DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1)

#define	DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0)

#define	DMA_CH4_CTRL_TRIG_INCR_READ_ACCESS "RW"

#define	DMA_CH4_CTRL_TRIG_INCR_READ_BITS _u(0x00000010)

#define	DMA_CH4_CTRL_TRIG_INCR_READ_LSB _u(4)

#define	DMA_CH4_CTRL_TRIG_INCR_READ_MSB _u(4)

#define	DMA_CH4_CTRL_TRIG_INCR_READ_RESET _u(0x0)

#define	DMA_CH4_CTRL_TRIG_INCR_READ_REV_ACCESS "RW"

#define	DMA_CH4_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020)

#define	DMA_CH4_CTRL_TRIG_INCR_READ_REV_LSB _u(5)

#define	DMA_CH4_CTRL_TRIG_INCR_READ_REV_MSB _u(5)

#define	DMA_CH4_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0)

#define	DMA_CH4_CTRL_TRIG_INCR_WRITE_ACCESS "RW"

#define	DMA_CH4_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040)

#define	DMA_CH4_CTRL_TRIG_INCR_WRITE_LSB _u(6)

#define	DMA_CH4_CTRL_TRIG_INCR_WRITE_MSB _u(6)

#define	DMA_CH4_CTRL_TRIG_INCR_WRITE_RESET _u(0x0)

#define	DMA_CH4_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW"

#define	DMA_CH4_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080)

#define	DMA_CH4_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7)

#define	DMA_CH4_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7)

#define	DMA_CH4_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0)

#define	DMA_CH4_CTRL_TRIG_IRQ_QUIET_ACCESS "RW"

#define	DMA_CH4_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000)

#define	DMA_CH4_CTRL_TRIG_IRQ_QUIET_LSB _u(23)

#define	DMA_CH4_CTRL_TRIG_IRQ_QUIET_MSB _u(23)

#define	DMA_CH4_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0)

#define	DMA_CH4_CTRL_TRIG_OFFSET _u(0x0000010c)

#define	DMA_CH4_CTRL_TRIG_READ_ERROR_ACCESS "WC"

#define	DMA_CH4_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000)

#define	DMA_CH4_CTRL_TRIG_READ_ERROR_LSB _u(30)

#define	DMA_CH4_CTRL_TRIG_READ_ERROR_MSB _u(30)

#define	DMA_CH4_CTRL_TRIG_READ_ERROR_RESET _u(0x0)

#define	DMA_CH4_CTRL_TRIG_RESET _u(0x00000000)

#define	DMA_CH4_CTRL_TRIG_RING_SEL_ACCESS "RW"

#define	DMA_CH4_CTRL_TRIG_RING_SEL_BITS _u(0x00001000)

#define	DMA_CH4_CTRL_TRIG_RING_SEL_LSB _u(12)

#define	DMA_CH4_CTRL_TRIG_RING_SEL_MSB _u(12)

#define	DMA_CH4_CTRL_TRIG_RING_SEL_RESET _u(0x0)

#define	DMA_CH4_CTRL_TRIG_RING_SIZE_ACCESS "RW"

#define	DMA_CH4_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00)

#define	DMA_CH4_CTRL_TRIG_RING_SIZE_LSB _u(8)

#define	DMA_CH4_CTRL_TRIG_RING_SIZE_MSB _u(11)

#define	DMA_CH4_CTRL_TRIG_RING_SIZE_RESET _u(0x0)

#define	DMA_CH4_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0)

#define	DMA_CH4_CTRL_TRIG_SNIFF_EN_ACCESS "RW"

#define	DMA_CH4_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000)

#define	DMA_CH4_CTRL_TRIG_SNIFF_EN_LSB _u(25)

#define	DMA_CH4_CTRL_TRIG_SNIFF_EN_MSB _u(25)

#define	DMA_CH4_CTRL_TRIG_SNIFF_EN_RESET _u(0x0)

#define	DMA_CH4_CTRL_TRIG_TREQ_SEL_ACCESS "RW"

#define	DMA_CH4_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000)

#define	DMA_CH4_CTRL_TRIG_TREQ_SEL_LSB _u(17)

#define	DMA_CH4_CTRL_TRIG_TREQ_SEL_MSB _u(22)

#define	DMA_CH4_CTRL_TRIG_TREQ_SEL_RESET _u(0x00)

#define	DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f)

#define	DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b)

#define	DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c)

#define	DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d)

#define	DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e)

#define	DMA_CH4_CTRL_TRIG_WRITE_ERROR_ACCESS "WC"

#define	DMA_CH4_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000)

#define	DMA_CH4_CTRL_TRIG_WRITE_ERROR_LSB _u(29)

#define	DMA_CH4_CTRL_TRIG_WRITE_ERROR_MSB _u(29)

#define	DMA_CH4_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0)

#define	DMA_CH4_DBG_CTDREQ_ACCESS "WC"

#define	DMA_CH4_DBG_CTDREQ_BITS _u(0x0000003f)

#define	DMA_CH4_DBG_CTDREQ_LSB _u(0)

#define	DMA_CH4_DBG_CTDREQ_MSB _u(5)

#define	DMA_CH4_DBG_CTDREQ_OFFSET _u(0x00000900)

#define	DMA_CH4_DBG_CTDREQ_RESET _u(0x00000000)

#define	DMA_CH4_DBG_TCR_ACCESS "RO"

#define	DMA_CH4_DBG_TCR_BITS _u(0xffffffff)

#define	DMA_CH4_DBG_TCR_LSB _u(0)

#define	DMA_CH4_DBG_TCR_MSB _u(31)

#define	DMA_CH4_DBG_TCR_OFFSET _u(0x00000904)

#define	DMA_CH4_DBG_TCR_RESET _u(0x00000000)

#define	DMA_CH4_READ_ADDR_ACCESS "RW"

#define	DMA_CH4_READ_ADDR_BITS _u(0xffffffff)

#define	DMA_CH4_READ_ADDR_LSB _u(0)

#define	DMA_CH4_READ_ADDR_MSB _u(31)

#define	DMA_CH4_READ_ADDR_OFFSET _u(0x00000100)

#define	DMA_CH4_READ_ADDR_RESET _u(0x00000000)

#define	DMA_CH4_TRANS_COUNT_BITS _u(0xffffffff)

#define	DMA_CH4_TRANS_COUNT_COUNT_ACCESS "RW"

#define	DMA_CH4_TRANS_COUNT_COUNT_BITS _u(0x0fffffff)

#define	DMA_CH4_TRANS_COUNT_COUNT_LSB _u(0)

#define	DMA_CH4_TRANS_COUNT_COUNT_MSB _u(27)

#define	DMA_CH4_TRANS_COUNT_COUNT_RESET _u(0x0000000)

#define	DMA_CH4_TRANS_COUNT_MODE_ACCESS "RW"

#define	DMA_CH4_TRANS_COUNT_MODE_BITS _u(0xf0000000)

#define	DMA_CH4_TRANS_COUNT_MODE_LSB _u(28)

#define	DMA_CH4_TRANS_COUNT_MODE_MSB _u(31)

#define	DMA_CH4_TRANS_COUNT_MODE_RESET _u(0x0)

#define	DMA_CH4_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf)

#define	DMA_CH4_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0)

#define	DMA_CH4_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1)

#define	DMA_CH4_TRANS_COUNT_OFFSET _u(0x00000108)

#define	DMA_CH4_TRANS_COUNT_RESET _u(0x00000000)

#define	DMA_CH4_WRITE_ADDR_ACCESS "RW"

#define	DMA_CH4_WRITE_ADDR_BITS _u(0xffffffff)

#define	DMA_CH4_WRITE_ADDR_LSB _u(0)

#define	DMA_CH4_WRITE_ADDR_MSB _u(31)

#define	DMA_CH4_WRITE_ADDR_OFFSET _u(0x00000104)

#define	DMA_CH4_WRITE_ADDR_RESET _u(0x00000000)

#define	DMA_CH5_AL1_CTRL_ACCESS "RW"

#define	DMA_CH5_AL1_CTRL_BITS _u(0xffffffff)

#define	DMA_CH5_AL1_CTRL_LSB _u(0)

#define	DMA_CH5_AL1_CTRL_MSB _u(31)

#define	DMA_CH5_AL1_CTRL_OFFSET _u(0x00000150)

#define	DMA_CH5_AL1_CTRL_RESET "-"

#define	DMA_CH5_AL1_READ_ADDR_ACCESS "RW"

#define	DMA_CH5_AL1_READ_ADDR_BITS _u(0xffffffff)

#define	DMA_CH5_AL1_READ_ADDR_LSB _u(0)

#define	DMA_CH5_AL1_READ_ADDR_MSB _u(31)

#define	DMA_CH5_AL1_READ_ADDR_OFFSET _u(0x00000154)

#define	DMA_CH5_AL1_READ_ADDR_RESET "-"

#define	DMA_CH5_AL1_TRANS_COUNT_TRIG_ACCESS "RW"

#define	DMA_CH5_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff)

#define	DMA_CH5_AL1_TRANS_COUNT_TRIG_LSB _u(0)

#define	DMA_CH5_AL1_TRANS_COUNT_TRIG_MSB _u(31)

#define	DMA_CH5_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000015c)

#define	DMA_CH5_AL1_TRANS_COUNT_TRIG_RESET "-"

#define	DMA_CH5_AL1_WRITE_ADDR_ACCESS "RW"

#define	DMA_CH5_AL1_WRITE_ADDR_BITS _u(0xffffffff)

#define	DMA_CH5_AL1_WRITE_ADDR_LSB _u(0)

#define	DMA_CH5_AL1_WRITE_ADDR_MSB _u(31)

#define	DMA_CH5_AL1_WRITE_ADDR_OFFSET _u(0x00000158)

#define	DMA_CH5_AL1_WRITE_ADDR_RESET "-"

#define	DMA_CH5_AL2_CTRL_ACCESS "RW"

#define	DMA_CH5_AL2_CTRL_BITS _u(0xffffffff)

#define	DMA_CH5_AL2_CTRL_LSB _u(0)

#define	DMA_CH5_AL2_CTRL_MSB _u(31)

#define	DMA_CH5_AL2_CTRL_OFFSET _u(0x00000160)

#define	DMA_CH5_AL2_CTRL_RESET "-"

#define	DMA_CH5_AL2_READ_ADDR_ACCESS "RW"

#define	DMA_CH5_AL2_READ_ADDR_BITS _u(0xffffffff)

#define	DMA_CH5_AL2_READ_ADDR_LSB _u(0)

#define	DMA_CH5_AL2_READ_ADDR_MSB _u(31)

#define	DMA_CH5_AL2_READ_ADDR_OFFSET _u(0x00000168)

#define	DMA_CH5_AL2_READ_ADDR_RESET "-"

#define	DMA_CH5_AL2_TRANS_COUNT_ACCESS "RW"

#define	DMA_CH5_AL2_TRANS_COUNT_BITS _u(0xffffffff)

#define	DMA_CH5_AL2_TRANS_COUNT_LSB _u(0)

#define	DMA_CH5_AL2_TRANS_COUNT_MSB _u(31)

#define	DMA_CH5_AL2_TRANS_COUNT_OFFSET _u(0x00000164)

#define	DMA_CH5_AL2_TRANS_COUNT_RESET "-"

#define	DMA_CH5_AL2_WRITE_ADDR_TRIG_ACCESS "RW"

#define	DMA_CH5_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff)

#define	DMA_CH5_AL2_WRITE_ADDR_TRIG_LSB _u(0)

#define	DMA_CH5_AL2_WRITE_ADDR_TRIG_MSB _u(31)

#define	DMA_CH5_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x0000016c)

#define	DMA_CH5_AL2_WRITE_ADDR_TRIG_RESET "-"

#define	DMA_CH5_AL3_CTRL_ACCESS "RW"

#define	DMA_CH5_AL3_CTRL_BITS _u(0xffffffff)

#define	DMA_CH5_AL3_CTRL_LSB _u(0)

#define	DMA_CH5_AL3_CTRL_MSB _u(31)

#define	DMA_CH5_AL3_CTRL_OFFSET _u(0x00000170)

#define	DMA_CH5_AL3_CTRL_RESET "-"

#define	DMA_CH5_AL3_READ_ADDR_TRIG_ACCESS "RW"

#define	DMA_CH5_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff)

#define	DMA_CH5_AL3_READ_ADDR_TRIG_LSB _u(0)

#define	DMA_CH5_AL3_READ_ADDR_TRIG_MSB _u(31)

#define	DMA_CH5_AL3_READ_ADDR_TRIG_OFFSET _u(0x0000017c)

#define	DMA_CH5_AL3_READ_ADDR_TRIG_RESET "-"

#define	DMA_CH5_AL3_TRANS_COUNT_ACCESS "RW"

#define	DMA_CH5_AL3_TRANS_COUNT_BITS _u(0xffffffff)

#define	DMA_CH5_AL3_TRANS_COUNT_LSB _u(0)

#define	DMA_CH5_AL3_TRANS_COUNT_MSB _u(31)

#define	DMA_CH5_AL3_TRANS_COUNT_OFFSET _u(0x00000178)

#define	DMA_CH5_AL3_TRANS_COUNT_RESET "-"

#define	DMA_CH5_AL3_WRITE_ADDR_ACCESS "RW"

#define	DMA_CH5_AL3_WRITE_ADDR_BITS _u(0xffffffff)

#define	DMA_CH5_AL3_WRITE_ADDR_LSB _u(0)

#define	DMA_CH5_AL3_WRITE_ADDR_MSB _u(31)

#define	DMA_CH5_AL3_WRITE_ADDR_OFFSET _u(0x00000174)

#define	DMA_CH5_AL3_WRITE_ADDR_RESET "-"

#define	DMA_CH5_CTRL_TRIG_AHB_ERROR_ACCESS "RO"

#define	DMA_CH5_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000)

#define	DMA_CH5_CTRL_TRIG_AHB_ERROR_LSB _u(31)

#define	DMA_CH5_CTRL_TRIG_AHB_ERROR_MSB _u(31)

#define	DMA_CH5_CTRL_TRIG_AHB_ERROR_RESET _u(0x0)

#define	DMA_CH5_CTRL_TRIG_BITS _u(0xe7ffffff)

#define	DMA_CH5_CTRL_TRIG_BSWAP_ACCESS "RW"

#define	DMA_CH5_CTRL_TRIG_BSWAP_BITS _u(0x01000000)

#define	DMA_CH5_CTRL_TRIG_BSWAP_LSB _u(24)

#define	DMA_CH5_CTRL_TRIG_BSWAP_MSB _u(24)

#define	DMA_CH5_CTRL_TRIG_BSWAP_RESET _u(0x0)

#define	DMA_CH5_CTRL_TRIG_BUSY_ACCESS "RO"

#define	DMA_CH5_CTRL_TRIG_BUSY_BITS _u(0x04000000)

#define	DMA_CH5_CTRL_TRIG_BUSY_LSB _u(26)

#define	DMA_CH5_CTRL_TRIG_BUSY_MSB _u(26)

#define	DMA_CH5_CTRL_TRIG_BUSY_RESET _u(0x0)

#define	DMA_CH5_CTRL_TRIG_CHAIN_TO_ACCESS "RW"

#define	DMA_CH5_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000)

#define	DMA_CH5_CTRL_TRIG_CHAIN_TO_LSB _u(13)

#define	DMA_CH5_CTRL_TRIG_CHAIN_TO_MSB _u(16)

#define	DMA_CH5_CTRL_TRIG_CHAIN_TO_RESET _u(0x0)

#define	DMA_CH5_CTRL_TRIG_DATA_SIZE_ACCESS "RW"

#define	DMA_CH5_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c)

#define	DMA_CH5_CTRL_TRIG_DATA_SIZE_LSB _u(2)

#define	DMA_CH5_CTRL_TRIG_DATA_SIZE_MSB _u(3)

#define	DMA_CH5_CTRL_TRIG_DATA_SIZE_RESET _u(0x0)

#define	DMA_CH5_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0)

#define	DMA_CH5_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1)

#define	DMA_CH5_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2)

#define	DMA_CH5_CTRL_TRIG_EN_ACCESS "RW"

#define	DMA_CH5_CTRL_TRIG_EN_BITS _u(0x00000001)

#define	DMA_CH5_CTRL_TRIG_EN_LSB _u(0)

#define	DMA_CH5_CTRL_TRIG_EN_MSB _u(0)

#define	DMA_CH5_CTRL_TRIG_EN_RESET _u(0x0)

#define	DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW"

#define	DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002)

#define	DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1)

#define	DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1)

#define	DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0)

#define	DMA_CH5_CTRL_TRIG_INCR_READ_ACCESS "RW"

#define	DMA_CH5_CTRL_TRIG_INCR_READ_BITS _u(0x00000010)

#define	DMA_CH5_CTRL_TRIG_INCR_READ_LSB _u(4)

#define	DMA_CH5_CTRL_TRIG_INCR_READ_MSB _u(4)

#define	DMA_CH5_CTRL_TRIG_INCR_READ_RESET _u(0x0)

#define	DMA_CH5_CTRL_TRIG_INCR_READ_REV_ACCESS "RW"

#define	DMA_CH5_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020)

#define	DMA_CH5_CTRL_TRIG_INCR_READ_REV_LSB _u(5)

#define	DMA_CH5_CTRL_TRIG_INCR_READ_REV_MSB _u(5)

#define	DMA_CH5_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0)

#define	DMA_CH5_CTRL_TRIG_INCR_WRITE_ACCESS "RW"

#define	DMA_CH5_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040)

#define	DMA_CH5_CTRL_TRIG_INCR_WRITE_LSB _u(6)

#define	DMA_CH5_CTRL_TRIG_INCR_WRITE_MSB _u(6)

#define	DMA_CH5_CTRL_TRIG_INCR_WRITE_RESET _u(0x0)

#define	DMA_CH5_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW"

#define	DMA_CH5_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080)

#define	DMA_CH5_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7)

#define	DMA_CH5_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7)

#define	DMA_CH5_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0)

#define	DMA_CH5_CTRL_TRIG_IRQ_QUIET_ACCESS "RW"

#define	DMA_CH5_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000)

#define	DMA_CH5_CTRL_TRIG_IRQ_QUIET_LSB _u(23)

#define	DMA_CH5_CTRL_TRIG_IRQ_QUIET_MSB _u(23)

#define	DMA_CH5_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0)

#define	DMA_CH5_CTRL_TRIG_OFFSET _u(0x0000014c)

#define	DMA_CH5_CTRL_TRIG_READ_ERROR_ACCESS "WC"

#define	DMA_CH5_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000)

#define	DMA_CH5_CTRL_TRIG_READ_ERROR_LSB _u(30)

#define	DMA_CH5_CTRL_TRIG_READ_ERROR_MSB _u(30)

#define	DMA_CH5_CTRL_TRIG_READ_ERROR_RESET _u(0x0)

#define	DMA_CH5_CTRL_TRIG_RESET _u(0x00000000)

#define	DMA_CH5_CTRL_TRIG_RING_SEL_ACCESS "RW"

#define	DMA_CH5_CTRL_TRIG_RING_SEL_BITS _u(0x00001000)

#define	DMA_CH5_CTRL_TRIG_RING_SEL_LSB _u(12)

#define	DMA_CH5_CTRL_TRIG_RING_SEL_MSB _u(12)

#define	DMA_CH5_CTRL_TRIG_RING_SEL_RESET _u(0x0)

#define	DMA_CH5_CTRL_TRIG_RING_SIZE_ACCESS "RW"

#define	DMA_CH5_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00)

#define	DMA_CH5_CTRL_TRIG_RING_SIZE_LSB _u(8)

#define	DMA_CH5_CTRL_TRIG_RING_SIZE_MSB _u(11)

#define	DMA_CH5_CTRL_TRIG_RING_SIZE_RESET _u(0x0)

#define	DMA_CH5_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0)

#define	DMA_CH5_CTRL_TRIG_SNIFF_EN_ACCESS "RW"

#define	DMA_CH5_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000)

#define	DMA_CH5_CTRL_TRIG_SNIFF_EN_LSB _u(25)

#define	DMA_CH5_CTRL_TRIG_SNIFF_EN_MSB _u(25)

#define	DMA_CH5_CTRL_TRIG_SNIFF_EN_RESET _u(0x0)

#define	DMA_CH5_CTRL_TRIG_TREQ_SEL_ACCESS "RW"

#define	DMA_CH5_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000)

#define	DMA_CH5_CTRL_TRIG_TREQ_SEL_LSB _u(17)

#define	DMA_CH5_CTRL_TRIG_TREQ_SEL_MSB _u(22)

#define	DMA_CH5_CTRL_TRIG_TREQ_SEL_RESET _u(0x00)

#define	DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f)

#define	DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b)

#define	DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c)

#define	DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d)

#define	DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e)

#define	DMA_CH5_CTRL_TRIG_WRITE_ERROR_ACCESS "WC"

#define	DMA_CH5_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000)

#define	DMA_CH5_CTRL_TRIG_WRITE_ERROR_LSB _u(29)

#define	DMA_CH5_CTRL_TRIG_WRITE_ERROR_MSB _u(29)

#define	DMA_CH5_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0)

#define	DMA_CH5_DBG_CTDREQ_ACCESS "WC"

#define	DMA_CH5_DBG_CTDREQ_BITS _u(0x0000003f)

#define	DMA_CH5_DBG_CTDREQ_LSB _u(0)

#define	DMA_CH5_DBG_CTDREQ_MSB _u(5)

#define	DMA_CH5_DBG_CTDREQ_OFFSET _u(0x00000940)

#define	DMA_CH5_DBG_CTDREQ_RESET _u(0x00000000)

#define	DMA_CH5_DBG_TCR_ACCESS "RO"

#define	DMA_CH5_DBG_TCR_BITS _u(0xffffffff)

#define	DMA_CH5_DBG_TCR_LSB _u(0)

#define	DMA_CH5_DBG_TCR_MSB _u(31)

#define	DMA_CH5_DBG_TCR_OFFSET _u(0x00000944)

#define	DMA_CH5_DBG_TCR_RESET _u(0x00000000)

#define	DMA_CH5_READ_ADDR_ACCESS "RW"

#define	DMA_CH5_READ_ADDR_BITS _u(0xffffffff)

#define	DMA_CH5_READ_ADDR_LSB _u(0)

#define	DMA_CH5_READ_ADDR_MSB _u(31)

#define	DMA_CH5_READ_ADDR_OFFSET _u(0x00000140)

#define	DMA_CH5_READ_ADDR_RESET _u(0x00000000)

#define	DMA_CH5_TRANS_COUNT_BITS _u(0xffffffff)

#define	DMA_CH5_TRANS_COUNT_COUNT_ACCESS "RW"

#define	DMA_CH5_TRANS_COUNT_COUNT_BITS _u(0x0fffffff)

#define	DMA_CH5_TRANS_COUNT_COUNT_LSB _u(0)

#define	DMA_CH5_TRANS_COUNT_COUNT_MSB _u(27)

#define	DMA_CH5_TRANS_COUNT_COUNT_RESET _u(0x0000000)

#define	DMA_CH5_TRANS_COUNT_MODE_ACCESS "RW"

#define	DMA_CH5_TRANS_COUNT_MODE_BITS _u(0xf0000000)

#define	DMA_CH5_TRANS_COUNT_MODE_LSB _u(28)

#define	DMA_CH5_TRANS_COUNT_MODE_MSB _u(31)

#define	DMA_CH5_TRANS_COUNT_MODE_RESET _u(0x0)

#define	DMA_CH5_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf)

#define	DMA_CH5_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0)

#define	DMA_CH5_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1)

#define	DMA_CH5_TRANS_COUNT_OFFSET _u(0x00000148)

#define	DMA_CH5_TRANS_COUNT_RESET _u(0x00000000)

#define	DMA_CH5_WRITE_ADDR_ACCESS "RW"

#define	DMA_CH5_WRITE_ADDR_BITS _u(0xffffffff)

#define	DMA_CH5_WRITE_ADDR_LSB _u(0)

#define	DMA_CH5_WRITE_ADDR_MSB _u(31)

#define	DMA_CH5_WRITE_ADDR_OFFSET _u(0x00000144)

#define	DMA_CH5_WRITE_ADDR_RESET _u(0x00000000)

#define	DMA_CH6_AL1_CTRL_ACCESS "RW"

#define	DMA_CH6_AL1_CTRL_BITS _u(0xffffffff)

#define	DMA_CH6_AL1_CTRL_LSB _u(0)

#define	DMA_CH6_AL1_CTRL_MSB _u(31)

#define	DMA_CH6_AL1_CTRL_OFFSET _u(0x00000190)

#define	DMA_CH6_AL1_CTRL_RESET "-"

#define	DMA_CH6_AL1_READ_ADDR_ACCESS "RW"

#define	DMA_CH6_AL1_READ_ADDR_BITS _u(0xffffffff)

#define	DMA_CH6_AL1_READ_ADDR_LSB _u(0)

#define	DMA_CH6_AL1_READ_ADDR_MSB _u(31)

#define	DMA_CH6_AL1_READ_ADDR_OFFSET _u(0x00000194)

#define	DMA_CH6_AL1_READ_ADDR_RESET "-"

#define	DMA_CH6_AL1_TRANS_COUNT_TRIG_ACCESS "RW"

#define	DMA_CH6_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff)

#define	DMA_CH6_AL1_TRANS_COUNT_TRIG_LSB _u(0)

#define	DMA_CH6_AL1_TRANS_COUNT_TRIG_MSB _u(31)

#define	DMA_CH6_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000019c)

#define	DMA_CH6_AL1_TRANS_COUNT_TRIG_RESET "-"

#define	DMA_CH6_AL1_WRITE_ADDR_ACCESS "RW"

#define	DMA_CH6_AL1_WRITE_ADDR_BITS _u(0xffffffff)

#define	DMA_CH6_AL1_WRITE_ADDR_LSB _u(0)

#define	DMA_CH6_AL1_WRITE_ADDR_MSB _u(31)

#define	DMA_CH6_AL1_WRITE_ADDR_OFFSET _u(0x00000198)

#define	DMA_CH6_AL1_WRITE_ADDR_RESET "-"

#define	DMA_CH6_AL2_CTRL_ACCESS "RW"

#define	DMA_CH6_AL2_CTRL_BITS _u(0xffffffff)

#define	DMA_CH6_AL2_CTRL_LSB _u(0)

#define	DMA_CH6_AL2_CTRL_MSB _u(31)

#define	DMA_CH6_AL2_CTRL_OFFSET _u(0x000001a0)

#define	DMA_CH6_AL2_CTRL_RESET "-"

#define	DMA_CH6_AL2_READ_ADDR_ACCESS "RW"

#define	DMA_CH6_AL2_READ_ADDR_BITS _u(0xffffffff)

#define	DMA_CH6_AL2_READ_ADDR_LSB _u(0)

#define	DMA_CH6_AL2_READ_ADDR_MSB _u(31)

#define	DMA_CH6_AL2_READ_ADDR_OFFSET _u(0x000001a8)

#define	DMA_CH6_AL2_READ_ADDR_RESET "-"

#define	DMA_CH6_AL2_TRANS_COUNT_ACCESS "RW"

#define	DMA_CH6_AL2_TRANS_COUNT_BITS _u(0xffffffff)

#define	DMA_CH6_AL2_TRANS_COUNT_LSB _u(0)

#define	DMA_CH6_AL2_TRANS_COUNT_MSB _u(31)

#define	DMA_CH6_AL2_TRANS_COUNT_OFFSET _u(0x000001a4)

#define	DMA_CH6_AL2_TRANS_COUNT_RESET "-"

#define	DMA_CH6_AL2_WRITE_ADDR_TRIG_ACCESS "RW"

#define	DMA_CH6_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff)

#define	DMA_CH6_AL2_WRITE_ADDR_TRIG_LSB _u(0)

#define	DMA_CH6_AL2_WRITE_ADDR_TRIG_MSB _u(31)

#define	DMA_CH6_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x000001ac)

#define	DMA_CH6_AL2_WRITE_ADDR_TRIG_RESET "-"

#define	DMA_CH6_AL3_CTRL_ACCESS "RW"

#define	DMA_CH6_AL3_CTRL_BITS _u(0xffffffff)

#define	DMA_CH6_AL3_CTRL_LSB _u(0)

#define	DMA_CH6_AL3_CTRL_MSB _u(31)

#define	DMA_CH6_AL3_CTRL_OFFSET _u(0x000001b0)

#define	DMA_CH6_AL3_CTRL_RESET "-"

#define	DMA_CH6_AL3_READ_ADDR_TRIG_ACCESS "RW"

#define	DMA_CH6_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff)

#define	DMA_CH6_AL3_READ_ADDR_TRIG_LSB _u(0)

#define	DMA_CH6_AL3_READ_ADDR_TRIG_MSB _u(31)

#define	DMA_CH6_AL3_READ_ADDR_TRIG_OFFSET _u(0x000001bc)

#define	DMA_CH6_AL3_READ_ADDR_TRIG_RESET "-"

#define	DMA_CH6_AL3_TRANS_COUNT_ACCESS "RW"

#define	DMA_CH6_AL3_TRANS_COUNT_BITS _u(0xffffffff)

#define	DMA_CH6_AL3_TRANS_COUNT_LSB _u(0)

#define	DMA_CH6_AL3_TRANS_COUNT_MSB _u(31)

#define	DMA_CH6_AL3_TRANS_COUNT_OFFSET _u(0x000001b8)

#define	DMA_CH6_AL3_TRANS_COUNT_RESET "-"

#define	DMA_CH6_AL3_WRITE_ADDR_ACCESS "RW"

#define	DMA_CH6_AL3_WRITE_ADDR_BITS _u(0xffffffff)

#define	DMA_CH6_AL3_WRITE_ADDR_LSB _u(0)

#define	DMA_CH6_AL3_WRITE_ADDR_MSB _u(31)

#define	DMA_CH6_AL3_WRITE_ADDR_OFFSET _u(0x000001b4)

#define	DMA_CH6_AL3_WRITE_ADDR_RESET "-"

#define	DMA_CH6_CTRL_TRIG_AHB_ERROR_ACCESS "RO"

#define	DMA_CH6_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000)

#define	DMA_CH6_CTRL_TRIG_AHB_ERROR_LSB _u(31)

#define	DMA_CH6_CTRL_TRIG_AHB_ERROR_MSB _u(31)

#define	DMA_CH6_CTRL_TRIG_AHB_ERROR_RESET _u(0x0)

#define	DMA_CH6_CTRL_TRIG_BITS _u(0xe7ffffff)

#define	DMA_CH6_CTRL_TRIG_BSWAP_ACCESS "RW"

#define	DMA_CH6_CTRL_TRIG_BSWAP_BITS _u(0x01000000)

#define	DMA_CH6_CTRL_TRIG_BSWAP_LSB _u(24)

#define	DMA_CH6_CTRL_TRIG_BSWAP_MSB _u(24)

#define	DMA_CH6_CTRL_TRIG_BSWAP_RESET _u(0x0)

#define	DMA_CH6_CTRL_TRIG_BUSY_ACCESS "RO"

#define	DMA_CH6_CTRL_TRIG_BUSY_BITS _u(0x04000000)

#define	DMA_CH6_CTRL_TRIG_BUSY_LSB _u(26)

#define	DMA_CH6_CTRL_TRIG_BUSY_MSB _u(26)

#define	DMA_CH6_CTRL_TRIG_BUSY_RESET _u(0x0)

#define	DMA_CH6_CTRL_TRIG_CHAIN_TO_ACCESS "RW"

#define	DMA_CH6_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000)

#define	DMA_CH6_CTRL_TRIG_CHAIN_TO_LSB _u(13)

#define	DMA_CH6_CTRL_TRIG_CHAIN_TO_MSB _u(16)

#define	DMA_CH6_CTRL_TRIG_CHAIN_TO_RESET _u(0x0)

#define	DMA_CH6_CTRL_TRIG_DATA_SIZE_ACCESS "RW"

#define	DMA_CH6_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c)

#define	DMA_CH6_CTRL_TRIG_DATA_SIZE_LSB _u(2)

#define	DMA_CH6_CTRL_TRIG_DATA_SIZE_MSB _u(3)

#define	DMA_CH6_CTRL_TRIG_DATA_SIZE_RESET _u(0x0)

#define	DMA_CH6_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0)

#define	DMA_CH6_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1)

#define	DMA_CH6_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2)

#define	DMA_CH6_CTRL_TRIG_EN_ACCESS "RW"

#define	DMA_CH6_CTRL_TRIG_EN_BITS _u(0x00000001)

#define	DMA_CH6_CTRL_TRIG_EN_LSB _u(0)

#define	DMA_CH6_CTRL_TRIG_EN_MSB _u(0)

#define	DMA_CH6_CTRL_TRIG_EN_RESET _u(0x0)

#define	DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW"

#define	DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002)

#define	DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1)

#define	DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1)

#define	DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0)

#define	DMA_CH6_CTRL_TRIG_INCR_READ_ACCESS "RW"

#define	DMA_CH6_CTRL_TRIG_INCR_READ_BITS _u(0x00000010)

#define	DMA_CH6_CTRL_TRIG_INCR_READ_LSB _u(4)

#define	DMA_CH6_CTRL_TRIG_INCR_READ_MSB _u(4)

#define	DMA_CH6_CTRL_TRIG_INCR_READ_RESET _u(0x0)

#define	DMA_CH6_CTRL_TRIG_INCR_READ_REV_ACCESS "RW"

#define	DMA_CH6_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020)

#define	DMA_CH6_CTRL_TRIG_INCR_READ_REV_LSB _u(5)

#define	DMA_CH6_CTRL_TRIG_INCR_READ_REV_MSB _u(5)

#define	DMA_CH6_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0)

#define	DMA_CH6_CTRL_TRIG_INCR_WRITE_ACCESS "RW"

#define	DMA_CH6_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040)

#define	DMA_CH6_CTRL_TRIG_INCR_WRITE_LSB _u(6)

#define	DMA_CH6_CTRL_TRIG_INCR_WRITE_MSB _u(6)

#define	DMA_CH6_CTRL_TRIG_INCR_WRITE_RESET _u(0x0)

#define	DMA_CH6_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW"

#define	DMA_CH6_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080)

#define	DMA_CH6_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7)

#define	DMA_CH6_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7)

#define	DMA_CH6_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0)

#define	DMA_CH6_CTRL_TRIG_IRQ_QUIET_ACCESS "RW"

#define	DMA_CH6_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000)

#define	DMA_CH6_CTRL_TRIG_IRQ_QUIET_LSB _u(23)

#define	DMA_CH6_CTRL_TRIG_IRQ_QUIET_MSB _u(23)

#define	DMA_CH6_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0)

#define	DMA_CH6_CTRL_TRIG_OFFSET _u(0x0000018c)

#define	DMA_CH6_CTRL_TRIG_READ_ERROR_ACCESS "WC"

#define	DMA_CH6_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000)

#define	DMA_CH6_CTRL_TRIG_READ_ERROR_LSB _u(30)

#define	DMA_CH6_CTRL_TRIG_READ_ERROR_MSB _u(30)

#define	DMA_CH6_CTRL_TRIG_READ_ERROR_RESET _u(0x0)

#define	DMA_CH6_CTRL_TRIG_RESET _u(0x00000000)

#define	DMA_CH6_CTRL_TRIG_RING_SEL_ACCESS "RW"

#define	DMA_CH6_CTRL_TRIG_RING_SEL_BITS _u(0x00001000)

#define	DMA_CH6_CTRL_TRIG_RING_SEL_LSB _u(12)

#define	DMA_CH6_CTRL_TRIG_RING_SEL_MSB _u(12)

#define	DMA_CH6_CTRL_TRIG_RING_SEL_RESET _u(0x0)

#define	DMA_CH6_CTRL_TRIG_RING_SIZE_ACCESS "RW"

#define	DMA_CH6_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00)

#define	DMA_CH6_CTRL_TRIG_RING_SIZE_LSB _u(8)

#define	DMA_CH6_CTRL_TRIG_RING_SIZE_MSB _u(11)

#define	DMA_CH6_CTRL_TRIG_RING_SIZE_RESET _u(0x0)

#define	DMA_CH6_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0)

#define	DMA_CH6_CTRL_TRIG_SNIFF_EN_ACCESS "RW"

#define	DMA_CH6_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000)

#define	DMA_CH6_CTRL_TRIG_SNIFF_EN_LSB _u(25)

#define	DMA_CH6_CTRL_TRIG_SNIFF_EN_MSB _u(25)

#define	DMA_CH6_CTRL_TRIG_SNIFF_EN_RESET _u(0x0)

#define	DMA_CH6_CTRL_TRIG_TREQ_SEL_ACCESS "RW"

#define	DMA_CH6_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000)

#define	DMA_CH6_CTRL_TRIG_TREQ_SEL_LSB _u(17)

#define	DMA_CH6_CTRL_TRIG_TREQ_SEL_MSB _u(22)

#define	DMA_CH6_CTRL_TRIG_TREQ_SEL_RESET _u(0x00)

#define	DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f)

#define	DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b)

#define	DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c)

#define	DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d)

#define	DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e)

#define	DMA_CH6_CTRL_TRIG_WRITE_ERROR_ACCESS "WC"

#define	DMA_CH6_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000)

#define	DMA_CH6_CTRL_TRIG_WRITE_ERROR_LSB _u(29)

#define	DMA_CH6_CTRL_TRIG_WRITE_ERROR_MSB _u(29)

#define	DMA_CH6_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0)

#define	DMA_CH6_DBG_CTDREQ_ACCESS "WC"

#define	DMA_CH6_DBG_CTDREQ_BITS _u(0x0000003f)

#define	DMA_CH6_DBG_CTDREQ_LSB _u(0)

#define	DMA_CH6_DBG_CTDREQ_MSB _u(5)

#define	DMA_CH6_DBG_CTDREQ_OFFSET _u(0x00000980)

#define	DMA_CH6_DBG_CTDREQ_RESET _u(0x00000000)

#define	DMA_CH6_DBG_TCR_ACCESS "RO"

#define	DMA_CH6_DBG_TCR_BITS _u(0xffffffff)

#define	DMA_CH6_DBG_TCR_LSB _u(0)

#define	DMA_CH6_DBG_TCR_MSB _u(31)

#define	DMA_CH6_DBG_TCR_OFFSET _u(0x00000984)

#define	DMA_CH6_DBG_TCR_RESET _u(0x00000000)

#define	DMA_CH6_READ_ADDR_ACCESS "RW"

#define	DMA_CH6_READ_ADDR_BITS _u(0xffffffff)

#define	DMA_CH6_READ_ADDR_LSB _u(0)

#define	DMA_CH6_READ_ADDR_MSB _u(31)

#define	DMA_CH6_READ_ADDR_OFFSET _u(0x00000180)

#define	DMA_CH6_READ_ADDR_RESET _u(0x00000000)

#define	DMA_CH6_TRANS_COUNT_BITS _u(0xffffffff)

#define	DMA_CH6_TRANS_COUNT_COUNT_ACCESS "RW"

#define	DMA_CH6_TRANS_COUNT_COUNT_BITS _u(0x0fffffff)

#define	DMA_CH6_TRANS_COUNT_COUNT_LSB _u(0)

#define	DMA_CH6_TRANS_COUNT_COUNT_MSB _u(27)

#define	DMA_CH6_TRANS_COUNT_COUNT_RESET _u(0x0000000)

#define	DMA_CH6_TRANS_COUNT_MODE_ACCESS "RW"

#define	DMA_CH6_TRANS_COUNT_MODE_BITS _u(0xf0000000)

#define	DMA_CH6_TRANS_COUNT_MODE_LSB _u(28)

#define	DMA_CH6_TRANS_COUNT_MODE_MSB _u(31)

#define	DMA_CH6_TRANS_COUNT_MODE_RESET _u(0x0)

#define	DMA_CH6_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf)

#define	DMA_CH6_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0)

#define	DMA_CH6_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1)

#define	DMA_CH6_TRANS_COUNT_OFFSET _u(0x00000188)

#define	DMA_CH6_TRANS_COUNT_RESET _u(0x00000000)

#define	DMA_CH6_WRITE_ADDR_ACCESS "RW"

#define	DMA_CH6_WRITE_ADDR_BITS _u(0xffffffff)

#define	DMA_CH6_WRITE_ADDR_LSB _u(0)

#define	DMA_CH6_WRITE_ADDR_MSB _u(31)

#define	DMA_CH6_WRITE_ADDR_OFFSET _u(0x00000184)

#define	DMA_CH6_WRITE_ADDR_RESET _u(0x00000000)

#define	DMA_CH7_AL1_CTRL_ACCESS "RW"

#define	DMA_CH7_AL1_CTRL_BITS _u(0xffffffff)

#define	DMA_CH7_AL1_CTRL_LSB _u(0)

#define	DMA_CH7_AL1_CTRL_MSB _u(31)

#define	DMA_CH7_AL1_CTRL_OFFSET _u(0x000001d0)

#define	DMA_CH7_AL1_CTRL_RESET "-"

#define	DMA_CH7_AL1_READ_ADDR_ACCESS "RW"

#define	DMA_CH7_AL1_READ_ADDR_BITS _u(0xffffffff)

#define	DMA_CH7_AL1_READ_ADDR_LSB _u(0)

#define	DMA_CH7_AL1_READ_ADDR_MSB _u(31)

#define	DMA_CH7_AL1_READ_ADDR_OFFSET _u(0x000001d4)

#define	DMA_CH7_AL1_READ_ADDR_RESET "-"

#define	DMA_CH7_AL1_TRANS_COUNT_TRIG_ACCESS "RW"

#define	DMA_CH7_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff)

#define	DMA_CH7_AL1_TRANS_COUNT_TRIG_LSB _u(0)

#define	DMA_CH7_AL1_TRANS_COUNT_TRIG_MSB _u(31)

#define	DMA_CH7_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x000001dc)

#define	DMA_CH7_AL1_TRANS_COUNT_TRIG_RESET "-"

#define	DMA_CH7_AL1_WRITE_ADDR_ACCESS "RW"

#define	DMA_CH7_AL1_WRITE_ADDR_BITS _u(0xffffffff)

#define	DMA_CH7_AL1_WRITE_ADDR_LSB _u(0)

#define	DMA_CH7_AL1_WRITE_ADDR_MSB _u(31)

#define	DMA_CH7_AL1_WRITE_ADDR_OFFSET _u(0x000001d8)

#define	DMA_CH7_AL1_WRITE_ADDR_RESET "-"

#define	DMA_CH7_AL2_CTRL_ACCESS "RW"

#define	DMA_CH7_AL2_CTRL_BITS _u(0xffffffff)

#define	DMA_CH7_AL2_CTRL_LSB _u(0)

#define	DMA_CH7_AL2_CTRL_MSB _u(31)

#define	DMA_CH7_AL2_CTRL_OFFSET _u(0x000001e0)

#define	DMA_CH7_AL2_CTRL_RESET "-"

#define	DMA_CH7_AL2_READ_ADDR_ACCESS "RW"

#define	DMA_CH7_AL2_READ_ADDR_BITS _u(0xffffffff)

#define	DMA_CH7_AL2_READ_ADDR_LSB _u(0)

#define	DMA_CH7_AL2_READ_ADDR_MSB _u(31)

#define	DMA_CH7_AL2_READ_ADDR_OFFSET _u(0x000001e8)

#define	DMA_CH7_AL2_READ_ADDR_RESET "-"

#define	DMA_CH7_AL2_TRANS_COUNT_ACCESS "RW"

#define	DMA_CH7_AL2_TRANS_COUNT_BITS _u(0xffffffff)

#define	DMA_CH7_AL2_TRANS_COUNT_LSB _u(0)

#define	DMA_CH7_AL2_TRANS_COUNT_MSB _u(31)

#define	DMA_CH7_AL2_TRANS_COUNT_OFFSET _u(0x000001e4)

#define	DMA_CH7_AL2_TRANS_COUNT_RESET "-"

#define	DMA_CH7_AL2_WRITE_ADDR_TRIG_ACCESS "RW"

#define	DMA_CH7_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff)

#define	DMA_CH7_AL2_WRITE_ADDR_TRIG_LSB _u(0)

#define	DMA_CH7_AL2_WRITE_ADDR_TRIG_MSB _u(31)

#define	DMA_CH7_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x000001ec)

#define	DMA_CH7_AL2_WRITE_ADDR_TRIG_RESET "-"

#define	DMA_CH7_AL3_CTRL_ACCESS "RW"

#define	DMA_CH7_AL3_CTRL_BITS _u(0xffffffff)

#define	DMA_CH7_AL3_CTRL_LSB _u(0)

#define	DMA_CH7_AL3_CTRL_MSB _u(31)

#define	DMA_CH7_AL3_CTRL_OFFSET _u(0x000001f0)

#define	DMA_CH7_AL3_CTRL_RESET "-"

#define	DMA_CH7_AL3_READ_ADDR_TRIG_ACCESS "RW"

#define	DMA_CH7_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff)

#define	DMA_CH7_AL3_READ_ADDR_TRIG_LSB _u(0)

#define	DMA_CH7_AL3_READ_ADDR_TRIG_MSB _u(31)

#define	DMA_CH7_AL3_READ_ADDR_TRIG_OFFSET _u(0x000001fc)

#define	DMA_CH7_AL3_READ_ADDR_TRIG_RESET "-"

#define	DMA_CH7_AL3_TRANS_COUNT_ACCESS "RW"

#define	DMA_CH7_AL3_TRANS_COUNT_BITS _u(0xffffffff)

#define	DMA_CH7_AL3_TRANS_COUNT_LSB _u(0)

#define	DMA_CH7_AL3_TRANS_COUNT_MSB _u(31)

#define	DMA_CH7_AL3_TRANS_COUNT_OFFSET _u(0x000001f8)

#define	DMA_CH7_AL3_TRANS_COUNT_RESET "-"

#define	DMA_CH7_AL3_WRITE_ADDR_ACCESS "RW"

#define	DMA_CH7_AL3_WRITE_ADDR_BITS _u(0xffffffff)

#define	DMA_CH7_AL3_WRITE_ADDR_LSB _u(0)

#define	DMA_CH7_AL3_WRITE_ADDR_MSB _u(31)

#define	DMA_CH7_AL3_WRITE_ADDR_OFFSET _u(0x000001f4)

#define	DMA_CH7_AL3_WRITE_ADDR_RESET "-"

#define	DMA_CH7_CTRL_TRIG_AHB_ERROR_ACCESS "RO"

#define	DMA_CH7_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000)

#define	DMA_CH7_CTRL_TRIG_AHB_ERROR_LSB _u(31)

#define	DMA_CH7_CTRL_TRIG_AHB_ERROR_MSB _u(31)

#define	DMA_CH7_CTRL_TRIG_AHB_ERROR_RESET _u(0x0)

#define	DMA_CH7_CTRL_TRIG_BITS _u(0xe7ffffff)

#define	DMA_CH7_CTRL_TRIG_BSWAP_ACCESS "RW"

#define	DMA_CH7_CTRL_TRIG_BSWAP_BITS _u(0x01000000)

#define	DMA_CH7_CTRL_TRIG_BSWAP_LSB _u(24)

#define	DMA_CH7_CTRL_TRIG_BSWAP_MSB _u(24)

#define	DMA_CH7_CTRL_TRIG_BSWAP_RESET _u(0x0)

#define	DMA_CH7_CTRL_TRIG_BUSY_ACCESS "RO"

#define	DMA_CH7_CTRL_TRIG_BUSY_BITS _u(0x04000000)

#define	DMA_CH7_CTRL_TRIG_BUSY_LSB _u(26)

#define	DMA_CH7_CTRL_TRIG_BUSY_MSB _u(26)

#define	DMA_CH7_CTRL_TRIG_BUSY_RESET _u(0x0)

#define	DMA_CH7_CTRL_TRIG_CHAIN_TO_ACCESS "RW"

#define	DMA_CH7_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000)

#define	DMA_CH7_CTRL_TRIG_CHAIN_TO_LSB _u(13)

#define	DMA_CH7_CTRL_TRIG_CHAIN_TO_MSB _u(16)

#define	DMA_CH7_CTRL_TRIG_CHAIN_TO_RESET _u(0x0)

#define	DMA_CH7_CTRL_TRIG_DATA_SIZE_ACCESS "RW"

#define	DMA_CH7_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c)

#define	DMA_CH7_CTRL_TRIG_DATA_SIZE_LSB _u(2)

#define	DMA_CH7_CTRL_TRIG_DATA_SIZE_MSB _u(3)

#define	DMA_CH7_CTRL_TRIG_DATA_SIZE_RESET _u(0x0)

#define	DMA_CH7_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0)

#define	DMA_CH7_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1)

#define	DMA_CH7_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2)

#define	DMA_CH7_CTRL_TRIG_EN_ACCESS "RW"

#define	DMA_CH7_CTRL_TRIG_EN_BITS _u(0x00000001)

#define	DMA_CH7_CTRL_TRIG_EN_LSB _u(0)

#define	DMA_CH7_CTRL_TRIG_EN_MSB _u(0)

#define	DMA_CH7_CTRL_TRIG_EN_RESET _u(0x0)

#define	DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW"

#define	DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002)

#define	DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1)

#define	DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1)

#define	DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0)

#define	DMA_CH7_CTRL_TRIG_INCR_READ_ACCESS "RW"

#define	DMA_CH7_CTRL_TRIG_INCR_READ_BITS _u(0x00000010)

#define	DMA_CH7_CTRL_TRIG_INCR_READ_LSB _u(4)

#define	DMA_CH7_CTRL_TRIG_INCR_READ_MSB _u(4)

#define	DMA_CH7_CTRL_TRIG_INCR_READ_RESET _u(0x0)

#define	DMA_CH7_CTRL_TRIG_INCR_READ_REV_ACCESS "RW"

#define	DMA_CH7_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020)

#define	DMA_CH7_CTRL_TRIG_INCR_READ_REV_LSB _u(5)

#define	DMA_CH7_CTRL_TRIG_INCR_READ_REV_MSB _u(5)

#define	DMA_CH7_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0)

#define	DMA_CH7_CTRL_TRIG_INCR_WRITE_ACCESS "RW"

#define	DMA_CH7_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040)

#define	DMA_CH7_CTRL_TRIG_INCR_WRITE_LSB _u(6)

#define	DMA_CH7_CTRL_TRIG_INCR_WRITE_MSB _u(6)

#define	DMA_CH7_CTRL_TRIG_INCR_WRITE_RESET _u(0x0)

#define	DMA_CH7_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW"

#define	DMA_CH7_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080)

#define	DMA_CH7_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7)

#define	DMA_CH7_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7)

#define	DMA_CH7_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0)

#define	DMA_CH7_CTRL_TRIG_IRQ_QUIET_ACCESS "RW"

#define	DMA_CH7_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000)

#define	DMA_CH7_CTRL_TRIG_IRQ_QUIET_LSB _u(23)

#define	DMA_CH7_CTRL_TRIG_IRQ_QUIET_MSB _u(23)

#define	DMA_CH7_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0)

#define	DMA_CH7_CTRL_TRIG_OFFSET _u(0x000001cc)

#define	DMA_CH7_CTRL_TRIG_READ_ERROR_ACCESS "WC"

#define	DMA_CH7_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000)

#define	DMA_CH7_CTRL_TRIG_READ_ERROR_LSB _u(30)

#define	DMA_CH7_CTRL_TRIG_READ_ERROR_MSB _u(30)

#define	DMA_CH7_CTRL_TRIG_READ_ERROR_RESET _u(0x0)

#define	DMA_CH7_CTRL_TRIG_RESET _u(0x00000000)

#define	DMA_CH7_CTRL_TRIG_RING_SEL_ACCESS "RW"

#define	DMA_CH7_CTRL_TRIG_RING_SEL_BITS _u(0x00001000)

#define	DMA_CH7_CTRL_TRIG_RING_SEL_LSB _u(12)

#define	DMA_CH7_CTRL_TRIG_RING_SEL_MSB _u(12)

#define	DMA_CH7_CTRL_TRIG_RING_SEL_RESET _u(0x0)

#define	DMA_CH7_CTRL_TRIG_RING_SIZE_ACCESS "RW"

#define	DMA_CH7_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00)

#define	DMA_CH7_CTRL_TRIG_RING_SIZE_LSB _u(8)

#define	DMA_CH7_CTRL_TRIG_RING_SIZE_MSB _u(11)

#define	DMA_CH7_CTRL_TRIG_RING_SIZE_RESET _u(0x0)

#define	DMA_CH7_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0)

#define	DMA_CH7_CTRL_TRIG_SNIFF_EN_ACCESS "RW"

#define	DMA_CH7_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000)

#define	DMA_CH7_CTRL_TRIG_SNIFF_EN_LSB _u(25)

#define	DMA_CH7_CTRL_TRIG_SNIFF_EN_MSB _u(25)

#define	DMA_CH7_CTRL_TRIG_SNIFF_EN_RESET _u(0x0)

#define	DMA_CH7_CTRL_TRIG_TREQ_SEL_ACCESS "RW"

#define	DMA_CH7_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000)

#define	DMA_CH7_CTRL_TRIG_TREQ_SEL_LSB _u(17)

#define	DMA_CH7_CTRL_TRIG_TREQ_SEL_MSB _u(22)

#define	DMA_CH7_CTRL_TRIG_TREQ_SEL_RESET _u(0x00)

#define	DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f)

#define	DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b)

#define	DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c)

#define	DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d)

#define	DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e)

#define	DMA_CH7_CTRL_TRIG_WRITE_ERROR_ACCESS "WC"

#define	DMA_CH7_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000)

#define	DMA_CH7_CTRL_TRIG_WRITE_ERROR_LSB _u(29)

#define	DMA_CH7_CTRL_TRIG_WRITE_ERROR_MSB _u(29)

#define	DMA_CH7_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0)

#define	DMA_CH7_DBG_CTDREQ_ACCESS "WC"

#define	DMA_CH7_DBG_CTDREQ_BITS _u(0x0000003f)

#define	DMA_CH7_DBG_CTDREQ_LSB _u(0)

#define	DMA_CH7_DBG_CTDREQ_MSB _u(5)

#define	DMA_CH7_DBG_CTDREQ_OFFSET _u(0x000009c0)

#define	DMA_CH7_DBG_CTDREQ_RESET _u(0x00000000)

#define	DMA_CH7_DBG_TCR_ACCESS "RO"

#define	DMA_CH7_DBG_TCR_BITS _u(0xffffffff)

#define	DMA_CH7_DBG_TCR_LSB _u(0)

#define	DMA_CH7_DBG_TCR_MSB _u(31)

#define	DMA_CH7_DBG_TCR_OFFSET _u(0x000009c4)

#define	DMA_CH7_DBG_TCR_RESET _u(0x00000000)

#define	DMA_CH7_READ_ADDR_ACCESS "RW"

#define	DMA_CH7_READ_ADDR_BITS _u(0xffffffff)

#define	DMA_CH7_READ_ADDR_LSB _u(0)

#define	DMA_CH7_READ_ADDR_MSB _u(31)

#define	DMA_CH7_READ_ADDR_OFFSET _u(0x000001c0)

#define	DMA_CH7_READ_ADDR_RESET _u(0x00000000)

#define	DMA_CH7_TRANS_COUNT_BITS _u(0xffffffff)

#define	DMA_CH7_TRANS_COUNT_COUNT_ACCESS "RW"

#define	DMA_CH7_TRANS_COUNT_COUNT_BITS _u(0x0fffffff)

#define	DMA_CH7_TRANS_COUNT_COUNT_LSB _u(0)

#define	DMA_CH7_TRANS_COUNT_COUNT_MSB _u(27)

#define	DMA_CH7_TRANS_COUNT_COUNT_RESET _u(0x0000000)

#define	DMA_CH7_TRANS_COUNT_MODE_ACCESS "RW"

#define	DMA_CH7_TRANS_COUNT_MODE_BITS _u(0xf0000000)

#define	DMA_CH7_TRANS_COUNT_MODE_LSB _u(28)

#define	DMA_CH7_TRANS_COUNT_MODE_MSB _u(31)

#define	DMA_CH7_TRANS_COUNT_MODE_RESET _u(0x0)

#define	DMA_CH7_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf)

#define	DMA_CH7_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0)

#define	DMA_CH7_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1)

#define	DMA_CH7_TRANS_COUNT_OFFSET _u(0x000001c8)

#define	DMA_CH7_TRANS_COUNT_RESET _u(0x00000000)

#define	DMA_CH7_WRITE_ADDR_ACCESS "RW"

#define	DMA_CH7_WRITE_ADDR_BITS _u(0xffffffff)

#define	DMA_CH7_WRITE_ADDR_LSB _u(0)

#define	DMA_CH7_WRITE_ADDR_MSB _u(31)

#define	DMA_CH7_WRITE_ADDR_OFFSET _u(0x000001c4)

#define	DMA_CH7_WRITE_ADDR_RESET _u(0x00000000)

#define	DMA_CH8_AL1_CTRL_ACCESS "RW"

#define	DMA_CH8_AL1_CTRL_BITS _u(0xffffffff)

#define	DMA_CH8_AL1_CTRL_LSB _u(0)

#define	DMA_CH8_AL1_CTRL_MSB _u(31)

#define	DMA_CH8_AL1_CTRL_OFFSET _u(0x00000210)

#define	DMA_CH8_AL1_CTRL_RESET "-"

#define	DMA_CH8_AL1_READ_ADDR_ACCESS "RW"

#define	DMA_CH8_AL1_READ_ADDR_BITS _u(0xffffffff)

#define	DMA_CH8_AL1_READ_ADDR_LSB _u(0)

#define	DMA_CH8_AL1_READ_ADDR_MSB _u(31)

#define	DMA_CH8_AL1_READ_ADDR_OFFSET _u(0x00000214)

#define	DMA_CH8_AL1_READ_ADDR_RESET "-"

#define	DMA_CH8_AL1_TRANS_COUNT_TRIG_ACCESS "RW"

#define	DMA_CH8_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff)

#define	DMA_CH8_AL1_TRANS_COUNT_TRIG_LSB _u(0)

#define	DMA_CH8_AL1_TRANS_COUNT_TRIG_MSB _u(31)

#define	DMA_CH8_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000021c)

#define	DMA_CH8_AL1_TRANS_COUNT_TRIG_RESET "-"

#define	DMA_CH8_AL1_WRITE_ADDR_ACCESS "RW"

#define	DMA_CH8_AL1_WRITE_ADDR_BITS _u(0xffffffff)

#define	DMA_CH8_AL1_WRITE_ADDR_LSB _u(0)

#define	DMA_CH8_AL1_WRITE_ADDR_MSB _u(31)

#define	DMA_CH8_AL1_WRITE_ADDR_OFFSET _u(0x00000218)

#define	DMA_CH8_AL1_WRITE_ADDR_RESET "-"

#define	DMA_CH8_AL2_CTRL_ACCESS "RW"

#define	DMA_CH8_AL2_CTRL_BITS _u(0xffffffff)

#define	DMA_CH8_AL2_CTRL_LSB _u(0)

#define	DMA_CH8_AL2_CTRL_MSB _u(31)

#define	DMA_CH8_AL2_CTRL_OFFSET _u(0x00000220)

#define	DMA_CH8_AL2_CTRL_RESET "-"

#define	DMA_CH8_AL2_READ_ADDR_ACCESS "RW"

#define	DMA_CH8_AL2_READ_ADDR_BITS _u(0xffffffff)

#define	DMA_CH8_AL2_READ_ADDR_LSB _u(0)

#define	DMA_CH8_AL2_READ_ADDR_MSB _u(31)

#define	DMA_CH8_AL2_READ_ADDR_OFFSET _u(0x00000228)

#define	DMA_CH8_AL2_READ_ADDR_RESET "-"

#define	DMA_CH8_AL2_TRANS_COUNT_ACCESS "RW"

#define	DMA_CH8_AL2_TRANS_COUNT_BITS _u(0xffffffff)

#define	DMA_CH8_AL2_TRANS_COUNT_LSB _u(0)

#define	DMA_CH8_AL2_TRANS_COUNT_MSB _u(31)

#define	DMA_CH8_AL2_TRANS_COUNT_OFFSET _u(0x00000224)

#define	DMA_CH8_AL2_TRANS_COUNT_RESET "-"

#define	DMA_CH8_AL2_WRITE_ADDR_TRIG_ACCESS "RW"

#define	DMA_CH8_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff)

#define	DMA_CH8_AL2_WRITE_ADDR_TRIG_LSB _u(0)

#define	DMA_CH8_AL2_WRITE_ADDR_TRIG_MSB _u(31)

#define	DMA_CH8_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x0000022c)

#define	DMA_CH8_AL2_WRITE_ADDR_TRIG_RESET "-"

#define	DMA_CH8_AL3_CTRL_ACCESS "RW"

#define	DMA_CH8_AL3_CTRL_BITS _u(0xffffffff)

#define	DMA_CH8_AL3_CTRL_LSB _u(0)

#define	DMA_CH8_AL3_CTRL_MSB _u(31)

#define	DMA_CH8_AL3_CTRL_OFFSET _u(0x00000230)

#define	DMA_CH8_AL3_CTRL_RESET "-"

#define	DMA_CH8_AL3_READ_ADDR_TRIG_ACCESS "RW"

#define	DMA_CH8_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff)

#define	DMA_CH8_AL3_READ_ADDR_TRIG_LSB _u(0)

#define	DMA_CH8_AL3_READ_ADDR_TRIG_MSB _u(31)

#define	DMA_CH8_AL3_READ_ADDR_TRIG_OFFSET _u(0x0000023c)

#define	DMA_CH8_AL3_READ_ADDR_TRIG_RESET "-"

#define	DMA_CH8_AL3_TRANS_COUNT_ACCESS "RW"

#define	DMA_CH8_AL3_TRANS_COUNT_BITS _u(0xffffffff)

#define	DMA_CH8_AL3_TRANS_COUNT_LSB _u(0)

#define	DMA_CH8_AL3_TRANS_COUNT_MSB _u(31)

#define	DMA_CH8_AL3_TRANS_COUNT_OFFSET _u(0x00000238)

#define	DMA_CH8_AL3_TRANS_COUNT_RESET "-"

#define	DMA_CH8_AL3_WRITE_ADDR_ACCESS "RW"

#define	DMA_CH8_AL3_WRITE_ADDR_BITS _u(0xffffffff)

#define	DMA_CH8_AL3_WRITE_ADDR_LSB _u(0)

#define	DMA_CH8_AL3_WRITE_ADDR_MSB _u(31)

#define	DMA_CH8_AL3_WRITE_ADDR_OFFSET _u(0x00000234)

#define	DMA_CH8_AL3_WRITE_ADDR_RESET "-"

#define	DMA_CH8_CTRL_TRIG_AHB_ERROR_ACCESS "RO"

#define	DMA_CH8_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000)

#define	DMA_CH8_CTRL_TRIG_AHB_ERROR_LSB _u(31)

#define	DMA_CH8_CTRL_TRIG_AHB_ERROR_MSB _u(31)

#define	DMA_CH8_CTRL_TRIG_AHB_ERROR_RESET _u(0x0)

#define	DMA_CH8_CTRL_TRIG_BITS _u(0xe7ffffff)

#define	DMA_CH8_CTRL_TRIG_BSWAP_ACCESS "RW"

#define	DMA_CH8_CTRL_TRIG_BSWAP_BITS _u(0x01000000)

#define	DMA_CH8_CTRL_TRIG_BSWAP_LSB _u(24)

#define	DMA_CH8_CTRL_TRIG_BSWAP_MSB _u(24)

#define	DMA_CH8_CTRL_TRIG_BSWAP_RESET _u(0x0)

#define	DMA_CH8_CTRL_TRIG_BUSY_ACCESS "RO"

#define	DMA_CH8_CTRL_TRIG_BUSY_BITS _u(0x04000000)

#define	DMA_CH8_CTRL_TRIG_BUSY_LSB _u(26)

#define	DMA_CH8_CTRL_TRIG_BUSY_MSB _u(26)

#define	DMA_CH8_CTRL_TRIG_BUSY_RESET _u(0x0)

#define	DMA_CH8_CTRL_TRIG_CHAIN_TO_ACCESS "RW"

#define	DMA_CH8_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000)

#define	DMA_CH8_CTRL_TRIG_CHAIN_TO_LSB _u(13)

#define	DMA_CH8_CTRL_TRIG_CHAIN_TO_MSB _u(16)

#define	DMA_CH8_CTRL_TRIG_CHAIN_TO_RESET _u(0x0)

#define	DMA_CH8_CTRL_TRIG_DATA_SIZE_ACCESS "RW"

#define	DMA_CH8_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c)

#define	DMA_CH8_CTRL_TRIG_DATA_SIZE_LSB _u(2)

#define	DMA_CH8_CTRL_TRIG_DATA_SIZE_MSB _u(3)

#define	DMA_CH8_CTRL_TRIG_DATA_SIZE_RESET _u(0x0)

#define	DMA_CH8_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0)

#define	DMA_CH8_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1)

#define	DMA_CH8_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2)

#define	DMA_CH8_CTRL_TRIG_EN_ACCESS "RW"

#define	DMA_CH8_CTRL_TRIG_EN_BITS _u(0x00000001)

#define	DMA_CH8_CTRL_TRIG_EN_LSB _u(0)

#define	DMA_CH8_CTRL_TRIG_EN_MSB _u(0)

#define	DMA_CH8_CTRL_TRIG_EN_RESET _u(0x0)

#define	DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW"

#define	DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002)

#define	DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1)

#define	DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1)

#define	DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0)

#define	DMA_CH8_CTRL_TRIG_INCR_READ_ACCESS "RW"

#define	DMA_CH8_CTRL_TRIG_INCR_READ_BITS _u(0x00000010)

#define	DMA_CH8_CTRL_TRIG_INCR_READ_LSB _u(4)

#define	DMA_CH8_CTRL_TRIG_INCR_READ_MSB _u(4)

#define	DMA_CH8_CTRL_TRIG_INCR_READ_RESET _u(0x0)

#define	DMA_CH8_CTRL_TRIG_INCR_READ_REV_ACCESS "RW"

#define	DMA_CH8_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020)

#define	DMA_CH8_CTRL_TRIG_INCR_READ_REV_LSB _u(5)

#define	DMA_CH8_CTRL_TRIG_INCR_READ_REV_MSB _u(5)

#define	DMA_CH8_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0)

#define	DMA_CH8_CTRL_TRIG_INCR_WRITE_ACCESS "RW"

#define	DMA_CH8_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040)

#define	DMA_CH8_CTRL_TRIG_INCR_WRITE_LSB _u(6)

#define	DMA_CH8_CTRL_TRIG_INCR_WRITE_MSB _u(6)

#define	DMA_CH8_CTRL_TRIG_INCR_WRITE_RESET _u(0x0)

#define	DMA_CH8_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW"

#define	DMA_CH8_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080)

#define	DMA_CH8_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7)

#define	DMA_CH8_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7)

#define	DMA_CH8_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0)

#define	DMA_CH8_CTRL_TRIG_IRQ_QUIET_ACCESS "RW"

#define	DMA_CH8_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000)

#define	DMA_CH8_CTRL_TRIG_IRQ_QUIET_LSB _u(23)

#define	DMA_CH8_CTRL_TRIG_IRQ_QUIET_MSB _u(23)

#define	DMA_CH8_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0)

#define	DMA_CH8_CTRL_TRIG_OFFSET _u(0x0000020c)

#define	DMA_CH8_CTRL_TRIG_READ_ERROR_ACCESS "WC"

#define	DMA_CH8_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000)

#define	DMA_CH8_CTRL_TRIG_READ_ERROR_LSB _u(30)

#define	DMA_CH8_CTRL_TRIG_READ_ERROR_MSB _u(30)

#define	DMA_CH8_CTRL_TRIG_READ_ERROR_RESET _u(0x0)

#define	DMA_CH8_CTRL_TRIG_RESET _u(0x00000000)

#define	DMA_CH8_CTRL_TRIG_RING_SEL_ACCESS "RW"

#define	DMA_CH8_CTRL_TRIG_RING_SEL_BITS _u(0x00001000)

#define	DMA_CH8_CTRL_TRIG_RING_SEL_LSB _u(12)

#define	DMA_CH8_CTRL_TRIG_RING_SEL_MSB _u(12)

#define	DMA_CH8_CTRL_TRIG_RING_SEL_RESET _u(0x0)

#define	DMA_CH8_CTRL_TRIG_RING_SIZE_ACCESS "RW"

#define	DMA_CH8_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00)

#define	DMA_CH8_CTRL_TRIG_RING_SIZE_LSB _u(8)

#define	DMA_CH8_CTRL_TRIG_RING_SIZE_MSB _u(11)

#define	DMA_CH8_CTRL_TRIG_RING_SIZE_RESET _u(0x0)

#define	DMA_CH8_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0)

#define	DMA_CH8_CTRL_TRIG_SNIFF_EN_ACCESS "RW"

#define	DMA_CH8_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000)

#define	DMA_CH8_CTRL_TRIG_SNIFF_EN_LSB _u(25)

#define	DMA_CH8_CTRL_TRIG_SNIFF_EN_MSB _u(25)

#define	DMA_CH8_CTRL_TRIG_SNIFF_EN_RESET _u(0x0)

#define	DMA_CH8_CTRL_TRIG_TREQ_SEL_ACCESS "RW"

#define	DMA_CH8_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000)

#define	DMA_CH8_CTRL_TRIG_TREQ_SEL_LSB _u(17)

#define	DMA_CH8_CTRL_TRIG_TREQ_SEL_MSB _u(22)

#define	DMA_CH8_CTRL_TRIG_TREQ_SEL_RESET _u(0x00)

#define	DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f)

#define	DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b)

#define	DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c)

#define	DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d)

#define	DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e)

#define	DMA_CH8_CTRL_TRIG_WRITE_ERROR_ACCESS "WC"

#define	DMA_CH8_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000)

#define	DMA_CH8_CTRL_TRIG_WRITE_ERROR_LSB _u(29)

#define	DMA_CH8_CTRL_TRIG_WRITE_ERROR_MSB _u(29)

#define	DMA_CH8_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0)

#define	DMA_CH8_DBG_CTDREQ_ACCESS "WC"

#define	DMA_CH8_DBG_CTDREQ_BITS _u(0x0000003f)

#define	DMA_CH8_DBG_CTDREQ_LSB _u(0)

#define	DMA_CH8_DBG_CTDREQ_MSB _u(5)

#define	DMA_CH8_DBG_CTDREQ_OFFSET _u(0x00000a00)

#define	DMA_CH8_DBG_CTDREQ_RESET _u(0x00000000)

#define	DMA_CH8_DBG_TCR_ACCESS "RO"

#define	DMA_CH8_DBG_TCR_BITS _u(0xffffffff)

#define	DMA_CH8_DBG_TCR_LSB _u(0)

#define	DMA_CH8_DBG_TCR_MSB _u(31)

#define	DMA_CH8_DBG_TCR_OFFSET _u(0x00000a04)

#define	DMA_CH8_DBG_TCR_RESET _u(0x00000000)

#define	DMA_CH8_READ_ADDR_ACCESS "RW"

#define	DMA_CH8_READ_ADDR_BITS _u(0xffffffff)

#define	DMA_CH8_READ_ADDR_LSB _u(0)

#define	DMA_CH8_READ_ADDR_MSB _u(31)

#define	DMA_CH8_READ_ADDR_OFFSET _u(0x00000200)

#define	DMA_CH8_READ_ADDR_RESET _u(0x00000000)

#define	DMA_CH8_TRANS_COUNT_BITS _u(0xffffffff)

#define	DMA_CH8_TRANS_COUNT_COUNT_ACCESS "RW"

#define	DMA_CH8_TRANS_COUNT_COUNT_BITS _u(0x0fffffff)

#define	DMA_CH8_TRANS_COUNT_COUNT_LSB _u(0)

#define	DMA_CH8_TRANS_COUNT_COUNT_MSB _u(27)

#define	DMA_CH8_TRANS_COUNT_COUNT_RESET _u(0x0000000)

#define	DMA_CH8_TRANS_COUNT_MODE_ACCESS "RW"

#define	DMA_CH8_TRANS_COUNT_MODE_BITS _u(0xf0000000)

#define	DMA_CH8_TRANS_COUNT_MODE_LSB _u(28)

#define	DMA_CH8_TRANS_COUNT_MODE_MSB _u(31)

#define	DMA_CH8_TRANS_COUNT_MODE_RESET _u(0x0)

#define	DMA_CH8_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf)

#define	DMA_CH8_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0)

#define	DMA_CH8_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1)

#define	DMA_CH8_TRANS_COUNT_OFFSET _u(0x00000208)

#define	DMA_CH8_TRANS_COUNT_RESET _u(0x00000000)

#define	DMA_CH8_WRITE_ADDR_ACCESS "RW"

#define	DMA_CH8_WRITE_ADDR_BITS _u(0xffffffff)

#define	DMA_CH8_WRITE_ADDR_LSB _u(0)

#define	DMA_CH8_WRITE_ADDR_MSB _u(31)

#define	DMA_CH8_WRITE_ADDR_OFFSET _u(0x00000204)

#define	DMA_CH8_WRITE_ADDR_RESET _u(0x00000000)

#define	DMA_CH9_AL1_CTRL_ACCESS "RW"

#define	DMA_CH9_AL1_CTRL_BITS _u(0xffffffff)

#define	DMA_CH9_AL1_CTRL_LSB _u(0)

#define	DMA_CH9_AL1_CTRL_MSB _u(31)

#define	DMA_CH9_AL1_CTRL_OFFSET _u(0x00000250)

#define	DMA_CH9_AL1_CTRL_RESET "-"

#define	DMA_CH9_AL1_READ_ADDR_ACCESS "RW"

#define	DMA_CH9_AL1_READ_ADDR_BITS _u(0xffffffff)

#define	DMA_CH9_AL1_READ_ADDR_LSB _u(0)

#define	DMA_CH9_AL1_READ_ADDR_MSB _u(31)

#define	DMA_CH9_AL1_READ_ADDR_OFFSET _u(0x00000254)

#define	DMA_CH9_AL1_READ_ADDR_RESET "-"

#define	DMA_CH9_AL1_TRANS_COUNT_TRIG_ACCESS "RW"

#define	DMA_CH9_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff)

#define	DMA_CH9_AL1_TRANS_COUNT_TRIG_LSB _u(0)

#define	DMA_CH9_AL1_TRANS_COUNT_TRIG_MSB _u(31)

#define	DMA_CH9_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000025c)

#define	DMA_CH9_AL1_TRANS_COUNT_TRIG_RESET "-"

#define	DMA_CH9_AL1_WRITE_ADDR_ACCESS "RW"

#define	DMA_CH9_AL1_WRITE_ADDR_BITS _u(0xffffffff)

#define	DMA_CH9_AL1_WRITE_ADDR_LSB _u(0)

#define	DMA_CH9_AL1_WRITE_ADDR_MSB _u(31)

#define	DMA_CH9_AL1_WRITE_ADDR_OFFSET _u(0x00000258)

#define	DMA_CH9_AL1_WRITE_ADDR_RESET "-"

#define	DMA_CH9_AL2_CTRL_ACCESS "RW"

#define	DMA_CH9_AL2_CTRL_BITS _u(0xffffffff)

#define	DMA_CH9_AL2_CTRL_LSB _u(0)

#define	DMA_CH9_AL2_CTRL_MSB _u(31)

#define	DMA_CH9_AL2_CTRL_OFFSET _u(0x00000260)

#define	DMA_CH9_AL2_CTRL_RESET "-"

#define	DMA_CH9_AL2_READ_ADDR_ACCESS "RW"

#define	DMA_CH9_AL2_READ_ADDR_BITS _u(0xffffffff)

#define	DMA_CH9_AL2_READ_ADDR_LSB _u(0)

#define	DMA_CH9_AL2_READ_ADDR_MSB _u(31)

#define	DMA_CH9_AL2_READ_ADDR_OFFSET _u(0x00000268)

#define	DMA_CH9_AL2_READ_ADDR_RESET "-"

#define	DMA_CH9_AL2_TRANS_COUNT_ACCESS "RW"

#define	DMA_CH9_AL2_TRANS_COUNT_BITS _u(0xffffffff)

#define	DMA_CH9_AL2_TRANS_COUNT_LSB _u(0)

#define	DMA_CH9_AL2_TRANS_COUNT_MSB _u(31)

#define	DMA_CH9_AL2_TRANS_COUNT_OFFSET _u(0x00000264)

#define	DMA_CH9_AL2_TRANS_COUNT_RESET "-"

#define	DMA_CH9_AL2_WRITE_ADDR_TRIG_ACCESS "RW"

#define	DMA_CH9_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff)

#define	DMA_CH9_AL2_WRITE_ADDR_TRIG_LSB _u(0)

#define	DMA_CH9_AL2_WRITE_ADDR_TRIG_MSB _u(31)

#define	DMA_CH9_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x0000026c)

#define	DMA_CH9_AL2_WRITE_ADDR_TRIG_RESET "-"

#define	DMA_CH9_AL3_CTRL_ACCESS "RW"

#define	DMA_CH9_AL3_CTRL_BITS _u(0xffffffff)

#define	DMA_CH9_AL3_CTRL_LSB _u(0)

#define	DMA_CH9_AL3_CTRL_MSB _u(31)

#define	DMA_CH9_AL3_CTRL_OFFSET _u(0x00000270)

#define	DMA_CH9_AL3_CTRL_RESET "-"

#define	DMA_CH9_AL3_READ_ADDR_TRIG_ACCESS "RW"

#define	DMA_CH9_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff)

#define	DMA_CH9_AL3_READ_ADDR_TRIG_LSB _u(0)

#define	DMA_CH9_AL3_READ_ADDR_TRIG_MSB _u(31)

#define	DMA_CH9_AL3_READ_ADDR_TRIG_OFFSET _u(0x0000027c)

#define	DMA_CH9_AL3_READ_ADDR_TRIG_RESET "-"

#define	DMA_CH9_AL3_TRANS_COUNT_ACCESS "RW"

#define	DMA_CH9_AL3_TRANS_COUNT_BITS _u(0xffffffff)

#define	DMA_CH9_AL3_TRANS_COUNT_LSB _u(0)

#define	DMA_CH9_AL3_TRANS_COUNT_MSB _u(31)

#define	DMA_CH9_AL3_TRANS_COUNT_OFFSET _u(0x00000278)

#define	DMA_CH9_AL3_TRANS_COUNT_RESET "-"

#define	DMA_CH9_AL3_WRITE_ADDR_ACCESS "RW"

#define	DMA_CH9_AL3_WRITE_ADDR_BITS _u(0xffffffff)

#define	DMA_CH9_AL3_WRITE_ADDR_LSB _u(0)

#define	DMA_CH9_AL3_WRITE_ADDR_MSB _u(31)

#define	DMA_CH9_AL3_WRITE_ADDR_OFFSET _u(0x00000274)

#define	DMA_CH9_AL3_WRITE_ADDR_RESET "-"

#define	DMA_CH9_CTRL_TRIG_AHB_ERROR_ACCESS "RO"

#define	DMA_CH9_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000)

#define	DMA_CH9_CTRL_TRIG_AHB_ERROR_LSB _u(31)

#define	DMA_CH9_CTRL_TRIG_AHB_ERROR_MSB _u(31)

#define	DMA_CH9_CTRL_TRIG_AHB_ERROR_RESET _u(0x0)

#define	DMA_CH9_CTRL_TRIG_BITS _u(0xe7ffffff)

#define	DMA_CH9_CTRL_TRIG_BSWAP_ACCESS "RW"

#define	DMA_CH9_CTRL_TRIG_BSWAP_BITS _u(0x01000000)

#define	DMA_CH9_CTRL_TRIG_BSWAP_LSB _u(24)

#define	DMA_CH9_CTRL_TRIG_BSWAP_MSB _u(24)

#define	DMA_CH9_CTRL_TRIG_BSWAP_RESET _u(0x0)

#define	DMA_CH9_CTRL_TRIG_BUSY_ACCESS "RO"

#define	DMA_CH9_CTRL_TRIG_BUSY_BITS _u(0x04000000)

#define	DMA_CH9_CTRL_TRIG_BUSY_LSB _u(26)

#define	DMA_CH9_CTRL_TRIG_BUSY_MSB _u(26)

#define	DMA_CH9_CTRL_TRIG_BUSY_RESET _u(0x0)

#define	DMA_CH9_CTRL_TRIG_CHAIN_TO_ACCESS "RW"

#define	DMA_CH9_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000)

#define	DMA_CH9_CTRL_TRIG_CHAIN_TO_LSB _u(13)

#define	DMA_CH9_CTRL_TRIG_CHAIN_TO_MSB _u(16)

#define	DMA_CH9_CTRL_TRIG_CHAIN_TO_RESET _u(0x0)

#define	DMA_CH9_CTRL_TRIG_DATA_SIZE_ACCESS "RW"

#define	DMA_CH9_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c)

#define	DMA_CH9_CTRL_TRIG_DATA_SIZE_LSB _u(2)

#define	DMA_CH9_CTRL_TRIG_DATA_SIZE_MSB _u(3)

#define	DMA_CH9_CTRL_TRIG_DATA_SIZE_RESET _u(0x0)

#define	DMA_CH9_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0)

#define	DMA_CH9_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1)

#define	DMA_CH9_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2)

#define	DMA_CH9_CTRL_TRIG_EN_ACCESS "RW"

#define	DMA_CH9_CTRL_TRIG_EN_BITS _u(0x00000001)

#define	DMA_CH9_CTRL_TRIG_EN_LSB _u(0)

#define	DMA_CH9_CTRL_TRIG_EN_MSB _u(0)

#define	DMA_CH9_CTRL_TRIG_EN_RESET _u(0x0)

#define	DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW"

#define	DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002)

#define	DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1)

#define	DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1)

#define	DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0)

#define	DMA_CH9_CTRL_TRIG_INCR_READ_ACCESS "RW"

#define	DMA_CH9_CTRL_TRIG_INCR_READ_BITS _u(0x00000010)

#define	DMA_CH9_CTRL_TRIG_INCR_READ_LSB _u(4)

#define	DMA_CH9_CTRL_TRIG_INCR_READ_MSB _u(4)

#define	DMA_CH9_CTRL_TRIG_INCR_READ_RESET _u(0x0)

#define	DMA_CH9_CTRL_TRIG_INCR_READ_REV_ACCESS "RW"

#define	DMA_CH9_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020)

#define	DMA_CH9_CTRL_TRIG_INCR_READ_REV_LSB _u(5)

#define	DMA_CH9_CTRL_TRIG_INCR_READ_REV_MSB _u(5)

#define	DMA_CH9_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0)

#define	DMA_CH9_CTRL_TRIG_INCR_WRITE_ACCESS "RW"

#define	DMA_CH9_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040)

#define	DMA_CH9_CTRL_TRIG_INCR_WRITE_LSB _u(6)

#define	DMA_CH9_CTRL_TRIG_INCR_WRITE_MSB _u(6)

#define	DMA_CH9_CTRL_TRIG_INCR_WRITE_RESET _u(0x0)

#define	DMA_CH9_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW"

#define	DMA_CH9_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080)

#define	DMA_CH9_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7)

#define	DMA_CH9_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7)

#define	DMA_CH9_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0)

#define	DMA_CH9_CTRL_TRIG_IRQ_QUIET_ACCESS "RW"

#define	DMA_CH9_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000)

#define	DMA_CH9_CTRL_TRIG_IRQ_QUIET_LSB _u(23)

#define	DMA_CH9_CTRL_TRIG_IRQ_QUIET_MSB _u(23)

#define	DMA_CH9_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0)

#define	DMA_CH9_CTRL_TRIG_OFFSET _u(0x0000024c)

#define	DMA_CH9_CTRL_TRIG_READ_ERROR_ACCESS "WC"

#define	DMA_CH9_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000)

#define	DMA_CH9_CTRL_TRIG_READ_ERROR_LSB _u(30)

#define	DMA_CH9_CTRL_TRIG_READ_ERROR_MSB _u(30)

#define	DMA_CH9_CTRL_TRIG_READ_ERROR_RESET _u(0x0)

#define	DMA_CH9_CTRL_TRIG_RESET _u(0x00000000)

#define	DMA_CH9_CTRL_TRIG_RING_SEL_ACCESS "RW"

#define	DMA_CH9_CTRL_TRIG_RING_SEL_BITS _u(0x00001000)

#define	DMA_CH9_CTRL_TRIG_RING_SEL_LSB _u(12)

#define	DMA_CH9_CTRL_TRIG_RING_SEL_MSB _u(12)

#define	DMA_CH9_CTRL_TRIG_RING_SEL_RESET _u(0x0)

#define	DMA_CH9_CTRL_TRIG_RING_SIZE_ACCESS "RW"

#define	DMA_CH9_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00)

#define	DMA_CH9_CTRL_TRIG_RING_SIZE_LSB _u(8)

#define	DMA_CH9_CTRL_TRIG_RING_SIZE_MSB _u(11)

#define	DMA_CH9_CTRL_TRIG_RING_SIZE_RESET _u(0x0)

#define	DMA_CH9_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0)

#define	DMA_CH9_CTRL_TRIG_SNIFF_EN_ACCESS "RW"

#define	DMA_CH9_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000)

#define	DMA_CH9_CTRL_TRIG_SNIFF_EN_LSB _u(25)

#define	DMA_CH9_CTRL_TRIG_SNIFF_EN_MSB _u(25)

#define	DMA_CH9_CTRL_TRIG_SNIFF_EN_RESET _u(0x0)

#define	DMA_CH9_CTRL_TRIG_TREQ_SEL_ACCESS "RW"

#define	DMA_CH9_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000)

#define	DMA_CH9_CTRL_TRIG_TREQ_SEL_LSB _u(17)

#define	DMA_CH9_CTRL_TRIG_TREQ_SEL_MSB _u(22)

#define	DMA_CH9_CTRL_TRIG_TREQ_SEL_RESET _u(0x00)

#define	DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f)

#define	DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b)

#define	DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c)

#define	DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d)

#define	DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e)

#define	DMA_CH9_CTRL_TRIG_WRITE_ERROR_ACCESS "WC"

#define	DMA_CH9_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000)

#define	DMA_CH9_CTRL_TRIG_WRITE_ERROR_LSB _u(29)

#define	DMA_CH9_CTRL_TRIG_WRITE_ERROR_MSB _u(29)

#define	DMA_CH9_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0)

#define	DMA_CH9_DBG_CTDREQ_ACCESS "WC"

#define	DMA_CH9_DBG_CTDREQ_BITS _u(0x0000003f)

#define	DMA_CH9_DBG_CTDREQ_LSB _u(0)

#define	DMA_CH9_DBG_CTDREQ_MSB _u(5)

#define	DMA_CH9_DBG_CTDREQ_OFFSET _u(0x00000a40)

#define	DMA_CH9_DBG_CTDREQ_RESET _u(0x00000000)

#define	DMA_CH9_DBG_TCR_ACCESS "RO"

#define	DMA_CH9_DBG_TCR_BITS _u(0xffffffff)

#define	DMA_CH9_DBG_TCR_LSB _u(0)

#define	DMA_CH9_DBG_TCR_MSB _u(31)

#define	DMA_CH9_DBG_TCR_OFFSET _u(0x00000a44)

#define	DMA_CH9_DBG_TCR_RESET _u(0x00000000)

#define	DMA_CH9_READ_ADDR_ACCESS "RW"

#define	DMA_CH9_READ_ADDR_BITS _u(0xffffffff)

#define	DMA_CH9_READ_ADDR_LSB _u(0)

#define	DMA_CH9_READ_ADDR_MSB _u(31)

#define	DMA_CH9_READ_ADDR_OFFSET _u(0x00000240)

#define	DMA_CH9_READ_ADDR_RESET _u(0x00000000)

#define	DMA_CH9_TRANS_COUNT_BITS _u(0xffffffff)

#define	DMA_CH9_TRANS_COUNT_COUNT_ACCESS "RW"

#define	DMA_CH9_TRANS_COUNT_COUNT_BITS _u(0x0fffffff)

#define	DMA_CH9_TRANS_COUNT_COUNT_LSB _u(0)

#define	DMA_CH9_TRANS_COUNT_COUNT_MSB _u(27)

#define	DMA_CH9_TRANS_COUNT_COUNT_RESET _u(0x0000000)

#define	DMA_CH9_TRANS_COUNT_MODE_ACCESS "RW"

#define	DMA_CH9_TRANS_COUNT_MODE_BITS _u(0xf0000000)

#define	DMA_CH9_TRANS_COUNT_MODE_LSB _u(28)

#define	DMA_CH9_TRANS_COUNT_MODE_MSB _u(31)

#define	DMA_CH9_TRANS_COUNT_MODE_RESET _u(0x0)

#define	DMA_CH9_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf)

#define	DMA_CH9_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0)

#define	DMA_CH9_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1)

#define	DMA_CH9_TRANS_COUNT_OFFSET _u(0x00000248)

#define	DMA_CH9_TRANS_COUNT_RESET _u(0x00000000)

#define	DMA_CH9_WRITE_ADDR_ACCESS "RW"

#define	DMA_CH9_WRITE_ADDR_BITS _u(0xffffffff)

#define	DMA_CH9_WRITE_ADDR_LSB _u(0)

#define	DMA_CH9_WRITE_ADDR_MSB _u(31)

#define	DMA_CH9_WRITE_ADDR_OFFSET _u(0x00000244)

#define	DMA_CH9_WRITE_ADDR_RESET _u(0x00000000)

#define	DMA_CHAN_ABORT_ACCESS "SC"

#define	DMA_CHAN_ABORT_BITS _u(0x0000ffff)

#define	DMA_CHAN_ABORT_LSB _u(0)

#define	DMA_CHAN_ABORT_MSB _u(15)

#define	DMA_CHAN_ABORT_OFFSET _u(0x00000464)

#define	DMA_CHAN_ABORT_RESET _u(0x00000000)

#define	DMA_FIFO_LEVELS_BITS _u(0x00ffffff)

#define	DMA_FIFO_LEVELS_OFFSET _u(0x00000460)

#define	DMA_FIFO_LEVELS_RAF_LVL_ACCESS "RO"

#define	DMA_FIFO_LEVELS_RAF_LVL_BITS _u(0x00ff0000)

#define	DMA_FIFO_LEVELS_RAF_LVL_LSB _u(16)

#define	DMA_FIFO_LEVELS_RAF_LVL_MSB _u(23)

#define	DMA_FIFO_LEVELS_RAF_LVL_RESET _u(0x00)

#define	DMA_FIFO_LEVELS_RESET _u(0x00000000)

#define	DMA_FIFO_LEVELS_TDF_LVL_ACCESS "RO"

#define	DMA_FIFO_LEVELS_TDF_LVL_BITS _u(0x000000ff)

#define	DMA_FIFO_LEVELS_TDF_LVL_LSB _u(0)

#define	DMA_FIFO_LEVELS_TDF_LVL_MSB _u(7)

#define	DMA_FIFO_LEVELS_TDF_LVL_RESET _u(0x00)

#define	DMA_FIFO_LEVELS_WAF_LVL_ACCESS "RO"

#define	DMA_FIFO_LEVELS_WAF_LVL_BITS _u(0x0000ff00)

#define	DMA_FIFO_LEVELS_WAF_LVL_LSB _u(8)

#define	DMA_FIFO_LEVELS_WAF_LVL_MSB _u(15)

#define	DMA_FIFO_LEVELS_WAF_LVL_RESET _u(0x00)

#define	DMA_INTE0_ACCESS "RW"

#define	DMA_INTE0_BITS _u(0x0000ffff)

#define	DMA_INTE0_LSB _u(0)

#define	DMA_INTE0_MSB _u(15)

#define	DMA_INTE0_OFFSET _u(0x00000404)

#define	DMA_INTE0_RESET _u(0x00000000)

#define	DMA_INTE1_ACCESS "RW"

#define	DMA_INTE1_BITS _u(0x0000ffff)

#define	DMA_INTE1_LSB _u(0)

#define	DMA_INTE1_MSB _u(15)

#define	DMA_INTE1_OFFSET _u(0x00000414)

#define	DMA_INTE1_RESET _u(0x00000000)

#define	DMA_INTE2_ACCESS "RW"

#define	DMA_INTE2_BITS _u(0x0000ffff)

#define	DMA_INTE2_LSB _u(0)

#define	DMA_INTE2_MSB _u(15)

#define	DMA_INTE2_OFFSET _u(0x00000424)

#define	DMA_INTE2_RESET _u(0x00000000)

#define	DMA_INTE3_ACCESS "RW"

#define	DMA_INTE3_BITS _u(0x0000ffff)

#define	DMA_INTE3_LSB _u(0)

#define	DMA_INTE3_MSB _u(15)

#define	DMA_INTE3_OFFSET _u(0x00000434)

#define	DMA_INTE3_RESET _u(0x00000000)

#define	DMA_INTF0_ACCESS "RW"

#define	DMA_INTF0_BITS _u(0x0000ffff)

#define	DMA_INTF0_LSB _u(0)

#define	DMA_INTF0_MSB _u(15)

#define	DMA_INTF0_OFFSET _u(0x00000408)

#define	DMA_INTF0_RESET _u(0x00000000)

#define	DMA_INTF1_ACCESS "RW"

#define	DMA_INTF1_BITS _u(0x0000ffff)

#define	DMA_INTF1_LSB _u(0)

#define	DMA_INTF1_MSB _u(15)

#define	DMA_INTF1_OFFSET _u(0x00000418)

#define	DMA_INTF1_RESET _u(0x00000000)

#define	DMA_INTF2_ACCESS "RW"

#define	DMA_INTF2_BITS _u(0x0000ffff)

#define	DMA_INTF2_LSB _u(0)

#define	DMA_INTF2_MSB _u(15)

#define	DMA_INTF2_OFFSET _u(0x00000428)

#define	DMA_INTF2_RESET _u(0x00000000)

#define	DMA_INTF3_ACCESS "RW"

#define	DMA_INTF3_BITS _u(0x0000ffff)

#define	DMA_INTF3_LSB _u(0)

#define	DMA_INTF3_MSB _u(15)

#define	DMA_INTF3_OFFSET _u(0x00000438)

#define	DMA_INTF3_RESET _u(0x00000000)

#define	DMA_INTR_ACCESS "WC"

#define	DMA_INTR_BITS _u(0x0000ffff)

#define	DMA_INTR_LSB _u(0)

#define	DMA_INTR_MSB _u(15)

#define	DMA_INTR_OFFSET _u(0x00000400)

#define	DMA_INTR_RESET _u(0x00000000)

#define	DMA_INTS0_ACCESS "WC"

#define	DMA_INTS0_BITS _u(0x0000ffff)

#define	DMA_INTS0_LSB _u(0)

#define	DMA_INTS0_MSB _u(15)

#define	DMA_INTS0_OFFSET _u(0x0000040c)

#define	DMA_INTS0_RESET _u(0x00000000)

#define	DMA_INTS1_ACCESS "WC"

#define	DMA_INTS1_BITS _u(0x0000ffff)

#define	DMA_INTS1_LSB _u(0)

#define	DMA_INTS1_MSB _u(15)

#define	DMA_INTS1_OFFSET _u(0x0000041c)

#define	DMA_INTS1_RESET _u(0x00000000)

#define	DMA_INTS2_ACCESS "WC"

#define	DMA_INTS2_BITS _u(0x0000ffff)

#define	DMA_INTS2_LSB _u(0)

#define	DMA_INTS2_MSB _u(15)

#define	DMA_INTS2_OFFSET _u(0x0000042c)

#define	DMA_INTS2_RESET _u(0x00000000)

#define	DMA_INTS3_ACCESS "WC"

#define	DMA_INTS3_BITS _u(0x0000ffff)

#define	DMA_INTS3_LSB _u(0)

#define	DMA_INTS3_MSB _u(15)

#define	DMA_INTS3_OFFSET _u(0x0000043c)

#define	DMA_INTS3_RESET _u(0x00000000)

#define	DMA_MPU_BAR0_ADDR_ACCESS "RW"

#define	DMA_MPU_BAR0_ADDR_BITS _u(0xffffffe0)

#define	DMA_MPU_BAR0_ADDR_LSB _u(5)

#define	DMA_MPU_BAR0_ADDR_MSB _u(31)

#define	DMA_MPU_BAR0_ADDR_RESET _u(0x0000000)

#define	DMA_MPU_BAR0_BITS _u(0xffffffe0)

#define	DMA_MPU_BAR0_OFFSET _u(0x00000504)

#define	DMA_MPU_BAR0_RESET _u(0x00000000)

#define	DMA_MPU_BAR1_ADDR_ACCESS "RW"

#define	DMA_MPU_BAR1_ADDR_BITS _u(0xffffffe0)

#define	DMA_MPU_BAR1_ADDR_LSB _u(5)

#define	DMA_MPU_BAR1_ADDR_MSB _u(31)

#define	DMA_MPU_BAR1_ADDR_RESET _u(0x0000000)

#define	DMA_MPU_BAR1_BITS _u(0xffffffe0)

#define	DMA_MPU_BAR1_OFFSET _u(0x0000050c)

#define	DMA_MPU_BAR1_RESET _u(0x00000000)

#define	DMA_MPU_BAR2_ADDR_ACCESS "RW"

#define	DMA_MPU_BAR2_ADDR_BITS _u(0xffffffe0)

#define	DMA_MPU_BAR2_ADDR_LSB _u(5)

#define	DMA_MPU_BAR2_ADDR_MSB _u(31)

#define	DMA_MPU_BAR2_ADDR_RESET _u(0x0000000)

#define	DMA_MPU_BAR2_BITS _u(0xffffffe0)

#define	DMA_MPU_BAR2_OFFSET _u(0x00000514)

#define	DMA_MPU_BAR2_RESET _u(0x00000000)

#define	DMA_MPU_BAR3_ADDR_ACCESS "RW"

#define	DMA_MPU_BAR3_ADDR_BITS _u(0xffffffe0)

#define	DMA_MPU_BAR3_ADDR_LSB _u(5)

#define	DMA_MPU_BAR3_ADDR_MSB _u(31)

#define	DMA_MPU_BAR3_ADDR_RESET _u(0x0000000)

#define	DMA_MPU_BAR3_BITS _u(0xffffffe0)

#define	DMA_MPU_BAR3_OFFSET _u(0x0000051c)

#define	DMA_MPU_BAR3_RESET _u(0x00000000)

#define	DMA_MPU_BAR4_ADDR_ACCESS "RW"

#define	DMA_MPU_BAR4_ADDR_BITS _u(0xffffffe0)

#define	DMA_MPU_BAR4_ADDR_LSB _u(5)

#define	DMA_MPU_BAR4_ADDR_MSB _u(31)

#define	DMA_MPU_BAR4_ADDR_RESET _u(0x0000000)

#define	DMA_MPU_BAR4_BITS _u(0xffffffe0)

#define	DMA_MPU_BAR4_OFFSET _u(0x00000524)

#define	DMA_MPU_BAR4_RESET _u(0x00000000)

#define	DMA_MPU_BAR5_ADDR_ACCESS "RW"

#define	DMA_MPU_BAR5_ADDR_BITS _u(0xffffffe0)

#define	DMA_MPU_BAR5_ADDR_LSB _u(5)

#define	DMA_MPU_BAR5_ADDR_MSB _u(31)

#define	DMA_MPU_BAR5_ADDR_RESET _u(0x0000000)

#define	DMA_MPU_BAR5_BITS _u(0xffffffe0)

#define	DMA_MPU_BAR5_OFFSET _u(0x0000052c)

#define	DMA_MPU_BAR5_RESET _u(0x00000000)

#define	DMA_MPU_BAR6_ADDR_ACCESS "RW"

#define	DMA_MPU_BAR6_ADDR_BITS _u(0xffffffe0)

#define	DMA_MPU_BAR6_ADDR_LSB _u(5)

#define	DMA_MPU_BAR6_ADDR_MSB _u(31)

#define	DMA_MPU_BAR6_ADDR_RESET _u(0x0000000)

#define	DMA_MPU_BAR6_BITS _u(0xffffffe0)

#define	DMA_MPU_BAR6_OFFSET _u(0x00000534)

#define	DMA_MPU_BAR6_RESET _u(0x00000000)

#define	DMA_MPU_BAR7_ADDR_ACCESS "RW"

#define	DMA_MPU_BAR7_ADDR_BITS _u(0xffffffe0)

#define	DMA_MPU_BAR7_ADDR_LSB _u(5)

#define	DMA_MPU_BAR7_ADDR_MSB _u(31)

#define	DMA_MPU_BAR7_ADDR_RESET _u(0x0000000)

#define	DMA_MPU_BAR7_BITS _u(0xffffffe0)

#define	DMA_MPU_BAR7_OFFSET _u(0x0000053c)

#define	DMA_MPU_BAR7_RESET _u(0x00000000)

#define	DMA_MPU_CTRL_BITS _u(0x0000000e)

#define	DMA_MPU_CTRL_NS_HIDE_ADDR_ACCESS "RW"

#define	DMA_MPU_CTRL_NS_HIDE_ADDR_BITS _u(0x00000008)

#define	DMA_MPU_CTRL_NS_HIDE_ADDR_LSB _u(3)

#define	DMA_MPU_CTRL_NS_HIDE_ADDR_MSB _u(3)

#define	DMA_MPU_CTRL_NS_HIDE_ADDR_RESET _u(0x0)

#define	DMA_MPU_CTRL_OFFSET _u(0x00000500)

#define	DMA_MPU_CTRL_P_ACCESS "RW"

#define	DMA_MPU_CTRL_P_BITS _u(0x00000002)

#define	DMA_MPU_CTRL_P_LSB _u(1)

#define	DMA_MPU_CTRL_P_MSB _u(1)

#define	DMA_MPU_CTRL_P_RESET _u(0x0)

#define	DMA_MPU_CTRL_RESET _u(0x00000000)

#define	DMA_MPU_CTRL_S_ACCESS "RW"

#define	DMA_MPU_CTRL_S_BITS _u(0x00000004)

#define	DMA_MPU_CTRL_S_LSB _u(2)

#define	DMA_MPU_CTRL_S_MSB _u(2)

#define	DMA_MPU_CTRL_S_RESET _u(0x0)

#define	DMA_MPU_LAR0_ADDR_ACCESS "RW"

#define	DMA_MPU_LAR0_ADDR_BITS _u(0xffffffe0)

#define	DMA_MPU_LAR0_ADDR_LSB _u(5)

#define	DMA_MPU_LAR0_ADDR_MSB _u(31)

#define	DMA_MPU_LAR0_ADDR_RESET _u(0x0000000)

#define	DMA_MPU_LAR0_BITS _u(0xffffffe7)

#define	DMA_MPU_LAR0_EN_ACCESS "RW"

#define	DMA_MPU_LAR0_EN_BITS _u(0x00000001)

#define	DMA_MPU_LAR0_EN_LSB _u(0)

#define	DMA_MPU_LAR0_EN_MSB _u(0)

#define	DMA_MPU_LAR0_EN_RESET _u(0x0)

#define	DMA_MPU_LAR0_OFFSET _u(0x00000508)

#define	DMA_MPU_LAR0_P_ACCESS "RW"

#define	DMA_MPU_LAR0_P_BITS _u(0x00000002)

#define	DMA_MPU_LAR0_P_LSB _u(1)

#define	DMA_MPU_LAR0_P_MSB _u(1)

#define	DMA_MPU_LAR0_P_RESET _u(0x0)

#define	DMA_MPU_LAR0_RESET _u(0x00000000)

#define	DMA_MPU_LAR0_S_ACCESS "RW"

#define	DMA_MPU_LAR0_S_BITS _u(0x00000004)

#define	DMA_MPU_LAR0_S_LSB _u(2)

#define	DMA_MPU_LAR0_S_MSB _u(2)

#define	DMA_MPU_LAR0_S_RESET _u(0x0)

#define	DMA_MPU_LAR1_ADDR_ACCESS "RW"

#define	DMA_MPU_LAR1_ADDR_BITS _u(0xffffffe0)

#define	DMA_MPU_LAR1_ADDR_LSB _u(5)

#define	DMA_MPU_LAR1_ADDR_MSB _u(31)

#define	DMA_MPU_LAR1_ADDR_RESET _u(0x0000000)

#define	DMA_MPU_LAR1_BITS _u(0xffffffe7)

#define	DMA_MPU_LAR1_EN_ACCESS "RW"

#define	DMA_MPU_LAR1_EN_BITS _u(0x00000001)

#define	DMA_MPU_LAR1_EN_LSB _u(0)

#define	DMA_MPU_LAR1_EN_MSB _u(0)

#define	DMA_MPU_LAR1_EN_RESET _u(0x0)

#define	DMA_MPU_LAR1_OFFSET _u(0x00000510)

#define	DMA_MPU_LAR1_P_ACCESS "RW"

#define	DMA_MPU_LAR1_P_BITS _u(0x00000002)

#define	DMA_MPU_LAR1_P_LSB _u(1)

#define	DMA_MPU_LAR1_P_MSB _u(1)

#define	DMA_MPU_LAR1_P_RESET _u(0x0)

#define	DMA_MPU_LAR1_RESET _u(0x00000000)

#define	DMA_MPU_LAR1_S_ACCESS "RW"

#define	DMA_MPU_LAR1_S_BITS _u(0x00000004)

#define	DMA_MPU_LAR1_S_LSB _u(2)

#define	DMA_MPU_LAR1_S_MSB _u(2)

#define	DMA_MPU_LAR1_S_RESET _u(0x0)

#define	DMA_MPU_LAR2_ADDR_ACCESS "RW"

#define	DMA_MPU_LAR2_ADDR_BITS _u(0xffffffe0)

#define	DMA_MPU_LAR2_ADDR_LSB _u(5)

#define	DMA_MPU_LAR2_ADDR_MSB _u(31)

#define	DMA_MPU_LAR2_ADDR_RESET _u(0x0000000)

#define	DMA_MPU_LAR2_BITS _u(0xffffffe7)

#define	DMA_MPU_LAR2_EN_ACCESS "RW"

#define	DMA_MPU_LAR2_EN_BITS _u(0x00000001)

#define	DMA_MPU_LAR2_EN_LSB _u(0)

#define	DMA_MPU_LAR2_EN_MSB _u(0)

#define	DMA_MPU_LAR2_EN_RESET _u(0x0)

#define	DMA_MPU_LAR2_OFFSET _u(0x00000518)

#define	DMA_MPU_LAR2_P_ACCESS "RW"

#define	DMA_MPU_LAR2_P_BITS _u(0x00000002)

#define	DMA_MPU_LAR2_P_LSB _u(1)

#define	DMA_MPU_LAR2_P_MSB _u(1)

#define	DMA_MPU_LAR2_P_RESET _u(0x0)

#define	DMA_MPU_LAR2_RESET _u(0x00000000)

#define	DMA_MPU_LAR2_S_ACCESS "RW"

#define	DMA_MPU_LAR2_S_BITS _u(0x00000004)

#define	DMA_MPU_LAR2_S_LSB _u(2)

#define	DMA_MPU_LAR2_S_MSB _u(2)

#define	DMA_MPU_LAR2_S_RESET _u(0x0)

#define	DMA_MPU_LAR3_ADDR_ACCESS "RW"

#define	DMA_MPU_LAR3_ADDR_BITS _u(0xffffffe0)

#define	DMA_MPU_LAR3_ADDR_LSB _u(5)

#define	DMA_MPU_LAR3_ADDR_MSB _u(31)

#define	DMA_MPU_LAR3_ADDR_RESET _u(0x0000000)

#define	DMA_MPU_LAR3_BITS _u(0xffffffe7)

#define	DMA_MPU_LAR3_EN_ACCESS "RW"

#define	DMA_MPU_LAR3_EN_BITS _u(0x00000001)

#define	DMA_MPU_LAR3_EN_LSB _u(0)

#define	DMA_MPU_LAR3_EN_MSB _u(0)

#define	DMA_MPU_LAR3_EN_RESET _u(0x0)

#define	DMA_MPU_LAR3_OFFSET _u(0x00000520)

#define	DMA_MPU_LAR3_P_ACCESS "RW"

#define	DMA_MPU_LAR3_P_BITS _u(0x00000002)

#define	DMA_MPU_LAR3_P_LSB _u(1)

#define	DMA_MPU_LAR3_P_MSB _u(1)

#define	DMA_MPU_LAR3_P_RESET _u(0x0)

#define	DMA_MPU_LAR3_RESET _u(0x00000000)

#define	DMA_MPU_LAR3_S_ACCESS "RW"

#define	DMA_MPU_LAR3_S_BITS _u(0x00000004)

#define	DMA_MPU_LAR3_S_LSB _u(2)

#define	DMA_MPU_LAR3_S_MSB _u(2)

#define	DMA_MPU_LAR3_S_RESET _u(0x0)

#define	DMA_MPU_LAR4_ADDR_ACCESS "RW"

#define	DMA_MPU_LAR4_ADDR_BITS _u(0xffffffe0)

#define	DMA_MPU_LAR4_ADDR_LSB _u(5)

#define	DMA_MPU_LAR4_ADDR_MSB _u(31)

#define	DMA_MPU_LAR4_ADDR_RESET _u(0x0000000)

#define	DMA_MPU_LAR4_BITS _u(0xffffffe7)

#define	DMA_MPU_LAR4_EN_ACCESS "RW"

#define	DMA_MPU_LAR4_EN_BITS _u(0x00000001)

#define	DMA_MPU_LAR4_EN_LSB _u(0)

#define	DMA_MPU_LAR4_EN_MSB _u(0)

#define	DMA_MPU_LAR4_EN_RESET _u(0x0)

#define	DMA_MPU_LAR4_OFFSET _u(0x00000528)

#define	DMA_MPU_LAR4_P_ACCESS "RW"

#define	DMA_MPU_LAR4_P_BITS _u(0x00000002)

#define	DMA_MPU_LAR4_P_LSB _u(1)

#define	DMA_MPU_LAR4_P_MSB _u(1)

#define	DMA_MPU_LAR4_P_RESET _u(0x0)

#define	DMA_MPU_LAR4_RESET _u(0x00000000)

#define	DMA_MPU_LAR4_S_ACCESS "RW"

#define	DMA_MPU_LAR4_S_BITS _u(0x00000004)

#define	DMA_MPU_LAR4_S_LSB _u(2)

#define	DMA_MPU_LAR4_S_MSB _u(2)

#define	DMA_MPU_LAR4_S_RESET _u(0x0)

#define	DMA_MPU_LAR5_ADDR_ACCESS "RW"

#define	DMA_MPU_LAR5_ADDR_BITS _u(0xffffffe0)

#define	DMA_MPU_LAR5_ADDR_LSB _u(5)

#define	DMA_MPU_LAR5_ADDR_MSB _u(31)

#define	DMA_MPU_LAR5_ADDR_RESET _u(0x0000000)

#define	DMA_MPU_LAR5_BITS _u(0xffffffe7)

#define	DMA_MPU_LAR5_EN_ACCESS "RW"

#define	DMA_MPU_LAR5_EN_BITS _u(0x00000001)

#define	DMA_MPU_LAR5_EN_LSB _u(0)

#define	DMA_MPU_LAR5_EN_MSB _u(0)

#define	DMA_MPU_LAR5_EN_RESET _u(0x0)

#define	DMA_MPU_LAR5_OFFSET _u(0x00000530)

#define	DMA_MPU_LAR5_P_ACCESS "RW"

#define	DMA_MPU_LAR5_P_BITS _u(0x00000002)

#define	DMA_MPU_LAR5_P_LSB _u(1)

#define	DMA_MPU_LAR5_P_MSB _u(1)

#define	DMA_MPU_LAR5_P_RESET _u(0x0)

#define	DMA_MPU_LAR5_RESET _u(0x00000000)

#define	DMA_MPU_LAR5_S_ACCESS "RW"

#define	DMA_MPU_LAR5_S_BITS _u(0x00000004)

#define	DMA_MPU_LAR5_S_LSB _u(2)

#define	DMA_MPU_LAR5_S_MSB _u(2)

#define	DMA_MPU_LAR5_S_RESET _u(0x0)

#define	DMA_MPU_LAR6_ADDR_ACCESS "RW"

#define	DMA_MPU_LAR6_ADDR_BITS _u(0xffffffe0)

#define	DMA_MPU_LAR6_ADDR_LSB _u(5)

#define	DMA_MPU_LAR6_ADDR_MSB _u(31)

#define	DMA_MPU_LAR6_ADDR_RESET _u(0x0000000)

#define	DMA_MPU_LAR6_BITS _u(0xffffffe7)

#define	DMA_MPU_LAR6_EN_ACCESS "RW"

#define	DMA_MPU_LAR6_EN_BITS _u(0x00000001)

#define	DMA_MPU_LAR6_EN_LSB _u(0)

#define	DMA_MPU_LAR6_EN_MSB _u(0)

#define	DMA_MPU_LAR6_EN_RESET _u(0x0)

#define	DMA_MPU_LAR6_OFFSET _u(0x00000538)

#define	DMA_MPU_LAR6_P_ACCESS "RW"

#define	DMA_MPU_LAR6_P_BITS _u(0x00000002)

#define	DMA_MPU_LAR6_P_LSB _u(1)

#define	DMA_MPU_LAR6_P_MSB _u(1)

#define	DMA_MPU_LAR6_P_RESET _u(0x0)

#define	DMA_MPU_LAR6_RESET _u(0x00000000)

#define	DMA_MPU_LAR6_S_ACCESS "RW"

#define	DMA_MPU_LAR6_S_BITS _u(0x00000004)

#define	DMA_MPU_LAR6_S_LSB _u(2)

#define	DMA_MPU_LAR6_S_MSB _u(2)

#define	DMA_MPU_LAR6_S_RESET _u(0x0)

#define	DMA_MPU_LAR7_ADDR_ACCESS "RW"

#define	DMA_MPU_LAR7_ADDR_BITS _u(0xffffffe0)

#define	DMA_MPU_LAR7_ADDR_LSB _u(5)

#define	DMA_MPU_LAR7_ADDR_MSB _u(31)

#define	DMA_MPU_LAR7_ADDR_RESET _u(0x0000000)

#define	DMA_MPU_LAR7_BITS _u(0xffffffe7)

#define	DMA_MPU_LAR7_EN_ACCESS "RW"

#define	DMA_MPU_LAR7_EN_BITS _u(0x00000001)

#define	DMA_MPU_LAR7_EN_LSB _u(0)

#define	DMA_MPU_LAR7_EN_MSB _u(0)

#define	DMA_MPU_LAR7_EN_RESET _u(0x0)

#define	DMA_MPU_LAR7_OFFSET _u(0x00000540)

#define	DMA_MPU_LAR7_P_ACCESS "RW"

#define	DMA_MPU_LAR7_P_BITS _u(0x00000002)

#define	DMA_MPU_LAR7_P_LSB _u(1)

#define	DMA_MPU_LAR7_P_MSB _u(1)

#define	DMA_MPU_LAR7_P_RESET _u(0x0)

#define	DMA_MPU_LAR7_RESET _u(0x00000000)

#define	DMA_MPU_LAR7_S_ACCESS "RW"

#define	DMA_MPU_LAR7_S_BITS _u(0x00000004)

#define	DMA_MPU_LAR7_S_LSB _u(2)

#define	DMA_MPU_LAR7_S_MSB _u(2)

#define	DMA_MPU_LAR7_S_RESET _u(0x0)

#define	DMA_MULTI_CHAN_TRIGGER_ACCESS "SC"

#define	DMA_MULTI_CHAN_TRIGGER_BITS _u(0x0000ffff)

#define	DMA_MULTI_CHAN_TRIGGER_LSB _u(0)

#define	DMA_MULTI_CHAN_TRIGGER_MSB _u(15)

#define	DMA_MULTI_CHAN_TRIGGER_OFFSET _u(0x00000450)

#define	DMA_MULTI_CHAN_TRIGGER_RESET _u(0x00000000)

#define	DMA_N_CHANNELS_ACCESS "RO"

#define	DMA_N_CHANNELS_BITS _u(0x0000001f)

#define	DMA_N_CHANNELS_LSB _u(0)

#define	DMA_N_CHANNELS_MSB _u(4)

#define	DMA_N_CHANNELS_OFFSET _u(0x00000468)

#define	DMA_N_CHANNELS_RESET "-"

#define	DMA_SECCFG_CH0_BITS _u(0x00000007)

#define	DMA_SECCFG_CH0_LOCK_ACCESS "RW"

#define	DMA_SECCFG_CH0_LOCK_BITS _u(0x00000004)

#define	DMA_SECCFG_CH0_LOCK_LSB _u(2)

#define	DMA_SECCFG_CH0_LOCK_MSB _u(2)

#define	DMA_SECCFG_CH0_LOCK_RESET _u(0x0)

#define	DMA_SECCFG_CH0_OFFSET _u(0x00000480)

#define	DMA_SECCFG_CH0_P_ACCESS "RW"

#define	DMA_SECCFG_CH0_P_BITS _u(0x00000001)

#define	DMA_SECCFG_CH0_P_LSB _u(0)

#define	DMA_SECCFG_CH0_P_MSB _u(0)

#define	DMA_SECCFG_CH0_P_RESET _u(0x1)

#define	DMA_SECCFG_CH0_RESET _u(0x00000003)

#define	DMA_SECCFG_CH0_S_ACCESS "RW"

#define	DMA_SECCFG_CH0_S_BITS _u(0x00000002)

#define	DMA_SECCFG_CH0_S_LSB _u(1)

#define	DMA_SECCFG_CH0_S_MSB _u(1)

#define	DMA_SECCFG_CH0_S_RESET _u(0x1)

#define	DMA_SECCFG_CH10_BITS _u(0x00000007)

#define	DMA_SECCFG_CH10_LOCK_ACCESS "RW"

#define	DMA_SECCFG_CH10_LOCK_BITS _u(0x00000004)

#define	DMA_SECCFG_CH10_LOCK_LSB _u(2)

#define	DMA_SECCFG_CH10_LOCK_MSB _u(2)

#define	DMA_SECCFG_CH10_LOCK_RESET _u(0x0)

#define	DMA_SECCFG_CH10_OFFSET _u(0x000004a8)

#define	DMA_SECCFG_CH10_P_ACCESS "RW"

#define	DMA_SECCFG_CH10_P_BITS _u(0x00000001)

#define	DMA_SECCFG_CH10_P_LSB _u(0)

#define	DMA_SECCFG_CH10_P_MSB _u(0)

#define	DMA_SECCFG_CH10_P_RESET _u(0x1)

#define	DMA_SECCFG_CH10_RESET _u(0x00000003)

#define	DMA_SECCFG_CH10_S_ACCESS "RW"

#define	DMA_SECCFG_CH10_S_BITS _u(0x00000002)

#define	DMA_SECCFG_CH10_S_LSB _u(1)

#define	DMA_SECCFG_CH10_S_MSB _u(1)

#define	DMA_SECCFG_CH10_S_RESET _u(0x1)

#define	DMA_SECCFG_CH11_BITS _u(0x00000007)

#define	DMA_SECCFG_CH11_LOCK_ACCESS "RW"

#define	DMA_SECCFG_CH11_LOCK_BITS _u(0x00000004)

#define	DMA_SECCFG_CH11_LOCK_LSB _u(2)

#define	DMA_SECCFG_CH11_LOCK_MSB _u(2)

#define	DMA_SECCFG_CH11_LOCK_RESET _u(0x0)

#define	DMA_SECCFG_CH11_OFFSET _u(0x000004ac)

#define	DMA_SECCFG_CH11_P_ACCESS "RW"

#define	DMA_SECCFG_CH11_P_BITS _u(0x00000001)

#define	DMA_SECCFG_CH11_P_LSB _u(0)

#define	DMA_SECCFG_CH11_P_MSB _u(0)

#define	DMA_SECCFG_CH11_P_RESET _u(0x1)

#define	DMA_SECCFG_CH11_RESET _u(0x00000003)

#define	DMA_SECCFG_CH11_S_ACCESS "RW"

#define	DMA_SECCFG_CH11_S_BITS _u(0x00000002)

#define	DMA_SECCFG_CH11_S_LSB _u(1)

#define	DMA_SECCFG_CH11_S_MSB _u(1)

#define	DMA_SECCFG_CH11_S_RESET _u(0x1)

#define	DMA_SECCFG_CH12_BITS _u(0x00000007)

#define	DMA_SECCFG_CH12_LOCK_ACCESS "RW"

#define	DMA_SECCFG_CH12_LOCK_BITS _u(0x00000004)

#define	DMA_SECCFG_CH12_LOCK_LSB _u(2)

#define	DMA_SECCFG_CH12_LOCK_MSB _u(2)

#define	DMA_SECCFG_CH12_LOCK_RESET _u(0x0)

#define	DMA_SECCFG_CH12_OFFSET _u(0x000004b0)

#define	DMA_SECCFG_CH12_P_ACCESS "RW"

#define	DMA_SECCFG_CH12_P_BITS _u(0x00000001)

#define	DMA_SECCFG_CH12_P_LSB _u(0)

#define	DMA_SECCFG_CH12_P_MSB _u(0)

#define	DMA_SECCFG_CH12_P_RESET _u(0x1)

#define	DMA_SECCFG_CH12_RESET _u(0x00000003)

#define	DMA_SECCFG_CH12_S_ACCESS "RW"

#define	DMA_SECCFG_CH12_S_BITS _u(0x00000002)

#define	DMA_SECCFG_CH12_S_LSB _u(1)

#define	DMA_SECCFG_CH12_S_MSB _u(1)

#define	DMA_SECCFG_CH12_S_RESET _u(0x1)

#define	DMA_SECCFG_CH13_BITS _u(0x00000007)

#define	DMA_SECCFG_CH13_LOCK_ACCESS "RW"

#define	DMA_SECCFG_CH13_LOCK_BITS _u(0x00000004)

#define	DMA_SECCFG_CH13_LOCK_LSB _u(2)

#define	DMA_SECCFG_CH13_LOCK_MSB _u(2)

#define	DMA_SECCFG_CH13_LOCK_RESET _u(0x0)

#define	DMA_SECCFG_CH13_OFFSET _u(0x000004b4)

#define	DMA_SECCFG_CH13_P_ACCESS "RW"

#define	DMA_SECCFG_CH13_P_BITS _u(0x00000001)

#define	DMA_SECCFG_CH13_P_LSB _u(0)

#define	DMA_SECCFG_CH13_P_MSB _u(0)

#define	DMA_SECCFG_CH13_P_RESET _u(0x1)

#define	DMA_SECCFG_CH13_RESET _u(0x00000003)

#define	DMA_SECCFG_CH13_S_ACCESS "RW"

#define	DMA_SECCFG_CH13_S_BITS _u(0x00000002)

#define	DMA_SECCFG_CH13_S_LSB _u(1)

#define	DMA_SECCFG_CH13_S_MSB _u(1)

#define	DMA_SECCFG_CH13_S_RESET _u(0x1)

#define	DMA_SECCFG_CH14_BITS _u(0x00000007)

#define	DMA_SECCFG_CH14_LOCK_ACCESS "RW"

#define	DMA_SECCFG_CH14_LOCK_BITS _u(0x00000004)

#define	DMA_SECCFG_CH14_LOCK_LSB _u(2)

#define	DMA_SECCFG_CH14_LOCK_MSB _u(2)

#define	DMA_SECCFG_CH14_LOCK_RESET _u(0x0)

#define	DMA_SECCFG_CH14_OFFSET _u(0x000004b8)

#define	DMA_SECCFG_CH14_P_ACCESS "RW"

#define	DMA_SECCFG_CH14_P_BITS _u(0x00000001)

#define	DMA_SECCFG_CH14_P_LSB _u(0)

#define	DMA_SECCFG_CH14_P_MSB _u(0)

#define	DMA_SECCFG_CH14_P_RESET _u(0x1)

#define	DMA_SECCFG_CH14_RESET _u(0x00000003)

#define	DMA_SECCFG_CH14_S_ACCESS "RW"

#define	DMA_SECCFG_CH14_S_BITS _u(0x00000002)

#define	DMA_SECCFG_CH14_S_LSB _u(1)

#define	DMA_SECCFG_CH14_S_MSB _u(1)

#define	DMA_SECCFG_CH14_S_RESET _u(0x1)

#define	DMA_SECCFG_CH15_BITS _u(0x00000007)

#define	DMA_SECCFG_CH15_LOCK_ACCESS "RW"

#define	DMA_SECCFG_CH15_LOCK_BITS _u(0x00000004)

#define	DMA_SECCFG_CH15_LOCK_LSB _u(2)

#define	DMA_SECCFG_CH15_LOCK_MSB _u(2)

#define	DMA_SECCFG_CH15_LOCK_RESET _u(0x0)

#define	DMA_SECCFG_CH15_OFFSET _u(0x000004bc)

#define	DMA_SECCFG_CH15_P_ACCESS "RW"

#define	DMA_SECCFG_CH15_P_BITS _u(0x00000001)

#define	DMA_SECCFG_CH15_P_LSB _u(0)

#define	DMA_SECCFG_CH15_P_MSB _u(0)

#define	DMA_SECCFG_CH15_P_RESET _u(0x1)

#define	DMA_SECCFG_CH15_RESET _u(0x00000003)

#define	DMA_SECCFG_CH15_S_ACCESS "RW"

#define	DMA_SECCFG_CH15_S_BITS _u(0x00000002)

#define	DMA_SECCFG_CH15_S_LSB _u(1)

#define	DMA_SECCFG_CH15_S_MSB _u(1)

#define	DMA_SECCFG_CH15_S_RESET _u(0x1)

#define	DMA_SECCFG_CH1_BITS _u(0x00000007)

#define	DMA_SECCFG_CH1_LOCK_ACCESS "RW"

#define	DMA_SECCFG_CH1_LOCK_BITS _u(0x00000004)

#define	DMA_SECCFG_CH1_LOCK_LSB _u(2)

#define	DMA_SECCFG_CH1_LOCK_MSB _u(2)

#define	DMA_SECCFG_CH1_LOCK_RESET _u(0x0)

#define	DMA_SECCFG_CH1_OFFSET _u(0x00000484)

#define	DMA_SECCFG_CH1_P_ACCESS "RW"

#define	DMA_SECCFG_CH1_P_BITS _u(0x00000001)

#define	DMA_SECCFG_CH1_P_LSB _u(0)

#define	DMA_SECCFG_CH1_P_MSB _u(0)

#define	DMA_SECCFG_CH1_P_RESET _u(0x1)

#define	DMA_SECCFG_CH1_RESET _u(0x00000003)

#define	DMA_SECCFG_CH1_S_ACCESS "RW"

#define	DMA_SECCFG_CH1_S_BITS _u(0x00000002)

#define	DMA_SECCFG_CH1_S_LSB _u(1)

#define	DMA_SECCFG_CH1_S_MSB _u(1)

#define	DMA_SECCFG_CH1_S_RESET _u(0x1)

#define	DMA_SECCFG_CH2_BITS _u(0x00000007)

#define	DMA_SECCFG_CH2_LOCK_ACCESS "RW"

#define	DMA_SECCFG_CH2_LOCK_BITS _u(0x00000004)

#define	DMA_SECCFG_CH2_LOCK_LSB _u(2)

#define	DMA_SECCFG_CH2_LOCK_MSB _u(2)

#define	DMA_SECCFG_CH2_LOCK_RESET _u(0x0)

#define	DMA_SECCFG_CH2_OFFSET _u(0x00000488)

#define	DMA_SECCFG_CH2_P_ACCESS "RW"

#define	DMA_SECCFG_CH2_P_BITS _u(0x00000001)

#define	DMA_SECCFG_CH2_P_LSB _u(0)

#define	DMA_SECCFG_CH2_P_MSB _u(0)

#define	DMA_SECCFG_CH2_P_RESET _u(0x1)

#define	DMA_SECCFG_CH2_RESET _u(0x00000003)

#define	DMA_SECCFG_CH2_S_ACCESS "RW"

#define	DMA_SECCFG_CH2_S_BITS _u(0x00000002)

#define	DMA_SECCFG_CH2_S_LSB _u(1)

#define	DMA_SECCFG_CH2_S_MSB _u(1)

#define	DMA_SECCFG_CH2_S_RESET _u(0x1)

#define	DMA_SECCFG_CH3_BITS _u(0x00000007)

#define	DMA_SECCFG_CH3_LOCK_ACCESS "RW"

#define	DMA_SECCFG_CH3_LOCK_BITS _u(0x00000004)

#define	DMA_SECCFG_CH3_LOCK_LSB _u(2)

#define	DMA_SECCFG_CH3_LOCK_MSB _u(2)

#define	DMA_SECCFG_CH3_LOCK_RESET _u(0x0)

#define	DMA_SECCFG_CH3_OFFSET _u(0x0000048c)

#define	DMA_SECCFG_CH3_P_ACCESS "RW"

#define	DMA_SECCFG_CH3_P_BITS _u(0x00000001)

#define	DMA_SECCFG_CH3_P_LSB _u(0)

#define	DMA_SECCFG_CH3_P_MSB _u(0)

#define	DMA_SECCFG_CH3_P_RESET _u(0x1)

#define	DMA_SECCFG_CH3_RESET _u(0x00000003)

#define	DMA_SECCFG_CH3_S_ACCESS "RW"

#define	DMA_SECCFG_CH3_S_BITS _u(0x00000002)

#define	DMA_SECCFG_CH3_S_LSB _u(1)

#define	DMA_SECCFG_CH3_S_MSB _u(1)

#define	DMA_SECCFG_CH3_S_RESET _u(0x1)

#define	DMA_SECCFG_CH4_BITS _u(0x00000007)

#define	DMA_SECCFG_CH4_LOCK_ACCESS "RW"

#define	DMA_SECCFG_CH4_LOCK_BITS _u(0x00000004)

#define	DMA_SECCFG_CH4_LOCK_LSB _u(2)

#define	DMA_SECCFG_CH4_LOCK_MSB _u(2)

#define	DMA_SECCFG_CH4_LOCK_RESET _u(0x0)

#define	DMA_SECCFG_CH4_OFFSET _u(0x00000490)

#define	DMA_SECCFG_CH4_P_ACCESS "RW"

#define	DMA_SECCFG_CH4_P_BITS _u(0x00000001)

#define	DMA_SECCFG_CH4_P_LSB _u(0)

#define	DMA_SECCFG_CH4_P_MSB _u(0)

#define	DMA_SECCFG_CH4_P_RESET _u(0x1)

#define	DMA_SECCFG_CH4_RESET _u(0x00000003)

#define	DMA_SECCFG_CH4_S_ACCESS "RW"

#define	DMA_SECCFG_CH4_S_BITS _u(0x00000002)

#define	DMA_SECCFG_CH4_S_LSB _u(1)

#define	DMA_SECCFG_CH4_S_MSB _u(1)

#define	DMA_SECCFG_CH4_S_RESET _u(0x1)

#define	DMA_SECCFG_CH5_BITS _u(0x00000007)

#define	DMA_SECCFG_CH5_LOCK_ACCESS "RW"

#define	DMA_SECCFG_CH5_LOCK_BITS _u(0x00000004)

#define	DMA_SECCFG_CH5_LOCK_LSB _u(2)

#define	DMA_SECCFG_CH5_LOCK_MSB _u(2)

#define	DMA_SECCFG_CH5_LOCK_RESET _u(0x0)

#define	DMA_SECCFG_CH5_OFFSET _u(0x00000494)

#define	DMA_SECCFG_CH5_P_ACCESS "RW"

#define	DMA_SECCFG_CH5_P_BITS _u(0x00000001)

#define	DMA_SECCFG_CH5_P_LSB _u(0)

#define	DMA_SECCFG_CH5_P_MSB _u(0)

#define	DMA_SECCFG_CH5_P_RESET _u(0x1)

#define	DMA_SECCFG_CH5_RESET _u(0x00000003)

#define	DMA_SECCFG_CH5_S_ACCESS "RW"

#define	DMA_SECCFG_CH5_S_BITS _u(0x00000002)

#define	DMA_SECCFG_CH5_S_LSB _u(1)

#define	DMA_SECCFG_CH5_S_MSB _u(1)

#define	DMA_SECCFG_CH5_S_RESET _u(0x1)

#define	DMA_SECCFG_CH6_BITS _u(0x00000007)

#define	DMA_SECCFG_CH6_LOCK_ACCESS "RW"

#define	DMA_SECCFG_CH6_LOCK_BITS _u(0x00000004)

#define	DMA_SECCFG_CH6_LOCK_LSB _u(2)

#define	DMA_SECCFG_CH6_LOCK_MSB _u(2)

#define	DMA_SECCFG_CH6_LOCK_RESET _u(0x0)

#define	DMA_SECCFG_CH6_OFFSET _u(0x00000498)

#define	DMA_SECCFG_CH6_P_ACCESS "RW"

#define	DMA_SECCFG_CH6_P_BITS _u(0x00000001)

#define	DMA_SECCFG_CH6_P_LSB _u(0)

#define	DMA_SECCFG_CH6_P_MSB _u(0)

#define	DMA_SECCFG_CH6_P_RESET _u(0x1)

#define	DMA_SECCFG_CH6_RESET _u(0x00000003)

#define	DMA_SECCFG_CH6_S_ACCESS "RW"

#define	DMA_SECCFG_CH6_S_BITS _u(0x00000002)

#define	DMA_SECCFG_CH6_S_LSB _u(1)

#define	DMA_SECCFG_CH6_S_MSB _u(1)

#define	DMA_SECCFG_CH6_S_RESET _u(0x1)

#define	DMA_SECCFG_CH7_BITS _u(0x00000007)

#define	DMA_SECCFG_CH7_LOCK_ACCESS "RW"

#define	DMA_SECCFG_CH7_LOCK_BITS _u(0x00000004)

#define	DMA_SECCFG_CH7_LOCK_LSB _u(2)

#define	DMA_SECCFG_CH7_LOCK_MSB _u(2)

#define	DMA_SECCFG_CH7_LOCK_RESET _u(0x0)

#define	DMA_SECCFG_CH7_OFFSET _u(0x0000049c)

#define	DMA_SECCFG_CH7_P_ACCESS "RW"

#define	DMA_SECCFG_CH7_P_BITS _u(0x00000001)

#define	DMA_SECCFG_CH7_P_LSB _u(0)

#define	DMA_SECCFG_CH7_P_MSB _u(0)

#define	DMA_SECCFG_CH7_P_RESET _u(0x1)

#define	DMA_SECCFG_CH7_RESET _u(0x00000003)

#define	DMA_SECCFG_CH7_S_ACCESS "RW"

#define	DMA_SECCFG_CH7_S_BITS _u(0x00000002)

#define	DMA_SECCFG_CH7_S_LSB _u(1)

#define	DMA_SECCFG_CH7_S_MSB _u(1)

#define	DMA_SECCFG_CH7_S_RESET _u(0x1)

#define	DMA_SECCFG_CH8_BITS _u(0x00000007)

#define	DMA_SECCFG_CH8_LOCK_ACCESS "RW"

#define	DMA_SECCFG_CH8_LOCK_BITS _u(0x00000004)

#define	DMA_SECCFG_CH8_LOCK_LSB _u(2)

#define	DMA_SECCFG_CH8_LOCK_MSB _u(2)

#define	DMA_SECCFG_CH8_LOCK_RESET _u(0x0)

#define	DMA_SECCFG_CH8_OFFSET _u(0x000004a0)

#define	DMA_SECCFG_CH8_P_ACCESS "RW"

#define	DMA_SECCFG_CH8_P_BITS _u(0x00000001)

#define	DMA_SECCFG_CH8_P_LSB _u(0)

#define	DMA_SECCFG_CH8_P_MSB _u(0)

#define	DMA_SECCFG_CH8_P_RESET _u(0x1)

#define	DMA_SECCFG_CH8_RESET _u(0x00000003)

#define	DMA_SECCFG_CH8_S_ACCESS "RW"

#define	DMA_SECCFG_CH8_S_BITS _u(0x00000002)

#define	DMA_SECCFG_CH8_S_LSB _u(1)

#define	DMA_SECCFG_CH8_S_MSB _u(1)

#define	DMA_SECCFG_CH8_S_RESET _u(0x1)

#define	DMA_SECCFG_CH9_BITS _u(0x00000007)

#define	DMA_SECCFG_CH9_LOCK_ACCESS "RW"

#define	DMA_SECCFG_CH9_LOCK_BITS _u(0x00000004)

#define	DMA_SECCFG_CH9_LOCK_LSB _u(2)

#define	DMA_SECCFG_CH9_LOCK_MSB _u(2)

#define	DMA_SECCFG_CH9_LOCK_RESET _u(0x0)

#define	DMA_SECCFG_CH9_OFFSET _u(0x000004a4)

#define	DMA_SECCFG_CH9_P_ACCESS "RW"

#define	DMA_SECCFG_CH9_P_BITS _u(0x00000001)

#define	DMA_SECCFG_CH9_P_LSB _u(0)

#define	DMA_SECCFG_CH9_P_MSB _u(0)

#define	DMA_SECCFG_CH9_P_RESET _u(0x1)

#define	DMA_SECCFG_CH9_RESET _u(0x00000003)

#define	DMA_SECCFG_CH9_S_ACCESS "RW"

#define	DMA_SECCFG_CH9_S_BITS _u(0x00000002)

#define	DMA_SECCFG_CH9_S_LSB _u(1)

#define	DMA_SECCFG_CH9_S_MSB _u(1)

#define	DMA_SECCFG_CH9_S_RESET _u(0x1)

#define	DMA_SECCFG_IRQ0_BITS _u(0x00000003)

#define	DMA_SECCFG_IRQ0_OFFSET _u(0x000004c0)

#define	DMA_SECCFG_IRQ0_P_ACCESS "RW"

#define	DMA_SECCFG_IRQ0_P_BITS _u(0x00000001)

#define	DMA_SECCFG_IRQ0_P_LSB _u(0)

#define	DMA_SECCFG_IRQ0_P_MSB _u(0)

#define	DMA_SECCFG_IRQ0_P_RESET _u(0x1)

#define	DMA_SECCFG_IRQ0_RESET _u(0x00000003)

#define	DMA_SECCFG_IRQ0_S_ACCESS "RW"

#define	DMA_SECCFG_IRQ0_S_BITS _u(0x00000002)

#define	DMA_SECCFG_IRQ0_S_LSB _u(1)

#define	DMA_SECCFG_IRQ0_S_MSB _u(1)

#define	DMA_SECCFG_IRQ0_S_RESET _u(0x1)

#define	DMA_SECCFG_IRQ1_BITS _u(0x00000003)

#define	DMA_SECCFG_IRQ1_OFFSET _u(0x000004c4)

#define	DMA_SECCFG_IRQ1_P_ACCESS "RW"

#define	DMA_SECCFG_IRQ1_P_BITS _u(0x00000001)

#define	DMA_SECCFG_IRQ1_P_LSB _u(0)

#define	DMA_SECCFG_IRQ1_P_MSB _u(0)

#define	DMA_SECCFG_IRQ1_P_RESET _u(0x1)

#define	DMA_SECCFG_IRQ1_RESET _u(0x00000003)

#define	DMA_SECCFG_IRQ1_S_ACCESS "RW"

#define	DMA_SECCFG_IRQ1_S_BITS _u(0x00000002)

#define	DMA_SECCFG_IRQ1_S_LSB _u(1)

#define	DMA_SECCFG_IRQ1_S_MSB _u(1)

#define	DMA_SECCFG_IRQ1_S_RESET _u(0x1)

#define	DMA_SECCFG_IRQ2_BITS _u(0x00000003)

#define	DMA_SECCFG_IRQ2_OFFSET _u(0x000004c8)

#define	DMA_SECCFG_IRQ2_P_ACCESS "RW"

#define	DMA_SECCFG_IRQ2_P_BITS _u(0x00000001)

#define	DMA_SECCFG_IRQ2_P_LSB _u(0)

#define	DMA_SECCFG_IRQ2_P_MSB _u(0)

#define	DMA_SECCFG_IRQ2_P_RESET _u(0x1)

#define	DMA_SECCFG_IRQ2_RESET _u(0x00000003)

#define	DMA_SECCFG_IRQ2_S_ACCESS "RW"

#define	DMA_SECCFG_IRQ2_S_BITS _u(0x00000002)

#define	DMA_SECCFG_IRQ2_S_LSB _u(1)

#define	DMA_SECCFG_IRQ2_S_MSB _u(1)

#define	DMA_SECCFG_IRQ2_S_RESET _u(0x1)

#define	DMA_SECCFG_IRQ3_BITS _u(0x00000003)

#define	DMA_SECCFG_IRQ3_OFFSET _u(0x000004cc)

#define	DMA_SECCFG_IRQ3_P_ACCESS "RW"

#define	DMA_SECCFG_IRQ3_P_BITS _u(0x00000001)

#define	DMA_SECCFG_IRQ3_P_LSB _u(0)

#define	DMA_SECCFG_IRQ3_P_MSB _u(0)

#define	DMA_SECCFG_IRQ3_P_RESET _u(0x1)

#define	DMA_SECCFG_IRQ3_RESET _u(0x00000003)

#define	DMA_SECCFG_IRQ3_S_ACCESS "RW"

#define	DMA_SECCFG_IRQ3_S_BITS _u(0x00000002)

#define	DMA_SECCFG_IRQ3_S_LSB _u(1)

#define	DMA_SECCFG_IRQ3_S_MSB _u(1)

#define	DMA_SECCFG_IRQ3_S_RESET _u(0x1)

#define	DMA_SECCFG_MISC_BITS _u(0x000003ff)

#define	DMA_SECCFG_MISC_OFFSET _u(0x000004d0)

#define	DMA_SECCFG_MISC_RESET _u(0x000003ff)

#define	DMA_SECCFG_MISC_SNIFF_P_ACCESS "RW"

#define	DMA_SECCFG_MISC_SNIFF_P_BITS _u(0x00000001)

#define	DMA_SECCFG_MISC_SNIFF_P_LSB _u(0)

#define	DMA_SECCFG_MISC_SNIFF_P_MSB _u(0)

#define	DMA_SECCFG_MISC_SNIFF_P_RESET _u(0x1)

#define	DMA_SECCFG_MISC_SNIFF_S_ACCESS "RW"

#define	DMA_SECCFG_MISC_SNIFF_S_BITS _u(0x00000002)

#define	DMA_SECCFG_MISC_SNIFF_S_LSB _u(1)

#define	DMA_SECCFG_MISC_SNIFF_S_MSB _u(1)

#define	DMA_SECCFG_MISC_SNIFF_S_RESET _u(0x1)

#define	DMA_SECCFG_MISC_TIMER0_P_ACCESS "RW"

#define	DMA_SECCFG_MISC_TIMER0_P_BITS _u(0x00000004)

#define	DMA_SECCFG_MISC_TIMER0_P_LSB _u(2)

#define	DMA_SECCFG_MISC_TIMER0_P_MSB _u(2)

#define	DMA_SECCFG_MISC_TIMER0_P_RESET _u(0x1)

#define	DMA_SECCFG_MISC_TIMER0_S_ACCESS "RW"

#define	DMA_SECCFG_MISC_TIMER0_S_BITS _u(0x00000008)

#define	DMA_SECCFG_MISC_TIMER0_S_LSB _u(3)

#define	DMA_SECCFG_MISC_TIMER0_S_MSB _u(3)

#define	DMA_SECCFG_MISC_TIMER0_S_RESET _u(0x1)

#define	DMA_SECCFG_MISC_TIMER1_P_ACCESS "RW"

#define	DMA_SECCFG_MISC_TIMER1_P_BITS _u(0x00000010)

#define	DMA_SECCFG_MISC_TIMER1_P_LSB _u(4)

#define	DMA_SECCFG_MISC_TIMER1_P_MSB _u(4)

#define	DMA_SECCFG_MISC_TIMER1_P_RESET _u(0x1)

#define	DMA_SECCFG_MISC_TIMER1_S_ACCESS "RW"

#define	DMA_SECCFG_MISC_TIMER1_S_BITS _u(0x00000020)

#define	DMA_SECCFG_MISC_TIMER1_S_LSB _u(5)

#define	DMA_SECCFG_MISC_TIMER1_S_MSB _u(5)

#define	DMA_SECCFG_MISC_TIMER1_S_RESET _u(0x1)

#define	DMA_SECCFG_MISC_TIMER2_P_ACCESS "RW"

#define	DMA_SECCFG_MISC_TIMER2_P_BITS _u(0x00000040)

#define	DMA_SECCFG_MISC_TIMER2_P_LSB _u(6)

#define	DMA_SECCFG_MISC_TIMER2_P_MSB _u(6)

#define	DMA_SECCFG_MISC_TIMER2_P_RESET _u(0x1)

#define	DMA_SECCFG_MISC_TIMER2_S_ACCESS "RW"

#define	DMA_SECCFG_MISC_TIMER2_S_BITS _u(0x00000080)

#define	DMA_SECCFG_MISC_TIMER2_S_LSB _u(7)

#define	DMA_SECCFG_MISC_TIMER2_S_MSB _u(7)

#define	DMA_SECCFG_MISC_TIMER2_S_RESET _u(0x1)

#define	DMA_SECCFG_MISC_TIMER3_P_ACCESS "RW"

#define	DMA_SECCFG_MISC_TIMER3_P_BITS _u(0x00000100)

#define	DMA_SECCFG_MISC_TIMER3_P_LSB _u(8)

#define	DMA_SECCFG_MISC_TIMER3_P_MSB _u(8)

#define	DMA_SECCFG_MISC_TIMER3_P_RESET _u(0x1)

#define	DMA_SECCFG_MISC_TIMER3_S_ACCESS "RW"

#define	DMA_SECCFG_MISC_TIMER3_S_BITS _u(0x00000200)

#define	DMA_SECCFG_MISC_TIMER3_S_LSB _u(9)

#define	DMA_SECCFG_MISC_TIMER3_S_MSB _u(9)

#define	DMA_SECCFG_MISC_TIMER3_S_RESET _u(0x1)

#define	DMA_SNIFF_CTRL_BITS _u(0x00000fff)

#define	DMA_SNIFF_CTRL_BSWAP_ACCESS "RW"

#define	DMA_SNIFF_CTRL_BSWAP_BITS _u(0x00000200)

#define	DMA_SNIFF_CTRL_BSWAP_LSB _u(9)

#define	DMA_SNIFF_CTRL_BSWAP_MSB _u(9)

#define	DMA_SNIFF_CTRL_BSWAP_RESET _u(0x0)

#define	DMA_SNIFF_CTRL_CALC_ACCESS "RW"

#define	DMA_SNIFF_CTRL_CALC_BITS _u(0x000001e0)

#define	DMA_SNIFF_CTRL_CALC_LSB _u(5)

#define	DMA_SNIFF_CTRL_CALC_MSB _u(8)

#define	DMA_SNIFF_CTRL_CALC_RESET _u(0x0)

#define	DMA_SNIFF_CTRL_CALC_VALUE_CRC16 _u(0x2)

#define	DMA_SNIFF_CTRL_CALC_VALUE_CRC16R _u(0x3)

#define	DMA_SNIFF_CTRL_CALC_VALUE_CRC32 _u(0x0)

#define	DMA_SNIFF_CTRL_CALC_VALUE_CRC32R _u(0x1)

#define	DMA_SNIFF_CTRL_CALC_VALUE_EVEN _u(0xe)

#define	DMA_SNIFF_CTRL_CALC_VALUE_SUM _u(0xf)

#define	DMA_SNIFF_CTRL_DMACH_ACCESS "RW"

#define	DMA_SNIFF_CTRL_DMACH_BITS _u(0x0000001e)

#define	DMA_SNIFF_CTRL_DMACH_LSB _u(1)

#define	DMA_SNIFF_CTRL_DMACH_MSB _u(4)

#define	DMA_SNIFF_CTRL_DMACH_RESET _u(0x0)

#define	DMA_SNIFF_CTRL_EN_ACCESS "RW"

#define	DMA_SNIFF_CTRL_EN_BITS _u(0x00000001)

#define	DMA_SNIFF_CTRL_EN_LSB _u(0)

#define	DMA_SNIFF_CTRL_EN_MSB _u(0)

#define	DMA_SNIFF_CTRL_EN_RESET _u(0x0)

#define	DMA_SNIFF_CTRL_OFFSET _u(0x00000454)

#define	DMA_SNIFF_CTRL_OUT_INV_ACCESS "RW"

#define	DMA_SNIFF_CTRL_OUT_INV_BITS _u(0x00000800)

#define	DMA_SNIFF_CTRL_OUT_INV_LSB _u(11)

#define	DMA_SNIFF_CTRL_OUT_INV_MSB _u(11)

#define	DMA_SNIFF_CTRL_OUT_INV_RESET _u(0x0)

#define	DMA_SNIFF_CTRL_OUT_REV_ACCESS "RW"

#define	DMA_SNIFF_CTRL_OUT_REV_BITS _u(0x00000400)

#define	DMA_SNIFF_CTRL_OUT_REV_LSB _u(10)

#define	DMA_SNIFF_CTRL_OUT_REV_MSB _u(10)

#define	DMA_SNIFF_CTRL_OUT_REV_RESET _u(0x0)

#define	DMA_SNIFF_CTRL_RESET _u(0x00000000)

#define	DMA_SNIFF_DATA_ACCESS "RW"

#define	DMA_SNIFF_DATA_BITS _u(0xffffffff)

#define	DMA_SNIFF_DATA_LSB _u(0)

#define	DMA_SNIFF_DATA_MSB _u(31)

#define	DMA_SNIFF_DATA_OFFSET _u(0x00000458)

#define	DMA_SNIFF_DATA_RESET _u(0x00000000)

#define	DMA_TIMER0_BITS _u(0xffffffff)

#define	DMA_TIMER0_OFFSET _u(0x00000440)

#define	DMA_TIMER0_RESET _u(0x00000000)

#define	DMA_TIMER0_X_ACCESS "RW"

#define	DMA_TIMER0_X_BITS _u(0xffff0000)

#define	DMA_TIMER0_X_LSB _u(16)

#define	DMA_TIMER0_X_MSB _u(31)

#define	DMA_TIMER0_X_RESET _u(0x0000)

#define	DMA_TIMER0_Y_ACCESS "RW"

#define	DMA_TIMER0_Y_BITS _u(0x0000ffff)

#define	DMA_TIMER0_Y_LSB _u(0)

#define	DMA_TIMER0_Y_MSB _u(15)

#define	DMA_TIMER0_Y_RESET _u(0x0000)

#define	DMA_TIMER1_BITS _u(0xffffffff)

#define	DMA_TIMER1_OFFSET _u(0x00000444)

#define	DMA_TIMER1_RESET _u(0x00000000)

#define	DMA_TIMER1_X_ACCESS "RW"

#define	DMA_TIMER1_X_BITS _u(0xffff0000)

#define	DMA_TIMER1_X_LSB _u(16)

#define	DMA_TIMER1_X_MSB _u(31)

#define	DMA_TIMER1_X_RESET _u(0x0000)

#define	DMA_TIMER1_Y_ACCESS "RW"

#define	DMA_TIMER1_Y_BITS _u(0x0000ffff)

#define	DMA_TIMER1_Y_LSB _u(0)

#define	DMA_TIMER1_Y_MSB _u(15)

#define	DMA_TIMER1_Y_RESET _u(0x0000)

#define	DMA_TIMER2_BITS _u(0xffffffff)

#define	DMA_TIMER2_OFFSET _u(0x00000448)

#define	DMA_TIMER2_RESET _u(0x00000000)

#define	DMA_TIMER2_X_ACCESS "RW"

#define	DMA_TIMER2_X_BITS _u(0xffff0000)

#define	DMA_TIMER2_X_LSB _u(16)

#define	DMA_TIMER2_X_MSB _u(31)

#define	DMA_TIMER2_X_RESET _u(0x0000)

#define	DMA_TIMER2_Y_ACCESS "RW"

#define	DMA_TIMER2_Y_BITS _u(0x0000ffff)

#define	DMA_TIMER2_Y_LSB _u(0)

#define	DMA_TIMER2_Y_MSB _u(15)

#define	DMA_TIMER2_Y_RESET _u(0x0000)

#define	DMA_TIMER3_BITS _u(0xffffffff)

#define	DMA_TIMER3_OFFSET _u(0x0000044c)

#define	DMA_TIMER3_RESET _u(0x00000000)

#define	DMA_TIMER3_X_ACCESS "RW"

#define	DMA_TIMER3_X_BITS _u(0xffff0000)

#define	DMA_TIMER3_X_LSB _u(16)

#define	DMA_TIMER3_X_MSB _u(31)

#define	DMA_TIMER3_X_RESET _u(0x0000)

#define	DMA_TIMER3_Y_ACCESS "RW"

#define	DMA_TIMER3_Y_BITS _u(0x0000ffff)

#define	DMA_TIMER3_Y_LSB _u(0)

#define	DMA_TIMER3_Y_MSB _u(15)

#define	DMA_TIMER3_Y_RESET _u(0x0000)

Documentação das macros

◆ DMA_CH0_AL1_CTRL_ACCESS

#define DMA_CH0_AL1_CTRL_ACCESS "RW"

◆ DMA_CH0_AL1_CTRL_BITS

#define DMA_CH0_AL1_CTRL_BITS _u(0xffffffff)

◆ DMA_CH0_AL1_CTRL_LSB

#define DMA_CH0_AL1_CTRL_LSB _u(0)

◆ DMA_CH0_AL1_CTRL_MSB

#define DMA_CH0_AL1_CTRL_MSB _u(31)

◆ DMA_CH0_AL1_CTRL_OFFSET

#define DMA_CH0_AL1_CTRL_OFFSET _u(0x00000010)

◆ DMA_CH0_AL1_CTRL_RESET

#define DMA_CH0_AL1_CTRL_RESET "-"

◆ DMA_CH0_AL1_READ_ADDR_ACCESS

#define DMA_CH0_AL1_READ_ADDR_ACCESS "RW"

◆ DMA_CH0_AL1_READ_ADDR_BITS

#define DMA_CH0_AL1_READ_ADDR_BITS _u(0xffffffff)

◆ DMA_CH0_AL1_READ_ADDR_LSB

#define DMA_CH0_AL1_READ_ADDR_LSB _u(0)

◆ DMA_CH0_AL1_READ_ADDR_MSB

#define DMA_CH0_AL1_READ_ADDR_MSB _u(31)

◆ DMA_CH0_AL1_READ_ADDR_OFFSET

#define DMA_CH0_AL1_READ_ADDR_OFFSET _u(0x00000014)

◆ DMA_CH0_AL1_READ_ADDR_RESET

#define DMA_CH0_AL1_READ_ADDR_RESET "-"

◆ DMA_CH0_AL1_TRANS_COUNT_TRIG_ACCESS

#define DMA_CH0_AL1_TRANS_COUNT_TRIG_ACCESS "RW"

◆ DMA_CH0_AL1_TRANS_COUNT_TRIG_BITS

#define DMA_CH0_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff)

◆ DMA_CH0_AL1_TRANS_COUNT_TRIG_LSB

#define DMA_CH0_AL1_TRANS_COUNT_TRIG_LSB _u(0)

◆ DMA_CH0_AL1_TRANS_COUNT_TRIG_MSB

#define DMA_CH0_AL1_TRANS_COUNT_TRIG_MSB _u(31)

◆ DMA_CH0_AL1_TRANS_COUNT_TRIG_OFFSET

#define DMA_CH0_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000001c)

◆ DMA_CH0_AL1_TRANS_COUNT_TRIG_RESET

#define DMA_CH0_AL1_TRANS_COUNT_TRIG_RESET "-"

◆ DMA_CH0_AL1_WRITE_ADDR_ACCESS

#define DMA_CH0_AL1_WRITE_ADDR_ACCESS "RW"

◆ DMA_CH0_AL1_WRITE_ADDR_BITS

#define DMA_CH0_AL1_WRITE_ADDR_BITS _u(0xffffffff)

◆ DMA_CH0_AL1_WRITE_ADDR_LSB

#define DMA_CH0_AL1_WRITE_ADDR_LSB _u(0)

◆ DMA_CH0_AL1_WRITE_ADDR_MSB

#define DMA_CH0_AL1_WRITE_ADDR_MSB _u(31)

◆ DMA_CH0_AL1_WRITE_ADDR_OFFSET

#define DMA_CH0_AL1_WRITE_ADDR_OFFSET _u(0x00000018)

◆ DMA_CH0_AL1_WRITE_ADDR_RESET

#define DMA_CH0_AL1_WRITE_ADDR_RESET "-"

◆ DMA_CH0_AL2_CTRL_ACCESS

#define DMA_CH0_AL2_CTRL_ACCESS "RW"

◆ DMA_CH0_AL2_CTRL_BITS

#define DMA_CH0_AL2_CTRL_BITS _u(0xffffffff)

◆ DMA_CH0_AL2_CTRL_LSB

#define DMA_CH0_AL2_CTRL_LSB _u(0)

◆ DMA_CH0_AL2_CTRL_MSB

#define DMA_CH0_AL2_CTRL_MSB _u(31)

◆ DMA_CH0_AL2_CTRL_OFFSET

#define DMA_CH0_AL2_CTRL_OFFSET _u(0x00000020)

◆ DMA_CH0_AL2_CTRL_RESET

#define DMA_CH0_AL2_CTRL_RESET "-"

◆ DMA_CH0_AL2_READ_ADDR_ACCESS

#define DMA_CH0_AL2_READ_ADDR_ACCESS "RW"

◆ DMA_CH0_AL2_READ_ADDR_BITS

#define DMA_CH0_AL2_READ_ADDR_BITS _u(0xffffffff)

◆ DMA_CH0_AL2_READ_ADDR_LSB

#define DMA_CH0_AL2_READ_ADDR_LSB _u(0)

◆ DMA_CH0_AL2_READ_ADDR_MSB

#define DMA_CH0_AL2_READ_ADDR_MSB _u(31)

◆ DMA_CH0_AL2_READ_ADDR_OFFSET

#define DMA_CH0_AL2_READ_ADDR_OFFSET _u(0x00000028)

◆ DMA_CH0_AL2_READ_ADDR_RESET

#define DMA_CH0_AL2_READ_ADDR_RESET "-"

◆ DMA_CH0_AL2_TRANS_COUNT_ACCESS

#define DMA_CH0_AL2_TRANS_COUNT_ACCESS "RW"

◆ DMA_CH0_AL2_TRANS_COUNT_BITS

#define DMA_CH0_AL2_TRANS_COUNT_BITS _u(0xffffffff)

◆ DMA_CH0_AL2_TRANS_COUNT_LSB

#define DMA_CH0_AL2_TRANS_COUNT_LSB _u(0)

◆ DMA_CH0_AL2_TRANS_COUNT_MSB

#define DMA_CH0_AL2_TRANS_COUNT_MSB _u(31)

◆ DMA_CH0_AL2_TRANS_COUNT_OFFSET

#define DMA_CH0_AL2_TRANS_COUNT_OFFSET _u(0x00000024)

◆ DMA_CH0_AL2_TRANS_COUNT_RESET

#define DMA_CH0_AL2_TRANS_COUNT_RESET "-"

◆ DMA_CH0_AL2_WRITE_ADDR_TRIG_ACCESS

#define DMA_CH0_AL2_WRITE_ADDR_TRIG_ACCESS "RW"

◆ DMA_CH0_AL2_WRITE_ADDR_TRIG_BITS

#define DMA_CH0_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff)

◆ DMA_CH0_AL2_WRITE_ADDR_TRIG_LSB

#define DMA_CH0_AL2_WRITE_ADDR_TRIG_LSB _u(0)

◆ DMA_CH0_AL2_WRITE_ADDR_TRIG_MSB

#define DMA_CH0_AL2_WRITE_ADDR_TRIG_MSB _u(31)

◆ DMA_CH0_AL2_WRITE_ADDR_TRIG_OFFSET

#define DMA_CH0_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x0000002c)

◆ DMA_CH0_AL2_WRITE_ADDR_TRIG_RESET

#define DMA_CH0_AL2_WRITE_ADDR_TRIG_RESET "-"

◆ DMA_CH0_AL3_CTRL_ACCESS

#define DMA_CH0_AL3_CTRL_ACCESS "RW"

◆ DMA_CH0_AL3_CTRL_BITS

#define DMA_CH0_AL3_CTRL_BITS _u(0xffffffff)

◆ DMA_CH0_AL3_CTRL_LSB

#define DMA_CH0_AL3_CTRL_LSB _u(0)

◆ DMA_CH0_AL3_CTRL_MSB

#define DMA_CH0_AL3_CTRL_MSB _u(31)

◆ DMA_CH0_AL3_CTRL_OFFSET

#define DMA_CH0_AL3_CTRL_OFFSET _u(0x00000030)

◆ DMA_CH0_AL3_CTRL_RESET

#define DMA_CH0_AL3_CTRL_RESET "-"

◆ DMA_CH0_AL3_READ_ADDR_TRIG_ACCESS

#define DMA_CH0_AL3_READ_ADDR_TRIG_ACCESS "RW"

◆ DMA_CH0_AL3_READ_ADDR_TRIG_BITS

#define DMA_CH0_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff)

◆ DMA_CH0_AL3_READ_ADDR_TRIG_LSB

#define DMA_CH0_AL3_READ_ADDR_TRIG_LSB _u(0)

◆ DMA_CH0_AL3_READ_ADDR_TRIG_MSB

#define DMA_CH0_AL3_READ_ADDR_TRIG_MSB _u(31)

◆ DMA_CH0_AL3_READ_ADDR_TRIG_OFFSET

#define DMA_CH0_AL3_READ_ADDR_TRIG_OFFSET _u(0x0000003c)

◆ DMA_CH0_AL3_READ_ADDR_TRIG_RESET

#define DMA_CH0_AL3_READ_ADDR_TRIG_RESET "-"

◆ DMA_CH0_AL3_TRANS_COUNT_ACCESS

#define DMA_CH0_AL3_TRANS_COUNT_ACCESS "RW"

◆ DMA_CH0_AL3_TRANS_COUNT_BITS

#define DMA_CH0_AL3_TRANS_COUNT_BITS _u(0xffffffff)

◆ DMA_CH0_AL3_TRANS_COUNT_LSB

#define DMA_CH0_AL3_TRANS_COUNT_LSB _u(0)

◆ DMA_CH0_AL3_TRANS_COUNT_MSB

#define DMA_CH0_AL3_TRANS_COUNT_MSB _u(31)

◆ DMA_CH0_AL3_TRANS_COUNT_OFFSET

#define DMA_CH0_AL3_TRANS_COUNT_OFFSET _u(0x00000038)

◆ DMA_CH0_AL3_TRANS_COUNT_RESET

#define DMA_CH0_AL3_TRANS_COUNT_RESET "-"

◆ DMA_CH0_AL3_WRITE_ADDR_ACCESS

#define DMA_CH0_AL3_WRITE_ADDR_ACCESS "RW"

◆ DMA_CH0_AL3_WRITE_ADDR_BITS

#define DMA_CH0_AL3_WRITE_ADDR_BITS _u(0xffffffff)

◆ DMA_CH0_AL3_WRITE_ADDR_LSB

#define DMA_CH0_AL3_WRITE_ADDR_LSB _u(0)

◆ DMA_CH0_AL3_WRITE_ADDR_MSB

#define DMA_CH0_AL3_WRITE_ADDR_MSB _u(31)

◆ DMA_CH0_AL3_WRITE_ADDR_OFFSET

#define DMA_CH0_AL3_WRITE_ADDR_OFFSET _u(0x00000034)

◆ DMA_CH0_AL3_WRITE_ADDR_RESET

#define DMA_CH0_AL3_WRITE_ADDR_RESET "-"

◆ DMA_CH0_CTRL_TRIG_AHB_ERROR_ACCESS

#define DMA_CH0_CTRL_TRIG_AHB_ERROR_ACCESS "RO"

◆ DMA_CH0_CTRL_TRIG_AHB_ERROR_BITS

#define DMA_CH0_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000)

◆ DMA_CH0_CTRL_TRIG_AHB_ERROR_LSB

#define DMA_CH0_CTRL_TRIG_AHB_ERROR_LSB _u(31)

◆ DMA_CH0_CTRL_TRIG_AHB_ERROR_MSB

#define DMA_CH0_CTRL_TRIG_AHB_ERROR_MSB _u(31)

◆ DMA_CH0_CTRL_TRIG_AHB_ERROR_RESET

#define DMA_CH0_CTRL_TRIG_AHB_ERROR_RESET _u(0x0)

◆ DMA_CH0_CTRL_TRIG_BITS

#define DMA_CH0_CTRL_TRIG_BITS _u(0xe7ffffff)

◆ DMA_CH0_CTRL_TRIG_BSWAP_ACCESS

#define DMA_CH0_CTRL_TRIG_BSWAP_ACCESS "RW"

◆ DMA_CH0_CTRL_TRIG_BSWAP_BITS

#define DMA_CH0_CTRL_TRIG_BSWAP_BITS _u(0x01000000)

◆ DMA_CH0_CTRL_TRIG_BSWAP_LSB

#define DMA_CH0_CTRL_TRIG_BSWAP_LSB _u(24)

◆ DMA_CH0_CTRL_TRIG_BSWAP_MSB

#define DMA_CH0_CTRL_TRIG_BSWAP_MSB _u(24)

◆ DMA_CH0_CTRL_TRIG_BSWAP_RESET

#define DMA_CH0_CTRL_TRIG_BSWAP_RESET _u(0x0)

◆ DMA_CH0_CTRL_TRIG_BUSY_ACCESS

#define DMA_CH0_CTRL_TRIG_BUSY_ACCESS "RO"

◆ DMA_CH0_CTRL_TRIG_BUSY_BITS

#define DMA_CH0_CTRL_TRIG_BUSY_BITS _u(0x04000000)

◆ DMA_CH0_CTRL_TRIG_BUSY_LSB

#define DMA_CH0_CTRL_TRIG_BUSY_LSB _u(26)

◆ DMA_CH0_CTRL_TRIG_BUSY_MSB

#define DMA_CH0_CTRL_TRIG_BUSY_MSB _u(26)

◆ DMA_CH0_CTRL_TRIG_BUSY_RESET

#define DMA_CH0_CTRL_TRIG_BUSY_RESET _u(0x0)

◆ DMA_CH0_CTRL_TRIG_CHAIN_TO_ACCESS

#define DMA_CH0_CTRL_TRIG_CHAIN_TO_ACCESS "RW"

◆ DMA_CH0_CTRL_TRIG_CHAIN_TO_BITS

#define DMA_CH0_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000)

◆ DMA_CH0_CTRL_TRIG_CHAIN_TO_LSB

#define DMA_CH0_CTRL_TRIG_CHAIN_TO_LSB _u(13)

◆ DMA_CH0_CTRL_TRIG_CHAIN_TO_MSB

#define DMA_CH0_CTRL_TRIG_CHAIN_TO_MSB _u(16)

◆ DMA_CH0_CTRL_TRIG_CHAIN_TO_RESET

#define DMA_CH0_CTRL_TRIG_CHAIN_TO_RESET _u(0x0)

◆ DMA_CH0_CTRL_TRIG_DATA_SIZE_ACCESS

#define DMA_CH0_CTRL_TRIG_DATA_SIZE_ACCESS "RW"

◆ DMA_CH0_CTRL_TRIG_DATA_SIZE_BITS

#define DMA_CH0_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c)

◆ DMA_CH0_CTRL_TRIG_DATA_SIZE_LSB

#define DMA_CH0_CTRL_TRIG_DATA_SIZE_LSB _u(2)

◆ DMA_CH0_CTRL_TRIG_DATA_SIZE_MSB

#define DMA_CH0_CTRL_TRIG_DATA_SIZE_MSB _u(3)

◆ DMA_CH0_CTRL_TRIG_DATA_SIZE_RESET

#define DMA_CH0_CTRL_TRIG_DATA_SIZE_RESET _u(0x0)

◆ DMA_CH0_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE

#define DMA_CH0_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0)

◆ DMA_CH0_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD

#define DMA_CH0_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1)

◆ DMA_CH0_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD

#define DMA_CH0_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2)

◆ DMA_CH0_CTRL_TRIG_EN_ACCESS

#define DMA_CH0_CTRL_TRIG_EN_ACCESS "RW"

◆ DMA_CH0_CTRL_TRIG_EN_BITS

#define DMA_CH0_CTRL_TRIG_EN_BITS _u(0x00000001)

◆ DMA_CH0_CTRL_TRIG_EN_LSB

#define DMA_CH0_CTRL_TRIG_EN_LSB _u(0)

◆ DMA_CH0_CTRL_TRIG_EN_MSB

#define DMA_CH0_CTRL_TRIG_EN_MSB _u(0)

◆ DMA_CH0_CTRL_TRIG_EN_RESET

#define DMA_CH0_CTRL_TRIG_EN_RESET _u(0x0)

◆ DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_ACCESS

#define DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW"

◆ DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_BITS

#define DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002)

◆ DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_LSB

#define DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1)

◆ DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_MSB

#define DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1)

◆ DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_RESET

#define DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0)

◆ DMA_CH0_CTRL_TRIG_INCR_READ_ACCESS

#define DMA_CH0_CTRL_TRIG_INCR_READ_ACCESS "RW"

◆ DMA_CH0_CTRL_TRIG_INCR_READ_BITS

#define DMA_CH0_CTRL_TRIG_INCR_READ_BITS _u(0x00000010)

◆ DMA_CH0_CTRL_TRIG_INCR_READ_LSB

#define DMA_CH0_CTRL_TRIG_INCR_READ_LSB _u(4)

◆ DMA_CH0_CTRL_TRIG_INCR_READ_MSB

#define DMA_CH0_CTRL_TRIG_INCR_READ_MSB _u(4)

◆ DMA_CH0_CTRL_TRIG_INCR_READ_RESET

#define DMA_CH0_CTRL_TRIG_INCR_READ_RESET _u(0x0)

◆ DMA_CH0_CTRL_TRIG_INCR_READ_REV_ACCESS

#define DMA_CH0_CTRL_TRIG_INCR_READ_REV_ACCESS "RW"

◆ DMA_CH0_CTRL_TRIG_INCR_READ_REV_BITS

#define DMA_CH0_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020)

◆ DMA_CH0_CTRL_TRIG_INCR_READ_REV_LSB

#define DMA_CH0_CTRL_TRIG_INCR_READ_REV_LSB _u(5)

◆ DMA_CH0_CTRL_TRIG_INCR_READ_REV_MSB

#define DMA_CH0_CTRL_TRIG_INCR_READ_REV_MSB _u(5)

◆ DMA_CH0_CTRL_TRIG_INCR_READ_REV_RESET

#define DMA_CH0_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0)

◆ DMA_CH0_CTRL_TRIG_INCR_WRITE_ACCESS

#define DMA_CH0_CTRL_TRIG_INCR_WRITE_ACCESS "RW"

◆ DMA_CH0_CTRL_TRIG_INCR_WRITE_BITS

#define DMA_CH0_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040)

◆ DMA_CH0_CTRL_TRIG_INCR_WRITE_LSB

#define DMA_CH0_CTRL_TRIG_INCR_WRITE_LSB _u(6)

◆ DMA_CH0_CTRL_TRIG_INCR_WRITE_MSB

#define DMA_CH0_CTRL_TRIG_INCR_WRITE_MSB _u(6)

◆ DMA_CH0_CTRL_TRIG_INCR_WRITE_RESET

#define DMA_CH0_CTRL_TRIG_INCR_WRITE_RESET _u(0x0)

◆ DMA_CH0_CTRL_TRIG_INCR_WRITE_REV_ACCESS

#define DMA_CH0_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW"

◆ DMA_CH0_CTRL_TRIG_INCR_WRITE_REV_BITS

#define DMA_CH0_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080)

◆ DMA_CH0_CTRL_TRIG_INCR_WRITE_REV_LSB

#define DMA_CH0_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7)

◆ DMA_CH0_CTRL_TRIG_INCR_WRITE_REV_MSB

#define DMA_CH0_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7)

◆ DMA_CH0_CTRL_TRIG_INCR_WRITE_REV_RESET

#define DMA_CH0_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0)

◆ DMA_CH0_CTRL_TRIG_IRQ_QUIET_ACCESS

#define DMA_CH0_CTRL_TRIG_IRQ_QUIET_ACCESS "RW"

◆ DMA_CH0_CTRL_TRIG_IRQ_QUIET_BITS

#define DMA_CH0_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000)

◆ DMA_CH0_CTRL_TRIG_IRQ_QUIET_LSB

#define DMA_CH0_CTRL_TRIG_IRQ_QUIET_LSB _u(23)

◆ DMA_CH0_CTRL_TRIG_IRQ_QUIET_MSB

#define DMA_CH0_CTRL_TRIG_IRQ_QUIET_MSB _u(23)

◆ DMA_CH0_CTRL_TRIG_IRQ_QUIET_RESET

#define DMA_CH0_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0)

◆ DMA_CH0_CTRL_TRIG_OFFSET

#define DMA_CH0_CTRL_TRIG_OFFSET _u(0x0000000c)

◆ DMA_CH0_CTRL_TRIG_READ_ERROR_ACCESS

#define DMA_CH0_CTRL_TRIG_READ_ERROR_ACCESS "WC"

◆ DMA_CH0_CTRL_TRIG_READ_ERROR_BITS

#define DMA_CH0_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000)

◆ DMA_CH0_CTRL_TRIG_READ_ERROR_LSB

#define DMA_CH0_CTRL_TRIG_READ_ERROR_LSB _u(30)

◆ DMA_CH0_CTRL_TRIG_READ_ERROR_MSB

#define DMA_CH0_CTRL_TRIG_READ_ERROR_MSB _u(30)

◆ DMA_CH0_CTRL_TRIG_READ_ERROR_RESET

#define DMA_CH0_CTRL_TRIG_READ_ERROR_RESET _u(0x0)

◆ DMA_CH0_CTRL_TRIG_RESET

#define DMA_CH0_CTRL_TRIG_RESET _u(0x00000000)

◆ DMA_CH0_CTRL_TRIG_RING_SEL_ACCESS

#define DMA_CH0_CTRL_TRIG_RING_SEL_ACCESS "RW"

◆ DMA_CH0_CTRL_TRIG_RING_SEL_BITS

#define DMA_CH0_CTRL_TRIG_RING_SEL_BITS _u(0x00001000)

◆ DMA_CH0_CTRL_TRIG_RING_SEL_LSB

#define DMA_CH0_CTRL_TRIG_RING_SEL_LSB _u(12)

◆ DMA_CH0_CTRL_TRIG_RING_SEL_MSB

#define DMA_CH0_CTRL_TRIG_RING_SEL_MSB _u(12)

◆ DMA_CH0_CTRL_TRIG_RING_SEL_RESET

#define DMA_CH0_CTRL_TRIG_RING_SEL_RESET _u(0x0)

◆ DMA_CH0_CTRL_TRIG_RING_SIZE_ACCESS

#define DMA_CH0_CTRL_TRIG_RING_SIZE_ACCESS "RW"

◆ DMA_CH0_CTRL_TRIG_RING_SIZE_BITS

#define DMA_CH0_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00)

◆ DMA_CH0_CTRL_TRIG_RING_SIZE_LSB

#define DMA_CH0_CTRL_TRIG_RING_SIZE_LSB _u(8)

◆ DMA_CH0_CTRL_TRIG_RING_SIZE_MSB

#define DMA_CH0_CTRL_TRIG_RING_SIZE_MSB _u(11)

◆ DMA_CH0_CTRL_TRIG_RING_SIZE_RESET

#define DMA_CH0_CTRL_TRIG_RING_SIZE_RESET _u(0x0)

◆ DMA_CH0_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE

#define DMA_CH0_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0)

◆ DMA_CH0_CTRL_TRIG_SNIFF_EN_ACCESS

#define DMA_CH0_CTRL_TRIG_SNIFF_EN_ACCESS "RW"

◆ DMA_CH0_CTRL_TRIG_SNIFF_EN_BITS

#define DMA_CH0_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000)

◆ DMA_CH0_CTRL_TRIG_SNIFF_EN_LSB

#define DMA_CH0_CTRL_TRIG_SNIFF_EN_LSB _u(25)

◆ DMA_CH0_CTRL_TRIG_SNIFF_EN_MSB

#define DMA_CH0_CTRL_TRIG_SNIFF_EN_MSB _u(25)

◆ DMA_CH0_CTRL_TRIG_SNIFF_EN_RESET

#define DMA_CH0_CTRL_TRIG_SNIFF_EN_RESET _u(0x0)

◆ DMA_CH0_CTRL_TRIG_TREQ_SEL_ACCESS

#define DMA_CH0_CTRL_TRIG_TREQ_SEL_ACCESS "RW"

◆ DMA_CH0_CTRL_TRIG_TREQ_SEL_BITS

#define DMA_CH0_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000)

◆ DMA_CH0_CTRL_TRIG_TREQ_SEL_LSB

#define DMA_CH0_CTRL_TRIG_TREQ_SEL_LSB _u(17)

◆ DMA_CH0_CTRL_TRIG_TREQ_SEL_MSB

#define DMA_CH0_CTRL_TRIG_TREQ_SEL_MSB _u(22)

◆ DMA_CH0_CTRL_TRIG_TREQ_SEL_RESET

#define DMA_CH0_CTRL_TRIG_TREQ_SEL_RESET _u(0x00)

◆ DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT

#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f)

◆ DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0

#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b)

◆ DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1

#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c)

◆ DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2

#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d)

◆ DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3

#define DMA_CH0_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e)

◆ DMA_CH0_CTRL_TRIG_WRITE_ERROR_ACCESS

#define DMA_CH0_CTRL_TRIG_WRITE_ERROR_ACCESS "WC"

◆ DMA_CH0_CTRL_TRIG_WRITE_ERROR_BITS

#define DMA_CH0_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000)

◆ DMA_CH0_CTRL_TRIG_WRITE_ERROR_LSB

#define DMA_CH0_CTRL_TRIG_WRITE_ERROR_LSB _u(29)

◆ DMA_CH0_CTRL_TRIG_WRITE_ERROR_MSB

#define DMA_CH0_CTRL_TRIG_WRITE_ERROR_MSB _u(29)

◆ DMA_CH0_CTRL_TRIG_WRITE_ERROR_RESET

#define DMA_CH0_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0)

◆ DMA_CH0_DBG_CTDREQ_ACCESS

#define DMA_CH0_DBG_CTDREQ_ACCESS "WC"

◆ DMA_CH0_DBG_CTDREQ_BITS

#define DMA_CH0_DBG_CTDREQ_BITS _u(0x0000003f)

◆ DMA_CH0_DBG_CTDREQ_LSB

#define DMA_CH0_DBG_CTDREQ_LSB _u(0)

◆ DMA_CH0_DBG_CTDREQ_MSB

#define DMA_CH0_DBG_CTDREQ_MSB _u(5)

◆ DMA_CH0_DBG_CTDREQ_OFFSET

#define DMA_CH0_DBG_CTDREQ_OFFSET _u(0x00000800)

◆ DMA_CH0_DBG_CTDREQ_RESET

#define DMA_CH0_DBG_CTDREQ_RESET _u(0x00000000)

◆ DMA_CH0_DBG_TCR_ACCESS

#define DMA_CH0_DBG_TCR_ACCESS "RO"

◆ DMA_CH0_DBG_TCR_BITS

#define DMA_CH0_DBG_TCR_BITS _u(0xffffffff)

◆ DMA_CH0_DBG_TCR_LSB

#define DMA_CH0_DBG_TCR_LSB _u(0)

◆ DMA_CH0_DBG_TCR_MSB

#define DMA_CH0_DBG_TCR_MSB _u(31)

◆ DMA_CH0_DBG_TCR_OFFSET

#define DMA_CH0_DBG_TCR_OFFSET _u(0x00000804)

◆ DMA_CH0_DBG_TCR_RESET

#define DMA_CH0_DBG_TCR_RESET _u(0x00000000)

◆ DMA_CH0_READ_ADDR_ACCESS

#define DMA_CH0_READ_ADDR_ACCESS "RW"

◆ DMA_CH0_READ_ADDR_BITS

#define DMA_CH0_READ_ADDR_BITS _u(0xffffffff)

◆ DMA_CH0_READ_ADDR_LSB

#define DMA_CH0_READ_ADDR_LSB _u(0)

◆ DMA_CH0_READ_ADDR_MSB

#define DMA_CH0_READ_ADDR_MSB _u(31)

◆ DMA_CH0_READ_ADDR_OFFSET

#define DMA_CH0_READ_ADDR_OFFSET _u(0x00000000)

SPDX-License-Identifier: BSD-3-Clause

◆ DMA_CH0_READ_ADDR_RESET

#define DMA_CH0_READ_ADDR_RESET _u(0x00000000)

◆ DMA_CH0_TRANS_COUNT_BITS

#define DMA_CH0_TRANS_COUNT_BITS _u(0xffffffff)

◆ DMA_CH0_TRANS_COUNT_COUNT_ACCESS

#define DMA_CH0_TRANS_COUNT_COUNT_ACCESS "RW"

◆ DMA_CH0_TRANS_COUNT_COUNT_BITS

#define DMA_CH0_TRANS_COUNT_COUNT_BITS _u(0x0fffffff)

◆ DMA_CH0_TRANS_COUNT_COUNT_LSB

#define DMA_CH0_TRANS_COUNT_COUNT_LSB _u(0)

◆ DMA_CH0_TRANS_COUNT_COUNT_MSB

#define DMA_CH0_TRANS_COUNT_COUNT_MSB _u(27)

◆ DMA_CH0_TRANS_COUNT_COUNT_RESET

#define DMA_CH0_TRANS_COUNT_COUNT_RESET _u(0x0000000)

◆ DMA_CH0_TRANS_COUNT_MODE_ACCESS

#define DMA_CH0_TRANS_COUNT_MODE_ACCESS "RW"

◆ DMA_CH0_TRANS_COUNT_MODE_BITS

#define DMA_CH0_TRANS_COUNT_MODE_BITS _u(0xf0000000)

◆ DMA_CH0_TRANS_COUNT_MODE_LSB

#define DMA_CH0_TRANS_COUNT_MODE_LSB _u(28)

◆ DMA_CH0_TRANS_COUNT_MODE_MSB

#define DMA_CH0_TRANS_COUNT_MODE_MSB _u(31)

◆ DMA_CH0_TRANS_COUNT_MODE_RESET

#define DMA_CH0_TRANS_COUNT_MODE_RESET _u(0x0)

◆ DMA_CH0_TRANS_COUNT_MODE_VALUE_ENDLESS

#define DMA_CH0_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf)

◆ DMA_CH0_TRANS_COUNT_MODE_VALUE_NORMAL

#define DMA_CH0_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0)

◆ DMA_CH0_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF

#define DMA_CH0_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1)

◆ DMA_CH0_TRANS_COUNT_OFFSET

#define DMA_CH0_TRANS_COUNT_OFFSET _u(0x00000008)

◆ DMA_CH0_TRANS_COUNT_RESET

#define DMA_CH0_TRANS_COUNT_RESET _u(0x00000000)

◆ DMA_CH0_WRITE_ADDR_ACCESS

#define DMA_CH0_WRITE_ADDR_ACCESS "RW"

◆ DMA_CH0_WRITE_ADDR_BITS

#define DMA_CH0_WRITE_ADDR_BITS _u(0xffffffff)

◆ DMA_CH0_WRITE_ADDR_LSB

#define DMA_CH0_WRITE_ADDR_LSB _u(0)

◆ DMA_CH0_WRITE_ADDR_MSB

#define DMA_CH0_WRITE_ADDR_MSB _u(31)

◆ DMA_CH0_WRITE_ADDR_OFFSET

#define DMA_CH0_WRITE_ADDR_OFFSET _u(0x00000004)

◆ DMA_CH0_WRITE_ADDR_RESET

#define DMA_CH0_WRITE_ADDR_RESET _u(0x00000000)

◆ DMA_CH10_AL1_CTRL_ACCESS

#define DMA_CH10_AL1_CTRL_ACCESS "RW"

◆ DMA_CH10_AL1_CTRL_BITS

#define DMA_CH10_AL1_CTRL_BITS _u(0xffffffff)

◆ DMA_CH10_AL1_CTRL_LSB

#define DMA_CH10_AL1_CTRL_LSB _u(0)

◆ DMA_CH10_AL1_CTRL_MSB

#define DMA_CH10_AL1_CTRL_MSB _u(31)

◆ DMA_CH10_AL1_CTRL_OFFSET

#define DMA_CH10_AL1_CTRL_OFFSET _u(0x00000290)

◆ DMA_CH10_AL1_CTRL_RESET

#define DMA_CH10_AL1_CTRL_RESET "-"

◆ DMA_CH10_AL1_READ_ADDR_ACCESS

#define DMA_CH10_AL1_READ_ADDR_ACCESS "RW"

◆ DMA_CH10_AL1_READ_ADDR_BITS

#define DMA_CH10_AL1_READ_ADDR_BITS _u(0xffffffff)

◆ DMA_CH10_AL1_READ_ADDR_LSB

#define DMA_CH10_AL1_READ_ADDR_LSB _u(0)

◆ DMA_CH10_AL1_READ_ADDR_MSB

#define DMA_CH10_AL1_READ_ADDR_MSB _u(31)

◆ DMA_CH10_AL1_READ_ADDR_OFFSET

#define DMA_CH10_AL1_READ_ADDR_OFFSET _u(0x00000294)

◆ DMA_CH10_AL1_READ_ADDR_RESET

#define DMA_CH10_AL1_READ_ADDR_RESET "-"

◆ DMA_CH10_AL1_TRANS_COUNT_TRIG_ACCESS

#define DMA_CH10_AL1_TRANS_COUNT_TRIG_ACCESS "RW"

◆ DMA_CH10_AL1_TRANS_COUNT_TRIG_BITS

#define DMA_CH10_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff)

◆ DMA_CH10_AL1_TRANS_COUNT_TRIG_LSB

#define DMA_CH10_AL1_TRANS_COUNT_TRIG_LSB _u(0)

◆ DMA_CH10_AL1_TRANS_COUNT_TRIG_MSB

#define DMA_CH10_AL1_TRANS_COUNT_TRIG_MSB _u(31)

◆ DMA_CH10_AL1_TRANS_COUNT_TRIG_OFFSET

#define DMA_CH10_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000029c)

◆ DMA_CH10_AL1_TRANS_COUNT_TRIG_RESET

#define DMA_CH10_AL1_TRANS_COUNT_TRIG_RESET "-"

◆ DMA_CH10_AL1_WRITE_ADDR_ACCESS

#define DMA_CH10_AL1_WRITE_ADDR_ACCESS "RW"

◆ DMA_CH10_AL1_WRITE_ADDR_BITS

#define DMA_CH10_AL1_WRITE_ADDR_BITS _u(0xffffffff)

◆ DMA_CH10_AL1_WRITE_ADDR_LSB

#define DMA_CH10_AL1_WRITE_ADDR_LSB _u(0)

◆ DMA_CH10_AL1_WRITE_ADDR_MSB

#define DMA_CH10_AL1_WRITE_ADDR_MSB _u(31)

◆ DMA_CH10_AL1_WRITE_ADDR_OFFSET

#define DMA_CH10_AL1_WRITE_ADDR_OFFSET _u(0x00000298)

◆ DMA_CH10_AL1_WRITE_ADDR_RESET

#define DMA_CH10_AL1_WRITE_ADDR_RESET "-"

◆ DMA_CH10_AL2_CTRL_ACCESS

#define DMA_CH10_AL2_CTRL_ACCESS "RW"

◆ DMA_CH10_AL2_CTRL_BITS

#define DMA_CH10_AL2_CTRL_BITS _u(0xffffffff)

◆ DMA_CH10_AL2_CTRL_LSB

#define DMA_CH10_AL2_CTRL_LSB _u(0)

◆ DMA_CH10_AL2_CTRL_MSB

#define DMA_CH10_AL2_CTRL_MSB _u(31)

◆ DMA_CH10_AL2_CTRL_OFFSET

#define DMA_CH10_AL2_CTRL_OFFSET _u(0x000002a0)

◆ DMA_CH10_AL2_CTRL_RESET

#define DMA_CH10_AL2_CTRL_RESET "-"

◆ DMA_CH10_AL2_READ_ADDR_ACCESS

#define DMA_CH10_AL2_READ_ADDR_ACCESS "RW"

◆ DMA_CH10_AL2_READ_ADDR_BITS

#define DMA_CH10_AL2_READ_ADDR_BITS _u(0xffffffff)

◆ DMA_CH10_AL2_READ_ADDR_LSB

#define DMA_CH10_AL2_READ_ADDR_LSB _u(0)

◆ DMA_CH10_AL2_READ_ADDR_MSB

#define DMA_CH10_AL2_READ_ADDR_MSB _u(31)

◆ DMA_CH10_AL2_READ_ADDR_OFFSET

#define DMA_CH10_AL2_READ_ADDR_OFFSET _u(0x000002a8)

◆ DMA_CH10_AL2_READ_ADDR_RESET

#define DMA_CH10_AL2_READ_ADDR_RESET "-"

◆ DMA_CH10_AL2_TRANS_COUNT_ACCESS

#define DMA_CH10_AL2_TRANS_COUNT_ACCESS "RW"

◆ DMA_CH10_AL2_TRANS_COUNT_BITS

#define DMA_CH10_AL2_TRANS_COUNT_BITS _u(0xffffffff)

◆ DMA_CH10_AL2_TRANS_COUNT_LSB

#define DMA_CH10_AL2_TRANS_COUNT_LSB _u(0)

◆ DMA_CH10_AL2_TRANS_COUNT_MSB

#define DMA_CH10_AL2_TRANS_COUNT_MSB _u(31)

◆ DMA_CH10_AL2_TRANS_COUNT_OFFSET

#define DMA_CH10_AL2_TRANS_COUNT_OFFSET _u(0x000002a4)

◆ DMA_CH10_AL2_TRANS_COUNT_RESET

#define DMA_CH10_AL2_TRANS_COUNT_RESET "-"

◆ DMA_CH10_AL2_WRITE_ADDR_TRIG_ACCESS

#define DMA_CH10_AL2_WRITE_ADDR_TRIG_ACCESS "RW"

◆ DMA_CH10_AL2_WRITE_ADDR_TRIG_BITS

#define DMA_CH10_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff)

◆ DMA_CH10_AL2_WRITE_ADDR_TRIG_LSB

#define DMA_CH10_AL2_WRITE_ADDR_TRIG_LSB _u(0)

◆ DMA_CH10_AL2_WRITE_ADDR_TRIG_MSB

#define DMA_CH10_AL2_WRITE_ADDR_TRIG_MSB _u(31)

◆ DMA_CH10_AL2_WRITE_ADDR_TRIG_OFFSET

#define DMA_CH10_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x000002ac)

◆ DMA_CH10_AL2_WRITE_ADDR_TRIG_RESET

#define DMA_CH10_AL2_WRITE_ADDR_TRIG_RESET "-"

◆ DMA_CH10_AL3_CTRL_ACCESS

#define DMA_CH10_AL3_CTRL_ACCESS "RW"

◆ DMA_CH10_AL3_CTRL_BITS

#define DMA_CH10_AL3_CTRL_BITS _u(0xffffffff)

◆ DMA_CH10_AL3_CTRL_LSB

#define DMA_CH10_AL3_CTRL_LSB _u(0)

◆ DMA_CH10_AL3_CTRL_MSB

#define DMA_CH10_AL3_CTRL_MSB _u(31)

◆ DMA_CH10_AL3_CTRL_OFFSET

#define DMA_CH10_AL3_CTRL_OFFSET _u(0x000002b0)

◆ DMA_CH10_AL3_CTRL_RESET

#define DMA_CH10_AL3_CTRL_RESET "-"

◆ DMA_CH10_AL3_READ_ADDR_TRIG_ACCESS

#define DMA_CH10_AL3_READ_ADDR_TRIG_ACCESS "RW"

◆ DMA_CH10_AL3_READ_ADDR_TRIG_BITS

#define DMA_CH10_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff)

◆ DMA_CH10_AL3_READ_ADDR_TRIG_LSB

#define DMA_CH10_AL3_READ_ADDR_TRIG_LSB _u(0)

◆ DMA_CH10_AL3_READ_ADDR_TRIG_MSB

#define DMA_CH10_AL3_READ_ADDR_TRIG_MSB _u(31)

◆ DMA_CH10_AL3_READ_ADDR_TRIG_OFFSET

#define DMA_CH10_AL3_READ_ADDR_TRIG_OFFSET _u(0x000002bc)

◆ DMA_CH10_AL3_READ_ADDR_TRIG_RESET

#define DMA_CH10_AL3_READ_ADDR_TRIG_RESET "-"

◆ DMA_CH10_AL3_TRANS_COUNT_ACCESS

#define DMA_CH10_AL3_TRANS_COUNT_ACCESS "RW"

◆ DMA_CH10_AL3_TRANS_COUNT_BITS

#define DMA_CH10_AL3_TRANS_COUNT_BITS _u(0xffffffff)

◆ DMA_CH10_AL3_TRANS_COUNT_LSB

#define DMA_CH10_AL3_TRANS_COUNT_LSB _u(0)

◆ DMA_CH10_AL3_TRANS_COUNT_MSB

#define DMA_CH10_AL3_TRANS_COUNT_MSB _u(31)

◆ DMA_CH10_AL3_TRANS_COUNT_OFFSET

#define DMA_CH10_AL3_TRANS_COUNT_OFFSET _u(0x000002b8)

◆ DMA_CH10_AL3_TRANS_COUNT_RESET

#define DMA_CH10_AL3_TRANS_COUNT_RESET "-"

◆ DMA_CH10_AL3_WRITE_ADDR_ACCESS

#define DMA_CH10_AL3_WRITE_ADDR_ACCESS "RW"

◆ DMA_CH10_AL3_WRITE_ADDR_BITS

#define DMA_CH10_AL3_WRITE_ADDR_BITS _u(0xffffffff)

◆ DMA_CH10_AL3_WRITE_ADDR_LSB

#define DMA_CH10_AL3_WRITE_ADDR_LSB _u(0)

◆ DMA_CH10_AL3_WRITE_ADDR_MSB

#define DMA_CH10_AL3_WRITE_ADDR_MSB _u(31)

◆ DMA_CH10_AL3_WRITE_ADDR_OFFSET

#define DMA_CH10_AL3_WRITE_ADDR_OFFSET _u(0x000002b4)

◆ DMA_CH10_AL3_WRITE_ADDR_RESET

#define DMA_CH10_AL3_WRITE_ADDR_RESET "-"

◆ DMA_CH10_CTRL_TRIG_AHB_ERROR_ACCESS

#define DMA_CH10_CTRL_TRIG_AHB_ERROR_ACCESS "RO"

◆ DMA_CH10_CTRL_TRIG_AHB_ERROR_BITS

#define DMA_CH10_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000)

◆ DMA_CH10_CTRL_TRIG_AHB_ERROR_LSB

#define DMA_CH10_CTRL_TRIG_AHB_ERROR_LSB _u(31)

◆ DMA_CH10_CTRL_TRIG_AHB_ERROR_MSB

#define DMA_CH10_CTRL_TRIG_AHB_ERROR_MSB _u(31)

◆ DMA_CH10_CTRL_TRIG_AHB_ERROR_RESET

#define DMA_CH10_CTRL_TRIG_AHB_ERROR_RESET _u(0x0)

◆ DMA_CH10_CTRL_TRIG_BITS

#define DMA_CH10_CTRL_TRIG_BITS _u(0xe7ffffff)

◆ DMA_CH10_CTRL_TRIG_BSWAP_ACCESS

#define DMA_CH10_CTRL_TRIG_BSWAP_ACCESS "RW"

◆ DMA_CH10_CTRL_TRIG_BSWAP_BITS

#define DMA_CH10_CTRL_TRIG_BSWAP_BITS _u(0x01000000)

◆ DMA_CH10_CTRL_TRIG_BSWAP_LSB

#define DMA_CH10_CTRL_TRIG_BSWAP_LSB _u(24)

◆ DMA_CH10_CTRL_TRIG_BSWAP_MSB

#define DMA_CH10_CTRL_TRIG_BSWAP_MSB _u(24)

◆ DMA_CH10_CTRL_TRIG_BSWAP_RESET

#define DMA_CH10_CTRL_TRIG_BSWAP_RESET _u(0x0)

◆ DMA_CH10_CTRL_TRIG_BUSY_ACCESS

#define DMA_CH10_CTRL_TRIG_BUSY_ACCESS "RO"

◆ DMA_CH10_CTRL_TRIG_BUSY_BITS

#define DMA_CH10_CTRL_TRIG_BUSY_BITS _u(0x04000000)

◆ DMA_CH10_CTRL_TRIG_BUSY_LSB

#define DMA_CH10_CTRL_TRIG_BUSY_LSB _u(26)

◆ DMA_CH10_CTRL_TRIG_BUSY_MSB

#define DMA_CH10_CTRL_TRIG_BUSY_MSB _u(26)

◆ DMA_CH10_CTRL_TRIG_BUSY_RESET

#define DMA_CH10_CTRL_TRIG_BUSY_RESET _u(0x0)

◆ DMA_CH10_CTRL_TRIG_CHAIN_TO_ACCESS

#define DMA_CH10_CTRL_TRIG_CHAIN_TO_ACCESS "RW"

◆ DMA_CH10_CTRL_TRIG_CHAIN_TO_BITS

#define DMA_CH10_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000)

◆ DMA_CH10_CTRL_TRIG_CHAIN_TO_LSB

#define DMA_CH10_CTRL_TRIG_CHAIN_TO_LSB _u(13)

◆ DMA_CH10_CTRL_TRIG_CHAIN_TO_MSB

#define DMA_CH10_CTRL_TRIG_CHAIN_TO_MSB _u(16)

◆ DMA_CH10_CTRL_TRIG_CHAIN_TO_RESET

#define DMA_CH10_CTRL_TRIG_CHAIN_TO_RESET _u(0x0)

◆ DMA_CH10_CTRL_TRIG_DATA_SIZE_ACCESS

#define DMA_CH10_CTRL_TRIG_DATA_SIZE_ACCESS "RW"

◆ DMA_CH10_CTRL_TRIG_DATA_SIZE_BITS

#define DMA_CH10_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c)

◆ DMA_CH10_CTRL_TRIG_DATA_SIZE_LSB

#define DMA_CH10_CTRL_TRIG_DATA_SIZE_LSB _u(2)

◆ DMA_CH10_CTRL_TRIG_DATA_SIZE_MSB

#define DMA_CH10_CTRL_TRIG_DATA_SIZE_MSB _u(3)

◆ DMA_CH10_CTRL_TRIG_DATA_SIZE_RESET

#define DMA_CH10_CTRL_TRIG_DATA_SIZE_RESET _u(0x0)

◆ DMA_CH10_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE

#define DMA_CH10_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0)

◆ DMA_CH10_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD

#define DMA_CH10_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1)

◆ DMA_CH10_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD

#define DMA_CH10_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2)

◆ DMA_CH10_CTRL_TRIG_EN_ACCESS

#define DMA_CH10_CTRL_TRIG_EN_ACCESS "RW"

◆ DMA_CH10_CTRL_TRIG_EN_BITS

#define DMA_CH10_CTRL_TRIG_EN_BITS _u(0x00000001)

◆ DMA_CH10_CTRL_TRIG_EN_LSB

#define DMA_CH10_CTRL_TRIG_EN_LSB _u(0)

◆ DMA_CH10_CTRL_TRIG_EN_MSB

#define DMA_CH10_CTRL_TRIG_EN_MSB _u(0)

◆ DMA_CH10_CTRL_TRIG_EN_RESET

#define DMA_CH10_CTRL_TRIG_EN_RESET _u(0x0)

◆ DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_ACCESS

#define DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW"

◆ DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_BITS

#define DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002)

◆ DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_LSB

#define DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1)

◆ DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_MSB

#define DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1)

◆ DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_RESET

#define DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0)

◆ DMA_CH10_CTRL_TRIG_INCR_READ_ACCESS

#define DMA_CH10_CTRL_TRIG_INCR_READ_ACCESS "RW"

◆ DMA_CH10_CTRL_TRIG_INCR_READ_BITS

#define DMA_CH10_CTRL_TRIG_INCR_READ_BITS _u(0x00000010)

◆ DMA_CH10_CTRL_TRIG_INCR_READ_LSB

#define DMA_CH10_CTRL_TRIG_INCR_READ_LSB _u(4)

◆ DMA_CH10_CTRL_TRIG_INCR_READ_MSB

#define DMA_CH10_CTRL_TRIG_INCR_READ_MSB _u(4)

◆ DMA_CH10_CTRL_TRIG_INCR_READ_RESET

#define DMA_CH10_CTRL_TRIG_INCR_READ_RESET _u(0x0)

◆ DMA_CH10_CTRL_TRIG_INCR_READ_REV_ACCESS

#define DMA_CH10_CTRL_TRIG_INCR_READ_REV_ACCESS "RW"

◆ DMA_CH10_CTRL_TRIG_INCR_READ_REV_BITS

#define DMA_CH10_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020)

◆ DMA_CH10_CTRL_TRIG_INCR_READ_REV_LSB

#define DMA_CH10_CTRL_TRIG_INCR_READ_REV_LSB _u(5)

◆ DMA_CH10_CTRL_TRIG_INCR_READ_REV_MSB

#define DMA_CH10_CTRL_TRIG_INCR_READ_REV_MSB _u(5)

◆ DMA_CH10_CTRL_TRIG_INCR_READ_REV_RESET

#define DMA_CH10_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0)

◆ DMA_CH10_CTRL_TRIG_INCR_WRITE_ACCESS

#define DMA_CH10_CTRL_TRIG_INCR_WRITE_ACCESS "RW"

◆ DMA_CH10_CTRL_TRIG_INCR_WRITE_BITS

#define DMA_CH10_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040)

◆ DMA_CH10_CTRL_TRIG_INCR_WRITE_LSB

#define DMA_CH10_CTRL_TRIG_INCR_WRITE_LSB _u(6)

◆ DMA_CH10_CTRL_TRIG_INCR_WRITE_MSB

#define DMA_CH10_CTRL_TRIG_INCR_WRITE_MSB _u(6)

◆ DMA_CH10_CTRL_TRIG_INCR_WRITE_RESET

#define DMA_CH10_CTRL_TRIG_INCR_WRITE_RESET _u(0x0)

◆ DMA_CH10_CTRL_TRIG_INCR_WRITE_REV_ACCESS

#define DMA_CH10_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW"

◆ DMA_CH10_CTRL_TRIG_INCR_WRITE_REV_BITS

#define DMA_CH10_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080)

◆ DMA_CH10_CTRL_TRIG_INCR_WRITE_REV_LSB

#define DMA_CH10_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7)

◆ DMA_CH10_CTRL_TRIG_INCR_WRITE_REV_MSB

#define DMA_CH10_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7)

◆ DMA_CH10_CTRL_TRIG_INCR_WRITE_REV_RESET

#define DMA_CH10_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0)

◆ DMA_CH10_CTRL_TRIG_IRQ_QUIET_ACCESS

#define DMA_CH10_CTRL_TRIG_IRQ_QUIET_ACCESS "RW"

◆ DMA_CH10_CTRL_TRIG_IRQ_QUIET_BITS

#define DMA_CH10_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000)

◆ DMA_CH10_CTRL_TRIG_IRQ_QUIET_LSB

#define DMA_CH10_CTRL_TRIG_IRQ_QUIET_LSB _u(23)

◆ DMA_CH10_CTRL_TRIG_IRQ_QUIET_MSB

#define DMA_CH10_CTRL_TRIG_IRQ_QUIET_MSB _u(23)

◆ DMA_CH10_CTRL_TRIG_IRQ_QUIET_RESET

#define DMA_CH10_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0)

◆ DMA_CH10_CTRL_TRIG_OFFSET

#define DMA_CH10_CTRL_TRIG_OFFSET _u(0x0000028c)

◆ DMA_CH10_CTRL_TRIG_READ_ERROR_ACCESS

#define DMA_CH10_CTRL_TRIG_READ_ERROR_ACCESS "WC"

◆ DMA_CH10_CTRL_TRIG_READ_ERROR_BITS

#define DMA_CH10_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000)

◆ DMA_CH10_CTRL_TRIG_READ_ERROR_LSB

#define DMA_CH10_CTRL_TRIG_READ_ERROR_LSB _u(30)

◆ DMA_CH10_CTRL_TRIG_READ_ERROR_MSB

#define DMA_CH10_CTRL_TRIG_READ_ERROR_MSB _u(30)

◆ DMA_CH10_CTRL_TRIG_READ_ERROR_RESET

#define DMA_CH10_CTRL_TRIG_READ_ERROR_RESET _u(0x0)

◆ DMA_CH10_CTRL_TRIG_RESET

#define DMA_CH10_CTRL_TRIG_RESET _u(0x00000000)

◆ DMA_CH10_CTRL_TRIG_RING_SEL_ACCESS

#define DMA_CH10_CTRL_TRIG_RING_SEL_ACCESS "RW"

◆ DMA_CH10_CTRL_TRIG_RING_SEL_BITS

#define DMA_CH10_CTRL_TRIG_RING_SEL_BITS _u(0x00001000)

◆ DMA_CH10_CTRL_TRIG_RING_SEL_LSB

#define DMA_CH10_CTRL_TRIG_RING_SEL_LSB _u(12)

◆ DMA_CH10_CTRL_TRIG_RING_SEL_MSB

#define DMA_CH10_CTRL_TRIG_RING_SEL_MSB _u(12)

◆ DMA_CH10_CTRL_TRIG_RING_SEL_RESET

#define DMA_CH10_CTRL_TRIG_RING_SEL_RESET _u(0x0)

◆ DMA_CH10_CTRL_TRIG_RING_SIZE_ACCESS

#define DMA_CH10_CTRL_TRIG_RING_SIZE_ACCESS "RW"

◆ DMA_CH10_CTRL_TRIG_RING_SIZE_BITS

#define DMA_CH10_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00)

◆ DMA_CH10_CTRL_TRIG_RING_SIZE_LSB

#define DMA_CH10_CTRL_TRIG_RING_SIZE_LSB _u(8)

◆ DMA_CH10_CTRL_TRIG_RING_SIZE_MSB

#define DMA_CH10_CTRL_TRIG_RING_SIZE_MSB _u(11)

◆ DMA_CH10_CTRL_TRIG_RING_SIZE_RESET

#define DMA_CH10_CTRL_TRIG_RING_SIZE_RESET _u(0x0)

◆ DMA_CH10_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE

#define DMA_CH10_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0)

◆ DMA_CH10_CTRL_TRIG_SNIFF_EN_ACCESS

#define DMA_CH10_CTRL_TRIG_SNIFF_EN_ACCESS "RW"

◆ DMA_CH10_CTRL_TRIG_SNIFF_EN_BITS

#define DMA_CH10_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000)

◆ DMA_CH10_CTRL_TRIG_SNIFF_EN_LSB

#define DMA_CH10_CTRL_TRIG_SNIFF_EN_LSB _u(25)

◆ DMA_CH10_CTRL_TRIG_SNIFF_EN_MSB

#define DMA_CH10_CTRL_TRIG_SNIFF_EN_MSB _u(25)

◆ DMA_CH10_CTRL_TRIG_SNIFF_EN_RESET

#define DMA_CH10_CTRL_TRIG_SNIFF_EN_RESET _u(0x0)

◆ DMA_CH10_CTRL_TRIG_TREQ_SEL_ACCESS

#define DMA_CH10_CTRL_TRIG_TREQ_SEL_ACCESS "RW"

◆ DMA_CH10_CTRL_TRIG_TREQ_SEL_BITS

#define DMA_CH10_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000)

◆ DMA_CH10_CTRL_TRIG_TREQ_SEL_LSB

#define DMA_CH10_CTRL_TRIG_TREQ_SEL_LSB _u(17)

◆ DMA_CH10_CTRL_TRIG_TREQ_SEL_MSB

#define DMA_CH10_CTRL_TRIG_TREQ_SEL_MSB _u(22)

◆ DMA_CH10_CTRL_TRIG_TREQ_SEL_RESET

#define DMA_CH10_CTRL_TRIG_TREQ_SEL_RESET _u(0x00)

◆ DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT

#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f)

◆ DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0

#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b)

◆ DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1

#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c)

◆ DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2

#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d)

◆ DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3

#define DMA_CH10_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e)

◆ DMA_CH10_CTRL_TRIG_WRITE_ERROR_ACCESS

#define DMA_CH10_CTRL_TRIG_WRITE_ERROR_ACCESS "WC"

◆ DMA_CH10_CTRL_TRIG_WRITE_ERROR_BITS

#define DMA_CH10_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000)

◆ DMA_CH10_CTRL_TRIG_WRITE_ERROR_LSB

#define DMA_CH10_CTRL_TRIG_WRITE_ERROR_LSB _u(29)

◆ DMA_CH10_CTRL_TRIG_WRITE_ERROR_MSB

#define DMA_CH10_CTRL_TRIG_WRITE_ERROR_MSB _u(29)

◆ DMA_CH10_CTRL_TRIG_WRITE_ERROR_RESET

#define DMA_CH10_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0)

◆ DMA_CH10_DBG_CTDREQ_ACCESS

#define DMA_CH10_DBG_CTDREQ_ACCESS "WC"

◆ DMA_CH10_DBG_CTDREQ_BITS

#define DMA_CH10_DBG_CTDREQ_BITS _u(0x0000003f)

◆ DMA_CH10_DBG_CTDREQ_LSB

#define DMA_CH10_DBG_CTDREQ_LSB _u(0)

◆ DMA_CH10_DBG_CTDREQ_MSB

#define DMA_CH10_DBG_CTDREQ_MSB _u(5)

◆ DMA_CH10_DBG_CTDREQ_OFFSET

#define DMA_CH10_DBG_CTDREQ_OFFSET _u(0x00000a80)

◆ DMA_CH10_DBG_CTDREQ_RESET

#define DMA_CH10_DBG_CTDREQ_RESET _u(0x00000000)

◆ DMA_CH10_DBG_TCR_ACCESS

#define DMA_CH10_DBG_TCR_ACCESS "RO"

◆ DMA_CH10_DBG_TCR_BITS

#define DMA_CH10_DBG_TCR_BITS _u(0xffffffff)

◆ DMA_CH10_DBG_TCR_LSB

#define DMA_CH10_DBG_TCR_LSB _u(0)

◆ DMA_CH10_DBG_TCR_MSB

#define DMA_CH10_DBG_TCR_MSB _u(31)

◆ DMA_CH10_DBG_TCR_OFFSET

#define DMA_CH10_DBG_TCR_OFFSET _u(0x00000a84)

◆ DMA_CH10_DBG_TCR_RESET

#define DMA_CH10_DBG_TCR_RESET _u(0x00000000)

◆ DMA_CH10_READ_ADDR_ACCESS

#define DMA_CH10_READ_ADDR_ACCESS "RW"

◆ DMA_CH10_READ_ADDR_BITS

#define DMA_CH10_READ_ADDR_BITS _u(0xffffffff)

◆ DMA_CH10_READ_ADDR_LSB

#define DMA_CH10_READ_ADDR_LSB _u(0)

◆ DMA_CH10_READ_ADDR_MSB

#define DMA_CH10_READ_ADDR_MSB _u(31)

◆ DMA_CH10_READ_ADDR_OFFSET

#define DMA_CH10_READ_ADDR_OFFSET _u(0x00000280)

◆ DMA_CH10_READ_ADDR_RESET

#define DMA_CH10_READ_ADDR_RESET _u(0x00000000)

◆ DMA_CH10_TRANS_COUNT_BITS

#define DMA_CH10_TRANS_COUNT_BITS _u(0xffffffff)

◆ DMA_CH10_TRANS_COUNT_COUNT_ACCESS

#define DMA_CH10_TRANS_COUNT_COUNT_ACCESS "RW"

◆ DMA_CH10_TRANS_COUNT_COUNT_BITS

#define DMA_CH10_TRANS_COUNT_COUNT_BITS _u(0x0fffffff)

◆ DMA_CH10_TRANS_COUNT_COUNT_LSB

#define DMA_CH10_TRANS_COUNT_COUNT_LSB _u(0)

◆ DMA_CH10_TRANS_COUNT_COUNT_MSB

#define DMA_CH10_TRANS_COUNT_COUNT_MSB _u(27)

◆ DMA_CH10_TRANS_COUNT_COUNT_RESET

#define DMA_CH10_TRANS_COUNT_COUNT_RESET _u(0x0000000)

◆ DMA_CH10_TRANS_COUNT_MODE_ACCESS

#define DMA_CH10_TRANS_COUNT_MODE_ACCESS "RW"

◆ DMA_CH10_TRANS_COUNT_MODE_BITS

#define DMA_CH10_TRANS_COUNT_MODE_BITS _u(0xf0000000)

◆ DMA_CH10_TRANS_COUNT_MODE_LSB

#define DMA_CH10_TRANS_COUNT_MODE_LSB _u(28)

◆ DMA_CH10_TRANS_COUNT_MODE_MSB

#define DMA_CH10_TRANS_COUNT_MODE_MSB _u(31)

◆ DMA_CH10_TRANS_COUNT_MODE_RESET

#define DMA_CH10_TRANS_COUNT_MODE_RESET _u(0x0)

◆ DMA_CH10_TRANS_COUNT_MODE_VALUE_ENDLESS

#define DMA_CH10_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf)

◆ DMA_CH10_TRANS_COUNT_MODE_VALUE_NORMAL

#define DMA_CH10_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0)

◆ DMA_CH10_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF

#define DMA_CH10_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1)

◆ DMA_CH10_TRANS_COUNT_OFFSET

#define DMA_CH10_TRANS_COUNT_OFFSET _u(0x00000288)

◆ DMA_CH10_TRANS_COUNT_RESET

#define DMA_CH10_TRANS_COUNT_RESET _u(0x00000000)

◆ DMA_CH10_WRITE_ADDR_ACCESS

#define DMA_CH10_WRITE_ADDR_ACCESS "RW"

◆ DMA_CH10_WRITE_ADDR_BITS

#define DMA_CH10_WRITE_ADDR_BITS _u(0xffffffff)

◆ DMA_CH10_WRITE_ADDR_LSB

#define DMA_CH10_WRITE_ADDR_LSB _u(0)

◆ DMA_CH10_WRITE_ADDR_MSB

#define DMA_CH10_WRITE_ADDR_MSB _u(31)

◆ DMA_CH10_WRITE_ADDR_OFFSET

#define DMA_CH10_WRITE_ADDR_OFFSET _u(0x00000284)

◆ DMA_CH10_WRITE_ADDR_RESET

#define DMA_CH10_WRITE_ADDR_RESET _u(0x00000000)

◆ DMA_CH11_AL1_CTRL_ACCESS

#define DMA_CH11_AL1_CTRL_ACCESS "RW"

◆ DMA_CH11_AL1_CTRL_BITS

#define DMA_CH11_AL1_CTRL_BITS _u(0xffffffff)

◆ DMA_CH11_AL1_CTRL_LSB

#define DMA_CH11_AL1_CTRL_LSB _u(0)

◆ DMA_CH11_AL1_CTRL_MSB

#define DMA_CH11_AL1_CTRL_MSB _u(31)

◆ DMA_CH11_AL1_CTRL_OFFSET

#define DMA_CH11_AL1_CTRL_OFFSET _u(0x000002d0)

◆ DMA_CH11_AL1_CTRL_RESET

#define DMA_CH11_AL1_CTRL_RESET "-"

◆ DMA_CH11_AL1_READ_ADDR_ACCESS

#define DMA_CH11_AL1_READ_ADDR_ACCESS "RW"

◆ DMA_CH11_AL1_READ_ADDR_BITS

#define DMA_CH11_AL1_READ_ADDR_BITS _u(0xffffffff)

◆ DMA_CH11_AL1_READ_ADDR_LSB

#define DMA_CH11_AL1_READ_ADDR_LSB _u(0)

◆ DMA_CH11_AL1_READ_ADDR_MSB

#define DMA_CH11_AL1_READ_ADDR_MSB _u(31)

◆ DMA_CH11_AL1_READ_ADDR_OFFSET

#define DMA_CH11_AL1_READ_ADDR_OFFSET _u(0x000002d4)

◆ DMA_CH11_AL1_READ_ADDR_RESET

#define DMA_CH11_AL1_READ_ADDR_RESET "-"

◆ DMA_CH11_AL1_TRANS_COUNT_TRIG_ACCESS

#define DMA_CH11_AL1_TRANS_COUNT_TRIG_ACCESS "RW"

◆ DMA_CH11_AL1_TRANS_COUNT_TRIG_BITS

#define DMA_CH11_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff)

◆ DMA_CH11_AL1_TRANS_COUNT_TRIG_LSB

#define DMA_CH11_AL1_TRANS_COUNT_TRIG_LSB _u(0)

◆ DMA_CH11_AL1_TRANS_COUNT_TRIG_MSB

#define DMA_CH11_AL1_TRANS_COUNT_TRIG_MSB _u(31)

◆ DMA_CH11_AL1_TRANS_COUNT_TRIG_OFFSET

#define DMA_CH11_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x000002dc)

◆ DMA_CH11_AL1_TRANS_COUNT_TRIG_RESET

#define DMA_CH11_AL1_TRANS_COUNT_TRIG_RESET "-"

◆ DMA_CH11_AL1_WRITE_ADDR_ACCESS

#define DMA_CH11_AL1_WRITE_ADDR_ACCESS "RW"

◆ DMA_CH11_AL1_WRITE_ADDR_BITS

#define DMA_CH11_AL1_WRITE_ADDR_BITS _u(0xffffffff)

◆ DMA_CH11_AL1_WRITE_ADDR_LSB

#define DMA_CH11_AL1_WRITE_ADDR_LSB _u(0)

◆ DMA_CH11_AL1_WRITE_ADDR_MSB

#define DMA_CH11_AL1_WRITE_ADDR_MSB _u(31)

◆ DMA_CH11_AL1_WRITE_ADDR_OFFSET

#define DMA_CH11_AL1_WRITE_ADDR_OFFSET _u(0x000002d8)

◆ DMA_CH11_AL1_WRITE_ADDR_RESET

#define DMA_CH11_AL1_WRITE_ADDR_RESET "-"

◆ DMA_CH11_AL2_CTRL_ACCESS

#define DMA_CH11_AL2_CTRL_ACCESS "RW"

◆ DMA_CH11_AL2_CTRL_BITS

#define DMA_CH11_AL2_CTRL_BITS _u(0xffffffff)

◆ DMA_CH11_AL2_CTRL_LSB

#define DMA_CH11_AL2_CTRL_LSB _u(0)

◆ DMA_CH11_AL2_CTRL_MSB

#define DMA_CH11_AL2_CTRL_MSB _u(31)

◆ DMA_CH11_AL2_CTRL_OFFSET

#define DMA_CH11_AL2_CTRL_OFFSET _u(0x000002e0)

◆ DMA_CH11_AL2_CTRL_RESET

#define DMA_CH11_AL2_CTRL_RESET "-"

◆ DMA_CH11_AL2_READ_ADDR_ACCESS

#define DMA_CH11_AL2_READ_ADDR_ACCESS "RW"

◆ DMA_CH11_AL2_READ_ADDR_BITS

#define DMA_CH11_AL2_READ_ADDR_BITS _u(0xffffffff)

◆ DMA_CH11_AL2_READ_ADDR_LSB

#define DMA_CH11_AL2_READ_ADDR_LSB _u(0)

◆ DMA_CH11_AL2_READ_ADDR_MSB

#define DMA_CH11_AL2_READ_ADDR_MSB _u(31)

◆ DMA_CH11_AL2_READ_ADDR_OFFSET

#define DMA_CH11_AL2_READ_ADDR_OFFSET _u(0x000002e8)

◆ DMA_CH11_AL2_READ_ADDR_RESET

#define DMA_CH11_AL2_READ_ADDR_RESET "-"

◆ DMA_CH11_AL2_TRANS_COUNT_ACCESS

#define DMA_CH11_AL2_TRANS_COUNT_ACCESS "RW"

◆ DMA_CH11_AL2_TRANS_COUNT_BITS

#define DMA_CH11_AL2_TRANS_COUNT_BITS _u(0xffffffff)

◆ DMA_CH11_AL2_TRANS_COUNT_LSB

#define DMA_CH11_AL2_TRANS_COUNT_LSB _u(0)

◆ DMA_CH11_AL2_TRANS_COUNT_MSB

#define DMA_CH11_AL2_TRANS_COUNT_MSB _u(31)

◆ DMA_CH11_AL2_TRANS_COUNT_OFFSET

#define DMA_CH11_AL2_TRANS_COUNT_OFFSET _u(0x000002e4)

◆ DMA_CH11_AL2_TRANS_COUNT_RESET

#define DMA_CH11_AL2_TRANS_COUNT_RESET "-"

◆ DMA_CH11_AL2_WRITE_ADDR_TRIG_ACCESS

#define DMA_CH11_AL2_WRITE_ADDR_TRIG_ACCESS "RW"

◆ DMA_CH11_AL2_WRITE_ADDR_TRIG_BITS

#define DMA_CH11_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff)

◆ DMA_CH11_AL2_WRITE_ADDR_TRIG_LSB

#define DMA_CH11_AL2_WRITE_ADDR_TRIG_LSB _u(0)

◆ DMA_CH11_AL2_WRITE_ADDR_TRIG_MSB

#define DMA_CH11_AL2_WRITE_ADDR_TRIG_MSB _u(31)

◆ DMA_CH11_AL2_WRITE_ADDR_TRIG_OFFSET

#define DMA_CH11_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x000002ec)

◆ DMA_CH11_AL2_WRITE_ADDR_TRIG_RESET

#define DMA_CH11_AL2_WRITE_ADDR_TRIG_RESET "-"

◆ DMA_CH11_AL3_CTRL_ACCESS

#define DMA_CH11_AL3_CTRL_ACCESS "RW"

◆ DMA_CH11_AL3_CTRL_BITS

#define DMA_CH11_AL3_CTRL_BITS _u(0xffffffff)

◆ DMA_CH11_AL3_CTRL_LSB

#define DMA_CH11_AL3_CTRL_LSB _u(0)

◆ DMA_CH11_AL3_CTRL_MSB

#define DMA_CH11_AL3_CTRL_MSB _u(31)

◆ DMA_CH11_AL3_CTRL_OFFSET

#define DMA_CH11_AL3_CTRL_OFFSET _u(0x000002f0)

◆ DMA_CH11_AL3_CTRL_RESET

#define DMA_CH11_AL3_CTRL_RESET "-"

◆ DMA_CH11_AL3_READ_ADDR_TRIG_ACCESS

#define DMA_CH11_AL3_READ_ADDR_TRIG_ACCESS "RW"

◆ DMA_CH11_AL3_READ_ADDR_TRIG_BITS

#define DMA_CH11_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff)

◆ DMA_CH11_AL3_READ_ADDR_TRIG_LSB

#define DMA_CH11_AL3_READ_ADDR_TRIG_LSB _u(0)

◆ DMA_CH11_AL3_READ_ADDR_TRIG_MSB

#define DMA_CH11_AL3_READ_ADDR_TRIG_MSB _u(31)

◆ DMA_CH11_AL3_READ_ADDR_TRIG_OFFSET

#define DMA_CH11_AL3_READ_ADDR_TRIG_OFFSET _u(0x000002fc)

◆ DMA_CH11_AL3_READ_ADDR_TRIG_RESET

#define DMA_CH11_AL3_READ_ADDR_TRIG_RESET "-"

◆ DMA_CH11_AL3_TRANS_COUNT_ACCESS

#define DMA_CH11_AL3_TRANS_COUNT_ACCESS "RW"

◆ DMA_CH11_AL3_TRANS_COUNT_BITS

#define DMA_CH11_AL3_TRANS_COUNT_BITS _u(0xffffffff)

◆ DMA_CH11_AL3_TRANS_COUNT_LSB

#define DMA_CH11_AL3_TRANS_COUNT_LSB _u(0)

◆ DMA_CH11_AL3_TRANS_COUNT_MSB

#define DMA_CH11_AL3_TRANS_COUNT_MSB _u(31)

◆ DMA_CH11_AL3_TRANS_COUNT_OFFSET

#define DMA_CH11_AL3_TRANS_COUNT_OFFSET _u(0x000002f8)

◆ DMA_CH11_AL3_TRANS_COUNT_RESET

#define DMA_CH11_AL3_TRANS_COUNT_RESET "-"

◆ DMA_CH11_AL3_WRITE_ADDR_ACCESS

#define DMA_CH11_AL3_WRITE_ADDR_ACCESS "RW"

◆ DMA_CH11_AL3_WRITE_ADDR_BITS

#define DMA_CH11_AL3_WRITE_ADDR_BITS _u(0xffffffff)

◆ DMA_CH11_AL3_WRITE_ADDR_LSB

#define DMA_CH11_AL3_WRITE_ADDR_LSB _u(0)

◆ DMA_CH11_AL3_WRITE_ADDR_MSB

#define DMA_CH11_AL3_WRITE_ADDR_MSB _u(31)

◆ DMA_CH11_AL3_WRITE_ADDR_OFFSET

#define DMA_CH11_AL3_WRITE_ADDR_OFFSET _u(0x000002f4)

◆ DMA_CH11_AL3_WRITE_ADDR_RESET

#define DMA_CH11_AL3_WRITE_ADDR_RESET "-"

◆ DMA_CH11_CTRL_TRIG_AHB_ERROR_ACCESS

#define DMA_CH11_CTRL_TRIG_AHB_ERROR_ACCESS "RO"

◆ DMA_CH11_CTRL_TRIG_AHB_ERROR_BITS

#define DMA_CH11_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000)

◆ DMA_CH11_CTRL_TRIG_AHB_ERROR_LSB

#define DMA_CH11_CTRL_TRIG_AHB_ERROR_LSB _u(31)

◆ DMA_CH11_CTRL_TRIG_AHB_ERROR_MSB

#define DMA_CH11_CTRL_TRIG_AHB_ERROR_MSB _u(31)

◆ DMA_CH11_CTRL_TRIG_AHB_ERROR_RESET

#define DMA_CH11_CTRL_TRIG_AHB_ERROR_RESET _u(0x0)

◆ DMA_CH11_CTRL_TRIG_BITS

#define DMA_CH11_CTRL_TRIG_BITS _u(0xe7ffffff)

◆ DMA_CH11_CTRL_TRIG_BSWAP_ACCESS

#define DMA_CH11_CTRL_TRIG_BSWAP_ACCESS "RW"

◆ DMA_CH11_CTRL_TRIG_BSWAP_BITS

#define DMA_CH11_CTRL_TRIG_BSWAP_BITS _u(0x01000000)

◆ DMA_CH11_CTRL_TRIG_BSWAP_LSB

#define DMA_CH11_CTRL_TRIG_BSWAP_LSB _u(24)

◆ DMA_CH11_CTRL_TRIG_BSWAP_MSB

#define DMA_CH11_CTRL_TRIG_BSWAP_MSB _u(24)

◆ DMA_CH11_CTRL_TRIG_BSWAP_RESET

#define DMA_CH11_CTRL_TRIG_BSWAP_RESET _u(0x0)

◆ DMA_CH11_CTRL_TRIG_BUSY_ACCESS

#define DMA_CH11_CTRL_TRIG_BUSY_ACCESS "RO"

◆ DMA_CH11_CTRL_TRIG_BUSY_BITS

#define DMA_CH11_CTRL_TRIG_BUSY_BITS _u(0x04000000)

◆ DMA_CH11_CTRL_TRIG_BUSY_LSB

#define DMA_CH11_CTRL_TRIG_BUSY_LSB _u(26)

◆ DMA_CH11_CTRL_TRIG_BUSY_MSB

#define DMA_CH11_CTRL_TRIG_BUSY_MSB _u(26)

◆ DMA_CH11_CTRL_TRIG_BUSY_RESET

#define DMA_CH11_CTRL_TRIG_BUSY_RESET _u(0x0)

◆ DMA_CH11_CTRL_TRIG_CHAIN_TO_ACCESS

#define DMA_CH11_CTRL_TRIG_CHAIN_TO_ACCESS "RW"

◆ DMA_CH11_CTRL_TRIG_CHAIN_TO_BITS

#define DMA_CH11_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000)

◆ DMA_CH11_CTRL_TRIG_CHAIN_TO_LSB

#define DMA_CH11_CTRL_TRIG_CHAIN_TO_LSB _u(13)

◆ DMA_CH11_CTRL_TRIG_CHAIN_TO_MSB

#define DMA_CH11_CTRL_TRIG_CHAIN_TO_MSB _u(16)

◆ DMA_CH11_CTRL_TRIG_CHAIN_TO_RESET

#define DMA_CH11_CTRL_TRIG_CHAIN_TO_RESET _u(0x0)

◆ DMA_CH11_CTRL_TRIG_DATA_SIZE_ACCESS

#define DMA_CH11_CTRL_TRIG_DATA_SIZE_ACCESS "RW"

◆ DMA_CH11_CTRL_TRIG_DATA_SIZE_BITS

#define DMA_CH11_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c)

◆ DMA_CH11_CTRL_TRIG_DATA_SIZE_LSB

#define DMA_CH11_CTRL_TRIG_DATA_SIZE_LSB _u(2)

◆ DMA_CH11_CTRL_TRIG_DATA_SIZE_MSB

#define DMA_CH11_CTRL_TRIG_DATA_SIZE_MSB _u(3)

◆ DMA_CH11_CTRL_TRIG_DATA_SIZE_RESET

#define DMA_CH11_CTRL_TRIG_DATA_SIZE_RESET _u(0x0)

◆ DMA_CH11_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE

#define DMA_CH11_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0)

◆ DMA_CH11_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD

#define DMA_CH11_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1)

◆ DMA_CH11_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD

#define DMA_CH11_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2)

◆ DMA_CH11_CTRL_TRIG_EN_ACCESS

#define DMA_CH11_CTRL_TRIG_EN_ACCESS "RW"

◆ DMA_CH11_CTRL_TRIG_EN_BITS

#define DMA_CH11_CTRL_TRIG_EN_BITS _u(0x00000001)

◆ DMA_CH11_CTRL_TRIG_EN_LSB

#define DMA_CH11_CTRL_TRIG_EN_LSB _u(0)

◆ DMA_CH11_CTRL_TRIG_EN_MSB

#define DMA_CH11_CTRL_TRIG_EN_MSB _u(0)

◆ DMA_CH11_CTRL_TRIG_EN_RESET

#define DMA_CH11_CTRL_TRIG_EN_RESET _u(0x0)

◆ DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_ACCESS

#define DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW"

◆ DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_BITS

#define DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002)

◆ DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_LSB

#define DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1)

◆ DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_MSB

#define DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1)

◆ DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_RESET

#define DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0)

◆ DMA_CH11_CTRL_TRIG_INCR_READ_ACCESS

#define DMA_CH11_CTRL_TRIG_INCR_READ_ACCESS "RW"

◆ DMA_CH11_CTRL_TRIG_INCR_READ_BITS

#define DMA_CH11_CTRL_TRIG_INCR_READ_BITS _u(0x00000010)

◆ DMA_CH11_CTRL_TRIG_INCR_READ_LSB

#define DMA_CH11_CTRL_TRIG_INCR_READ_LSB _u(4)

◆ DMA_CH11_CTRL_TRIG_INCR_READ_MSB

#define DMA_CH11_CTRL_TRIG_INCR_READ_MSB _u(4)

◆ DMA_CH11_CTRL_TRIG_INCR_READ_RESET

#define DMA_CH11_CTRL_TRIG_INCR_READ_RESET _u(0x0)

◆ DMA_CH11_CTRL_TRIG_INCR_READ_REV_ACCESS

#define DMA_CH11_CTRL_TRIG_INCR_READ_REV_ACCESS "RW"

◆ DMA_CH11_CTRL_TRIG_INCR_READ_REV_BITS

#define DMA_CH11_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020)

◆ DMA_CH11_CTRL_TRIG_INCR_READ_REV_LSB

#define DMA_CH11_CTRL_TRIG_INCR_READ_REV_LSB _u(5)

◆ DMA_CH11_CTRL_TRIG_INCR_READ_REV_MSB

#define DMA_CH11_CTRL_TRIG_INCR_READ_REV_MSB _u(5)

◆ DMA_CH11_CTRL_TRIG_INCR_READ_REV_RESET

#define DMA_CH11_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0)

◆ DMA_CH11_CTRL_TRIG_INCR_WRITE_ACCESS

#define DMA_CH11_CTRL_TRIG_INCR_WRITE_ACCESS "RW"

◆ DMA_CH11_CTRL_TRIG_INCR_WRITE_BITS

#define DMA_CH11_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040)

◆ DMA_CH11_CTRL_TRIG_INCR_WRITE_LSB

#define DMA_CH11_CTRL_TRIG_INCR_WRITE_LSB _u(6)

◆ DMA_CH11_CTRL_TRIG_INCR_WRITE_MSB

#define DMA_CH11_CTRL_TRIG_INCR_WRITE_MSB _u(6)

◆ DMA_CH11_CTRL_TRIG_INCR_WRITE_RESET

#define DMA_CH11_CTRL_TRIG_INCR_WRITE_RESET _u(0x0)

◆ DMA_CH11_CTRL_TRIG_INCR_WRITE_REV_ACCESS

#define DMA_CH11_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW"

◆ DMA_CH11_CTRL_TRIG_INCR_WRITE_REV_BITS

#define DMA_CH11_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080)

◆ DMA_CH11_CTRL_TRIG_INCR_WRITE_REV_LSB

#define DMA_CH11_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7)

◆ DMA_CH11_CTRL_TRIG_INCR_WRITE_REV_MSB

#define DMA_CH11_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7)

◆ DMA_CH11_CTRL_TRIG_INCR_WRITE_REV_RESET

#define DMA_CH11_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0)

◆ DMA_CH11_CTRL_TRIG_IRQ_QUIET_ACCESS

#define DMA_CH11_CTRL_TRIG_IRQ_QUIET_ACCESS "RW"

◆ DMA_CH11_CTRL_TRIG_IRQ_QUIET_BITS

#define DMA_CH11_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000)

◆ DMA_CH11_CTRL_TRIG_IRQ_QUIET_LSB

#define DMA_CH11_CTRL_TRIG_IRQ_QUIET_LSB _u(23)

◆ DMA_CH11_CTRL_TRIG_IRQ_QUIET_MSB

#define DMA_CH11_CTRL_TRIG_IRQ_QUIET_MSB _u(23)

◆ DMA_CH11_CTRL_TRIG_IRQ_QUIET_RESET

#define DMA_CH11_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0)

◆ DMA_CH11_CTRL_TRIG_OFFSET

#define DMA_CH11_CTRL_TRIG_OFFSET _u(0x000002cc)

◆ DMA_CH11_CTRL_TRIG_READ_ERROR_ACCESS

#define DMA_CH11_CTRL_TRIG_READ_ERROR_ACCESS "WC"

◆ DMA_CH11_CTRL_TRIG_READ_ERROR_BITS

#define DMA_CH11_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000)

◆ DMA_CH11_CTRL_TRIG_READ_ERROR_LSB

#define DMA_CH11_CTRL_TRIG_READ_ERROR_LSB _u(30)

◆ DMA_CH11_CTRL_TRIG_READ_ERROR_MSB

#define DMA_CH11_CTRL_TRIG_READ_ERROR_MSB _u(30)

◆ DMA_CH11_CTRL_TRIG_READ_ERROR_RESET

#define DMA_CH11_CTRL_TRIG_READ_ERROR_RESET _u(0x0)

◆ DMA_CH11_CTRL_TRIG_RESET

#define DMA_CH11_CTRL_TRIG_RESET _u(0x00000000)

◆ DMA_CH11_CTRL_TRIG_RING_SEL_ACCESS

#define DMA_CH11_CTRL_TRIG_RING_SEL_ACCESS "RW"

◆ DMA_CH11_CTRL_TRIG_RING_SEL_BITS

#define DMA_CH11_CTRL_TRIG_RING_SEL_BITS _u(0x00001000)

◆ DMA_CH11_CTRL_TRIG_RING_SEL_LSB

#define DMA_CH11_CTRL_TRIG_RING_SEL_LSB _u(12)

◆ DMA_CH11_CTRL_TRIG_RING_SEL_MSB

#define DMA_CH11_CTRL_TRIG_RING_SEL_MSB _u(12)

◆ DMA_CH11_CTRL_TRIG_RING_SEL_RESET

#define DMA_CH11_CTRL_TRIG_RING_SEL_RESET _u(0x0)

◆ DMA_CH11_CTRL_TRIG_RING_SIZE_ACCESS

#define DMA_CH11_CTRL_TRIG_RING_SIZE_ACCESS "RW"

◆ DMA_CH11_CTRL_TRIG_RING_SIZE_BITS

#define DMA_CH11_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00)

◆ DMA_CH11_CTRL_TRIG_RING_SIZE_LSB

#define DMA_CH11_CTRL_TRIG_RING_SIZE_LSB _u(8)

◆ DMA_CH11_CTRL_TRIG_RING_SIZE_MSB

#define DMA_CH11_CTRL_TRIG_RING_SIZE_MSB _u(11)

◆ DMA_CH11_CTRL_TRIG_RING_SIZE_RESET

#define DMA_CH11_CTRL_TRIG_RING_SIZE_RESET _u(0x0)

◆ DMA_CH11_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE

#define DMA_CH11_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0)

◆ DMA_CH11_CTRL_TRIG_SNIFF_EN_ACCESS

#define DMA_CH11_CTRL_TRIG_SNIFF_EN_ACCESS "RW"

◆ DMA_CH11_CTRL_TRIG_SNIFF_EN_BITS

#define DMA_CH11_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000)

◆ DMA_CH11_CTRL_TRIG_SNIFF_EN_LSB

#define DMA_CH11_CTRL_TRIG_SNIFF_EN_LSB _u(25)

◆ DMA_CH11_CTRL_TRIG_SNIFF_EN_MSB

#define DMA_CH11_CTRL_TRIG_SNIFF_EN_MSB _u(25)

◆ DMA_CH11_CTRL_TRIG_SNIFF_EN_RESET

#define DMA_CH11_CTRL_TRIG_SNIFF_EN_RESET _u(0x0)

◆ DMA_CH11_CTRL_TRIG_TREQ_SEL_ACCESS

#define DMA_CH11_CTRL_TRIG_TREQ_SEL_ACCESS "RW"

◆ DMA_CH11_CTRL_TRIG_TREQ_SEL_BITS

#define DMA_CH11_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000)

◆ DMA_CH11_CTRL_TRIG_TREQ_SEL_LSB

#define DMA_CH11_CTRL_TRIG_TREQ_SEL_LSB _u(17)

◆ DMA_CH11_CTRL_TRIG_TREQ_SEL_MSB

#define DMA_CH11_CTRL_TRIG_TREQ_SEL_MSB _u(22)

◆ DMA_CH11_CTRL_TRIG_TREQ_SEL_RESET

#define DMA_CH11_CTRL_TRIG_TREQ_SEL_RESET _u(0x00)

◆ DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT

#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f)

◆ DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0

#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b)

◆ DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1

#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c)

◆ DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2

#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d)

◆ DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3

#define DMA_CH11_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e)

◆ DMA_CH11_CTRL_TRIG_WRITE_ERROR_ACCESS

#define DMA_CH11_CTRL_TRIG_WRITE_ERROR_ACCESS "WC"

◆ DMA_CH11_CTRL_TRIG_WRITE_ERROR_BITS

#define DMA_CH11_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000)

◆ DMA_CH11_CTRL_TRIG_WRITE_ERROR_LSB

#define DMA_CH11_CTRL_TRIG_WRITE_ERROR_LSB _u(29)

◆ DMA_CH11_CTRL_TRIG_WRITE_ERROR_MSB

#define DMA_CH11_CTRL_TRIG_WRITE_ERROR_MSB _u(29)

◆ DMA_CH11_CTRL_TRIG_WRITE_ERROR_RESET

#define DMA_CH11_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0)

◆ DMA_CH11_DBG_CTDREQ_ACCESS

#define DMA_CH11_DBG_CTDREQ_ACCESS "WC"

◆ DMA_CH11_DBG_CTDREQ_BITS

#define DMA_CH11_DBG_CTDREQ_BITS _u(0x0000003f)

◆ DMA_CH11_DBG_CTDREQ_LSB

#define DMA_CH11_DBG_CTDREQ_LSB _u(0)

◆ DMA_CH11_DBG_CTDREQ_MSB

#define DMA_CH11_DBG_CTDREQ_MSB _u(5)

◆ DMA_CH11_DBG_CTDREQ_OFFSET

#define DMA_CH11_DBG_CTDREQ_OFFSET _u(0x00000ac0)

◆ DMA_CH11_DBG_CTDREQ_RESET

#define DMA_CH11_DBG_CTDREQ_RESET _u(0x00000000)

◆ DMA_CH11_DBG_TCR_ACCESS

#define DMA_CH11_DBG_TCR_ACCESS "RO"

◆ DMA_CH11_DBG_TCR_BITS

#define DMA_CH11_DBG_TCR_BITS _u(0xffffffff)

◆ DMA_CH11_DBG_TCR_LSB

#define DMA_CH11_DBG_TCR_LSB _u(0)

◆ DMA_CH11_DBG_TCR_MSB

#define DMA_CH11_DBG_TCR_MSB _u(31)

◆ DMA_CH11_DBG_TCR_OFFSET

#define DMA_CH11_DBG_TCR_OFFSET _u(0x00000ac4)

◆ DMA_CH11_DBG_TCR_RESET

#define DMA_CH11_DBG_TCR_RESET _u(0x00000000)

◆ DMA_CH11_READ_ADDR_ACCESS

#define DMA_CH11_READ_ADDR_ACCESS "RW"

◆ DMA_CH11_READ_ADDR_BITS

#define DMA_CH11_READ_ADDR_BITS _u(0xffffffff)

◆ DMA_CH11_READ_ADDR_LSB

#define DMA_CH11_READ_ADDR_LSB _u(0)

◆ DMA_CH11_READ_ADDR_MSB

#define DMA_CH11_READ_ADDR_MSB _u(31)

◆ DMA_CH11_READ_ADDR_OFFSET

#define DMA_CH11_READ_ADDR_OFFSET _u(0x000002c0)

◆ DMA_CH11_READ_ADDR_RESET

#define DMA_CH11_READ_ADDR_RESET _u(0x00000000)

◆ DMA_CH11_TRANS_COUNT_BITS

#define DMA_CH11_TRANS_COUNT_BITS _u(0xffffffff)

◆ DMA_CH11_TRANS_COUNT_COUNT_ACCESS

#define DMA_CH11_TRANS_COUNT_COUNT_ACCESS "RW"

◆ DMA_CH11_TRANS_COUNT_COUNT_BITS

#define DMA_CH11_TRANS_COUNT_COUNT_BITS _u(0x0fffffff)

◆ DMA_CH11_TRANS_COUNT_COUNT_LSB

#define DMA_CH11_TRANS_COUNT_COUNT_LSB _u(0)

◆ DMA_CH11_TRANS_COUNT_COUNT_MSB

#define DMA_CH11_TRANS_COUNT_COUNT_MSB _u(27)

◆ DMA_CH11_TRANS_COUNT_COUNT_RESET

#define DMA_CH11_TRANS_COUNT_COUNT_RESET _u(0x0000000)

◆ DMA_CH11_TRANS_COUNT_MODE_ACCESS

#define DMA_CH11_TRANS_COUNT_MODE_ACCESS "RW"

◆ DMA_CH11_TRANS_COUNT_MODE_BITS

#define DMA_CH11_TRANS_COUNT_MODE_BITS _u(0xf0000000)

◆ DMA_CH11_TRANS_COUNT_MODE_LSB

#define DMA_CH11_TRANS_COUNT_MODE_LSB _u(28)

◆ DMA_CH11_TRANS_COUNT_MODE_MSB

#define DMA_CH11_TRANS_COUNT_MODE_MSB _u(31)

◆ DMA_CH11_TRANS_COUNT_MODE_RESET

#define DMA_CH11_TRANS_COUNT_MODE_RESET _u(0x0)

◆ DMA_CH11_TRANS_COUNT_MODE_VALUE_ENDLESS

#define DMA_CH11_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf)

◆ DMA_CH11_TRANS_COUNT_MODE_VALUE_NORMAL

#define DMA_CH11_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0)

◆ DMA_CH11_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF

#define DMA_CH11_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1)

◆ DMA_CH11_TRANS_COUNT_OFFSET

#define DMA_CH11_TRANS_COUNT_OFFSET _u(0x000002c8)

◆ DMA_CH11_TRANS_COUNT_RESET

#define DMA_CH11_TRANS_COUNT_RESET _u(0x00000000)

◆ DMA_CH11_WRITE_ADDR_ACCESS

#define DMA_CH11_WRITE_ADDR_ACCESS "RW"

◆ DMA_CH11_WRITE_ADDR_BITS

#define DMA_CH11_WRITE_ADDR_BITS _u(0xffffffff)

◆ DMA_CH11_WRITE_ADDR_LSB

#define DMA_CH11_WRITE_ADDR_LSB _u(0)

◆ DMA_CH11_WRITE_ADDR_MSB

#define DMA_CH11_WRITE_ADDR_MSB _u(31)

◆ DMA_CH11_WRITE_ADDR_OFFSET

#define DMA_CH11_WRITE_ADDR_OFFSET _u(0x000002c4)

◆ DMA_CH11_WRITE_ADDR_RESET

#define DMA_CH11_WRITE_ADDR_RESET _u(0x00000000)

◆ DMA_CH12_AL1_CTRL_ACCESS

#define DMA_CH12_AL1_CTRL_ACCESS "RW"

◆ DMA_CH12_AL1_CTRL_BITS

#define DMA_CH12_AL1_CTRL_BITS _u(0xffffffff)

◆ DMA_CH12_AL1_CTRL_LSB

#define DMA_CH12_AL1_CTRL_LSB _u(0)

◆ DMA_CH12_AL1_CTRL_MSB

#define DMA_CH12_AL1_CTRL_MSB _u(31)

◆ DMA_CH12_AL1_CTRL_OFFSET

#define DMA_CH12_AL1_CTRL_OFFSET _u(0x00000310)

◆ DMA_CH12_AL1_CTRL_RESET

#define DMA_CH12_AL1_CTRL_RESET "-"

◆ DMA_CH12_AL1_READ_ADDR_ACCESS

#define DMA_CH12_AL1_READ_ADDR_ACCESS "RW"

◆ DMA_CH12_AL1_READ_ADDR_BITS

#define DMA_CH12_AL1_READ_ADDR_BITS _u(0xffffffff)

◆ DMA_CH12_AL1_READ_ADDR_LSB

#define DMA_CH12_AL1_READ_ADDR_LSB _u(0)

◆ DMA_CH12_AL1_READ_ADDR_MSB

#define DMA_CH12_AL1_READ_ADDR_MSB _u(31)

◆ DMA_CH12_AL1_READ_ADDR_OFFSET

#define DMA_CH12_AL1_READ_ADDR_OFFSET _u(0x00000314)

◆ DMA_CH12_AL1_READ_ADDR_RESET

#define DMA_CH12_AL1_READ_ADDR_RESET "-"

◆ DMA_CH12_AL1_TRANS_COUNT_TRIG_ACCESS

#define DMA_CH12_AL1_TRANS_COUNT_TRIG_ACCESS "RW"

◆ DMA_CH12_AL1_TRANS_COUNT_TRIG_BITS

#define DMA_CH12_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff)

◆ DMA_CH12_AL1_TRANS_COUNT_TRIG_LSB

#define DMA_CH12_AL1_TRANS_COUNT_TRIG_LSB _u(0)

◆ DMA_CH12_AL1_TRANS_COUNT_TRIG_MSB

#define DMA_CH12_AL1_TRANS_COUNT_TRIG_MSB _u(31)

◆ DMA_CH12_AL1_TRANS_COUNT_TRIG_OFFSET

#define DMA_CH12_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000031c)

◆ DMA_CH12_AL1_TRANS_COUNT_TRIG_RESET

#define DMA_CH12_AL1_TRANS_COUNT_TRIG_RESET "-"

◆ DMA_CH12_AL1_WRITE_ADDR_ACCESS

#define DMA_CH12_AL1_WRITE_ADDR_ACCESS "RW"

◆ DMA_CH12_AL1_WRITE_ADDR_BITS

#define DMA_CH12_AL1_WRITE_ADDR_BITS _u(0xffffffff)

◆ DMA_CH12_AL1_WRITE_ADDR_LSB

#define DMA_CH12_AL1_WRITE_ADDR_LSB _u(0)

◆ DMA_CH12_AL1_WRITE_ADDR_MSB

#define DMA_CH12_AL1_WRITE_ADDR_MSB _u(31)

◆ DMA_CH12_AL1_WRITE_ADDR_OFFSET

#define DMA_CH12_AL1_WRITE_ADDR_OFFSET _u(0x00000318)

◆ DMA_CH12_AL1_WRITE_ADDR_RESET

#define DMA_CH12_AL1_WRITE_ADDR_RESET "-"

◆ DMA_CH12_AL2_CTRL_ACCESS

#define DMA_CH12_AL2_CTRL_ACCESS "RW"

◆ DMA_CH12_AL2_CTRL_BITS

#define DMA_CH12_AL2_CTRL_BITS _u(0xffffffff)

◆ DMA_CH12_AL2_CTRL_LSB

#define DMA_CH12_AL2_CTRL_LSB _u(0)

◆ DMA_CH12_AL2_CTRL_MSB

#define DMA_CH12_AL2_CTRL_MSB _u(31)

◆ DMA_CH12_AL2_CTRL_OFFSET

#define DMA_CH12_AL2_CTRL_OFFSET _u(0x00000320)

◆ DMA_CH12_AL2_CTRL_RESET

#define DMA_CH12_AL2_CTRL_RESET "-"

◆ DMA_CH12_AL2_READ_ADDR_ACCESS

#define DMA_CH12_AL2_READ_ADDR_ACCESS "RW"

◆ DMA_CH12_AL2_READ_ADDR_BITS

#define DMA_CH12_AL2_READ_ADDR_BITS _u(0xffffffff)

◆ DMA_CH12_AL2_READ_ADDR_LSB

#define DMA_CH12_AL2_READ_ADDR_LSB _u(0)

◆ DMA_CH12_AL2_READ_ADDR_MSB

#define DMA_CH12_AL2_READ_ADDR_MSB _u(31)

◆ DMA_CH12_AL2_READ_ADDR_OFFSET

#define DMA_CH12_AL2_READ_ADDR_OFFSET _u(0x00000328)

◆ DMA_CH12_AL2_READ_ADDR_RESET

#define DMA_CH12_AL2_READ_ADDR_RESET "-"

◆ DMA_CH12_AL2_TRANS_COUNT_ACCESS

#define DMA_CH12_AL2_TRANS_COUNT_ACCESS "RW"

◆ DMA_CH12_AL2_TRANS_COUNT_BITS

#define DMA_CH12_AL2_TRANS_COUNT_BITS _u(0xffffffff)

◆ DMA_CH12_AL2_TRANS_COUNT_LSB

#define DMA_CH12_AL2_TRANS_COUNT_LSB _u(0)

◆ DMA_CH12_AL2_TRANS_COUNT_MSB

#define DMA_CH12_AL2_TRANS_COUNT_MSB _u(31)

◆ DMA_CH12_AL2_TRANS_COUNT_OFFSET

#define DMA_CH12_AL2_TRANS_COUNT_OFFSET _u(0x00000324)

◆ DMA_CH12_AL2_TRANS_COUNT_RESET

#define DMA_CH12_AL2_TRANS_COUNT_RESET "-"

◆ DMA_CH12_AL2_WRITE_ADDR_TRIG_ACCESS

#define DMA_CH12_AL2_WRITE_ADDR_TRIG_ACCESS "RW"

◆ DMA_CH12_AL2_WRITE_ADDR_TRIG_BITS

#define DMA_CH12_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff)

◆ DMA_CH12_AL2_WRITE_ADDR_TRIG_LSB

#define DMA_CH12_AL2_WRITE_ADDR_TRIG_LSB _u(0)

◆ DMA_CH12_AL2_WRITE_ADDR_TRIG_MSB

#define DMA_CH12_AL2_WRITE_ADDR_TRIG_MSB _u(31)

◆ DMA_CH12_AL2_WRITE_ADDR_TRIG_OFFSET

#define DMA_CH12_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x0000032c)

◆ DMA_CH12_AL2_WRITE_ADDR_TRIG_RESET

#define DMA_CH12_AL2_WRITE_ADDR_TRIG_RESET "-"

◆ DMA_CH12_AL3_CTRL_ACCESS

#define DMA_CH12_AL3_CTRL_ACCESS "RW"

◆ DMA_CH12_AL3_CTRL_BITS

#define DMA_CH12_AL3_CTRL_BITS _u(0xffffffff)

◆ DMA_CH12_AL3_CTRL_LSB

#define DMA_CH12_AL3_CTRL_LSB _u(0)

◆ DMA_CH12_AL3_CTRL_MSB

#define DMA_CH12_AL3_CTRL_MSB _u(31)

◆ DMA_CH12_AL3_CTRL_OFFSET

#define DMA_CH12_AL3_CTRL_OFFSET _u(0x00000330)

◆ DMA_CH12_AL3_CTRL_RESET

#define DMA_CH12_AL3_CTRL_RESET "-"

◆ DMA_CH12_AL3_READ_ADDR_TRIG_ACCESS

#define DMA_CH12_AL3_READ_ADDR_TRIG_ACCESS "RW"

◆ DMA_CH12_AL3_READ_ADDR_TRIG_BITS

#define DMA_CH12_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff)

◆ DMA_CH12_AL3_READ_ADDR_TRIG_LSB

#define DMA_CH12_AL3_READ_ADDR_TRIG_LSB _u(0)

◆ DMA_CH12_AL3_READ_ADDR_TRIG_MSB

#define DMA_CH12_AL3_READ_ADDR_TRIG_MSB _u(31)

◆ DMA_CH12_AL3_READ_ADDR_TRIG_OFFSET

#define DMA_CH12_AL3_READ_ADDR_TRIG_OFFSET _u(0x0000033c)

◆ DMA_CH12_AL3_READ_ADDR_TRIG_RESET

#define DMA_CH12_AL3_READ_ADDR_TRIG_RESET "-"

◆ DMA_CH12_AL3_TRANS_COUNT_ACCESS

#define DMA_CH12_AL3_TRANS_COUNT_ACCESS "RW"

◆ DMA_CH12_AL3_TRANS_COUNT_BITS

#define DMA_CH12_AL3_TRANS_COUNT_BITS _u(0xffffffff)

◆ DMA_CH12_AL3_TRANS_COUNT_LSB

#define DMA_CH12_AL3_TRANS_COUNT_LSB _u(0)

◆ DMA_CH12_AL3_TRANS_COUNT_MSB

#define DMA_CH12_AL3_TRANS_COUNT_MSB _u(31)

◆ DMA_CH12_AL3_TRANS_COUNT_OFFSET

#define DMA_CH12_AL3_TRANS_COUNT_OFFSET _u(0x00000338)

◆ DMA_CH12_AL3_TRANS_COUNT_RESET

#define DMA_CH12_AL3_TRANS_COUNT_RESET "-"

◆ DMA_CH12_AL3_WRITE_ADDR_ACCESS

#define DMA_CH12_AL3_WRITE_ADDR_ACCESS "RW"

◆ DMA_CH12_AL3_WRITE_ADDR_BITS

#define DMA_CH12_AL3_WRITE_ADDR_BITS _u(0xffffffff)

◆ DMA_CH12_AL3_WRITE_ADDR_LSB

#define DMA_CH12_AL3_WRITE_ADDR_LSB _u(0)

◆ DMA_CH12_AL3_WRITE_ADDR_MSB

#define DMA_CH12_AL3_WRITE_ADDR_MSB _u(31)

◆ DMA_CH12_AL3_WRITE_ADDR_OFFSET

#define DMA_CH12_AL3_WRITE_ADDR_OFFSET _u(0x00000334)

◆ DMA_CH12_AL3_WRITE_ADDR_RESET

#define DMA_CH12_AL3_WRITE_ADDR_RESET "-"

◆ DMA_CH12_CTRL_TRIG_AHB_ERROR_ACCESS

#define DMA_CH12_CTRL_TRIG_AHB_ERROR_ACCESS "RO"

◆ DMA_CH12_CTRL_TRIG_AHB_ERROR_BITS

#define DMA_CH12_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000)

◆ DMA_CH12_CTRL_TRIG_AHB_ERROR_LSB

#define DMA_CH12_CTRL_TRIG_AHB_ERROR_LSB _u(31)

◆ DMA_CH12_CTRL_TRIG_AHB_ERROR_MSB

#define DMA_CH12_CTRL_TRIG_AHB_ERROR_MSB _u(31)

◆ DMA_CH12_CTRL_TRIG_AHB_ERROR_RESET

#define DMA_CH12_CTRL_TRIG_AHB_ERROR_RESET _u(0x0)

◆ DMA_CH12_CTRL_TRIG_BITS

#define DMA_CH12_CTRL_TRIG_BITS _u(0xe7ffffff)

◆ DMA_CH12_CTRL_TRIG_BSWAP_ACCESS

#define DMA_CH12_CTRL_TRIG_BSWAP_ACCESS "RW"

◆ DMA_CH12_CTRL_TRIG_BSWAP_BITS

#define DMA_CH12_CTRL_TRIG_BSWAP_BITS _u(0x01000000)

◆ DMA_CH12_CTRL_TRIG_BSWAP_LSB

#define DMA_CH12_CTRL_TRIG_BSWAP_LSB _u(24)

◆ DMA_CH12_CTRL_TRIG_BSWAP_MSB

#define DMA_CH12_CTRL_TRIG_BSWAP_MSB _u(24)

◆ DMA_CH12_CTRL_TRIG_BSWAP_RESET

#define DMA_CH12_CTRL_TRIG_BSWAP_RESET _u(0x0)

◆ DMA_CH12_CTRL_TRIG_BUSY_ACCESS

#define DMA_CH12_CTRL_TRIG_BUSY_ACCESS "RO"

◆ DMA_CH12_CTRL_TRIG_BUSY_BITS

#define DMA_CH12_CTRL_TRIG_BUSY_BITS _u(0x04000000)

◆ DMA_CH12_CTRL_TRIG_BUSY_LSB

#define DMA_CH12_CTRL_TRIG_BUSY_LSB _u(26)

◆ DMA_CH12_CTRL_TRIG_BUSY_MSB

#define DMA_CH12_CTRL_TRIG_BUSY_MSB _u(26)

◆ DMA_CH12_CTRL_TRIG_BUSY_RESET

#define DMA_CH12_CTRL_TRIG_BUSY_RESET _u(0x0)

◆ DMA_CH12_CTRL_TRIG_CHAIN_TO_ACCESS

#define DMA_CH12_CTRL_TRIG_CHAIN_TO_ACCESS "RW"

◆ DMA_CH12_CTRL_TRIG_CHAIN_TO_BITS

#define DMA_CH12_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000)

◆ DMA_CH12_CTRL_TRIG_CHAIN_TO_LSB

#define DMA_CH12_CTRL_TRIG_CHAIN_TO_LSB _u(13)

◆ DMA_CH12_CTRL_TRIG_CHAIN_TO_MSB

#define DMA_CH12_CTRL_TRIG_CHAIN_TO_MSB _u(16)

◆ DMA_CH12_CTRL_TRIG_CHAIN_TO_RESET

#define DMA_CH12_CTRL_TRIG_CHAIN_TO_RESET _u(0x0)

◆ DMA_CH12_CTRL_TRIG_DATA_SIZE_ACCESS

#define DMA_CH12_CTRL_TRIG_DATA_SIZE_ACCESS "RW"

◆ DMA_CH12_CTRL_TRIG_DATA_SIZE_BITS

#define DMA_CH12_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c)

◆ DMA_CH12_CTRL_TRIG_DATA_SIZE_LSB

#define DMA_CH12_CTRL_TRIG_DATA_SIZE_LSB _u(2)

◆ DMA_CH12_CTRL_TRIG_DATA_SIZE_MSB

#define DMA_CH12_CTRL_TRIG_DATA_SIZE_MSB _u(3)

◆ DMA_CH12_CTRL_TRIG_DATA_SIZE_RESET

#define DMA_CH12_CTRL_TRIG_DATA_SIZE_RESET _u(0x0)

◆ DMA_CH12_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE

#define DMA_CH12_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0)

◆ DMA_CH12_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD

#define DMA_CH12_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1)

◆ DMA_CH12_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD

#define DMA_CH12_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2)

◆ DMA_CH12_CTRL_TRIG_EN_ACCESS

#define DMA_CH12_CTRL_TRIG_EN_ACCESS "RW"

◆ DMA_CH12_CTRL_TRIG_EN_BITS

#define DMA_CH12_CTRL_TRIG_EN_BITS _u(0x00000001)

◆ DMA_CH12_CTRL_TRIG_EN_LSB

#define DMA_CH12_CTRL_TRIG_EN_LSB _u(0)

◆ DMA_CH12_CTRL_TRIG_EN_MSB

#define DMA_CH12_CTRL_TRIG_EN_MSB _u(0)

◆ DMA_CH12_CTRL_TRIG_EN_RESET

#define DMA_CH12_CTRL_TRIG_EN_RESET _u(0x0)

◆ DMA_CH12_CTRL_TRIG_HIGH_PRIORITY_ACCESS

#define DMA_CH12_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW"

◆ DMA_CH12_CTRL_TRIG_HIGH_PRIORITY_BITS

#define DMA_CH12_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002)

◆ DMA_CH12_CTRL_TRIG_HIGH_PRIORITY_LSB

#define DMA_CH12_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1)

◆ DMA_CH12_CTRL_TRIG_HIGH_PRIORITY_MSB

#define DMA_CH12_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1)

◆ DMA_CH12_CTRL_TRIG_HIGH_PRIORITY_RESET

#define DMA_CH12_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0)

◆ DMA_CH12_CTRL_TRIG_INCR_READ_ACCESS

#define DMA_CH12_CTRL_TRIG_INCR_READ_ACCESS "RW"

◆ DMA_CH12_CTRL_TRIG_INCR_READ_BITS

#define DMA_CH12_CTRL_TRIG_INCR_READ_BITS _u(0x00000010)

◆ DMA_CH12_CTRL_TRIG_INCR_READ_LSB

#define DMA_CH12_CTRL_TRIG_INCR_READ_LSB _u(4)

◆ DMA_CH12_CTRL_TRIG_INCR_READ_MSB

#define DMA_CH12_CTRL_TRIG_INCR_READ_MSB _u(4)

◆ DMA_CH12_CTRL_TRIG_INCR_READ_RESET

#define DMA_CH12_CTRL_TRIG_INCR_READ_RESET _u(0x0)

◆ DMA_CH12_CTRL_TRIG_INCR_READ_REV_ACCESS

#define DMA_CH12_CTRL_TRIG_INCR_READ_REV_ACCESS "RW"

◆ DMA_CH12_CTRL_TRIG_INCR_READ_REV_BITS

#define DMA_CH12_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020)

◆ DMA_CH12_CTRL_TRIG_INCR_READ_REV_LSB

#define DMA_CH12_CTRL_TRIG_INCR_READ_REV_LSB _u(5)

◆ DMA_CH12_CTRL_TRIG_INCR_READ_REV_MSB

#define DMA_CH12_CTRL_TRIG_INCR_READ_REV_MSB _u(5)

◆ DMA_CH12_CTRL_TRIG_INCR_READ_REV_RESET

#define DMA_CH12_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0)

◆ DMA_CH12_CTRL_TRIG_INCR_WRITE_ACCESS

#define DMA_CH12_CTRL_TRIG_INCR_WRITE_ACCESS "RW"

◆ DMA_CH12_CTRL_TRIG_INCR_WRITE_BITS

#define DMA_CH12_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040)

◆ DMA_CH12_CTRL_TRIG_INCR_WRITE_LSB

#define DMA_CH12_CTRL_TRIG_INCR_WRITE_LSB _u(6)

◆ DMA_CH12_CTRL_TRIG_INCR_WRITE_MSB

#define DMA_CH12_CTRL_TRIG_INCR_WRITE_MSB _u(6)

◆ DMA_CH12_CTRL_TRIG_INCR_WRITE_RESET

#define DMA_CH12_CTRL_TRIG_INCR_WRITE_RESET _u(0x0)

◆ DMA_CH12_CTRL_TRIG_INCR_WRITE_REV_ACCESS

#define DMA_CH12_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW"

◆ DMA_CH12_CTRL_TRIG_INCR_WRITE_REV_BITS

#define DMA_CH12_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080)

◆ DMA_CH12_CTRL_TRIG_INCR_WRITE_REV_LSB

#define DMA_CH12_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7)

◆ DMA_CH12_CTRL_TRIG_INCR_WRITE_REV_MSB

#define DMA_CH12_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7)

◆ DMA_CH12_CTRL_TRIG_INCR_WRITE_REV_RESET

#define DMA_CH12_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0)

◆ DMA_CH12_CTRL_TRIG_IRQ_QUIET_ACCESS

#define DMA_CH12_CTRL_TRIG_IRQ_QUIET_ACCESS "RW"

◆ DMA_CH12_CTRL_TRIG_IRQ_QUIET_BITS

#define DMA_CH12_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000)

◆ DMA_CH12_CTRL_TRIG_IRQ_QUIET_LSB

#define DMA_CH12_CTRL_TRIG_IRQ_QUIET_LSB _u(23)

◆ DMA_CH12_CTRL_TRIG_IRQ_QUIET_MSB

#define DMA_CH12_CTRL_TRIG_IRQ_QUIET_MSB _u(23)

◆ DMA_CH12_CTRL_TRIG_IRQ_QUIET_RESET

#define DMA_CH12_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0)

◆ DMA_CH12_CTRL_TRIG_OFFSET

#define DMA_CH12_CTRL_TRIG_OFFSET _u(0x0000030c)

◆ DMA_CH12_CTRL_TRIG_READ_ERROR_ACCESS

#define DMA_CH12_CTRL_TRIG_READ_ERROR_ACCESS "WC"

◆ DMA_CH12_CTRL_TRIG_READ_ERROR_BITS

#define DMA_CH12_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000)

◆ DMA_CH12_CTRL_TRIG_READ_ERROR_LSB

#define DMA_CH12_CTRL_TRIG_READ_ERROR_LSB _u(30)

◆ DMA_CH12_CTRL_TRIG_READ_ERROR_MSB

#define DMA_CH12_CTRL_TRIG_READ_ERROR_MSB _u(30)

◆ DMA_CH12_CTRL_TRIG_READ_ERROR_RESET

#define DMA_CH12_CTRL_TRIG_READ_ERROR_RESET _u(0x0)

◆ DMA_CH12_CTRL_TRIG_RESET

#define DMA_CH12_CTRL_TRIG_RESET _u(0x00000000)

◆ DMA_CH12_CTRL_TRIG_RING_SEL_ACCESS

#define DMA_CH12_CTRL_TRIG_RING_SEL_ACCESS "RW"

◆ DMA_CH12_CTRL_TRIG_RING_SEL_BITS

#define DMA_CH12_CTRL_TRIG_RING_SEL_BITS _u(0x00001000)

◆ DMA_CH12_CTRL_TRIG_RING_SEL_LSB

#define DMA_CH12_CTRL_TRIG_RING_SEL_LSB _u(12)

◆ DMA_CH12_CTRL_TRIG_RING_SEL_MSB

#define DMA_CH12_CTRL_TRIG_RING_SEL_MSB _u(12)

◆ DMA_CH12_CTRL_TRIG_RING_SEL_RESET

#define DMA_CH12_CTRL_TRIG_RING_SEL_RESET _u(0x0)

◆ DMA_CH12_CTRL_TRIG_RING_SIZE_ACCESS

#define DMA_CH12_CTRL_TRIG_RING_SIZE_ACCESS "RW"

◆ DMA_CH12_CTRL_TRIG_RING_SIZE_BITS

#define DMA_CH12_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00)

◆ DMA_CH12_CTRL_TRIG_RING_SIZE_LSB

#define DMA_CH12_CTRL_TRIG_RING_SIZE_LSB _u(8)

◆ DMA_CH12_CTRL_TRIG_RING_SIZE_MSB

#define DMA_CH12_CTRL_TRIG_RING_SIZE_MSB _u(11)

◆ DMA_CH12_CTRL_TRIG_RING_SIZE_RESET

#define DMA_CH12_CTRL_TRIG_RING_SIZE_RESET _u(0x0)

◆ DMA_CH12_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE

#define DMA_CH12_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0)

◆ DMA_CH12_CTRL_TRIG_SNIFF_EN_ACCESS

#define DMA_CH12_CTRL_TRIG_SNIFF_EN_ACCESS "RW"

◆ DMA_CH12_CTRL_TRIG_SNIFF_EN_BITS

#define DMA_CH12_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000)

◆ DMA_CH12_CTRL_TRIG_SNIFF_EN_LSB

#define DMA_CH12_CTRL_TRIG_SNIFF_EN_LSB _u(25)

◆ DMA_CH12_CTRL_TRIG_SNIFF_EN_MSB

#define DMA_CH12_CTRL_TRIG_SNIFF_EN_MSB _u(25)

◆ DMA_CH12_CTRL_TRIG_SNIFF_EN_RESET

#define DMA_CH12_CTRL_TRIG_SNIFF_EN_RESET _u(0x0)

◆ DMA_CH12_CTRL_TRIG_TREQ_SEL_ACCESS

#define DMA_CH12_CTRL_TRIG_TREQ_SEL_ACCESS "RW"

◆ DMA_CH12_CTRL_TRIG_TREQ_SEL_BITS

#define DMA_CH12_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000)

◆ DMA_CH12_CTRL_TRIG_TREQ_SEL_LSB

#define DMA_CH12_CTRL_TRIG_TREQ_SEL_LSB _u(17)

◆ DMA_CH12_CTRL_TRIG_TREQ_SEL_MSB

#define DMA_CH12_CTRL_TRIG_TREQ_SEL_MSB _u(22)

◆ DMA_CH12_CTRL_TRIG_TREQ_SEL_RESET

#define DMA_CH12_CTRL_TRIG_TREQ_SEL_RESET _u(0x00)

◆ DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT

#define DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f)

◆ DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0

#define DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b)

◆ DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1

#define DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c)

◆ DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2

#define DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d)

◆ DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3

#define DMA_CH12_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e)

◆ DMA_CH12_CTRL_TRIG_WRITE_ERROR_ACCESS

#define DMA_CH12_CTRL_TRIG_WRITE_ERROR_ACCESS "WC"

◆ DMA_CH12_CTRL_TRIG_WRITE_ERROR_BITS

#define DMA_CH12_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000)

◆ DMA_CH12_CTRL_TRIG_WRITE_ERROR_LSB

#define DMA_CH12_CTRL_TRIG_WRITE_ERROR_LSB _u(29)

◆ DMA_CH12_CTRL_TRIG_WRITE_ERROR_MSB

#define DMA_CH12_CTRL_TRIG_WRITE_ERROR_MSB _u(29)

◆ DMA_CH12_CTRL_TRIG_WRITE_ERROR_RESET

#define DMA_CH12_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0)

◆ DMA_CH12_DBG_CTDREQ_ACCESS

#define DMA_CH12_DBG_CTDREQ_ACCESS "WC"

◆ DMA_CH12_DBG_CTDREQ_BITS

#define DMA_CH12_DBG_CTDREQ_BITS _u(0x0000003f)

◆ DMA_CH12_DBG_CTDREQ_LSB

#define DMA_CH12_DBG_CTDREQ_LSB _u(0)

◆ DMA_CH12_DBG_CTDREQ_MSB

#define DMA_CH12_DBG_CTDREQ_MSB _u(5)

◆ DMA_CH12_DBG_CTDREQ_OFFSET

#define DMA_CH12_DBG_CTDREQ_OFFSET _u(0x00000b00)

◆ DMA_CH12_DBG_CTDREQ_RESET

#define DMA_CH12_DBG_CTDREQ_RESET _u(0x00000000)

◆ DMA_CH12_DBG_TCR_ACCESS

#define DMA_CH12_DBG_TCR_ACCESS "RO"

◆ DMA_CH12_DBG_TCR_BITS

#define DMA_CH12_DBG_TCR_BITS _u(0xffffffff)

◆ DMA_CH12_DBG_TCR_LSB

#define DMA_CH12_DBG_TCR_LSB _u(0)

◆ DMA_CH12_DBG_TCR_MSB

#define DMA_CH12_DBG_TCR_MSB _u(31)

◆ DMA_CH12_DBG_TCR_OFFSET

#define DMA_CH12_DBG_TCR_OFFSET _u(0x00000b04)

◆ DMA_CH12_DBG_TCR_RESET

#define DMA_CH12_DBG_TCR_RESET _u(0x00000000)

◆ DMA_CH12_READ_ADDR_ACCESS

#define DMA_CH12_READ_ADDR_ACCESS "RW"

◆ DMA_CH12_READ_ADDR_BITS

#define DMA_CH12_READ_ADDR_BITS _u(0xffffffff)

◆ DMA_CH12_READ_ADDR_LSB

#define DMA_CH12_READ_ADDR_LSB _u(0)

◆ DMA_CH12_READ_ADDR_MSB

#define DMA_CH12_READ_ADDR_MSB _u(31)

◆ DMA_CH12_READ_ADDR_OFFSET

#define DMA_CH12_READ_ADDR_OFFSET _u(0x00000300)

◆ DMA_CH12_READ_ADDR_RESET

#define DMA_CH12_READ_ADDR_RESET _u(0x00000000)

◆ DMA_CH12_TRANS_COUNT_BITS

#define DMA_CH12_TRANS_COUNT_BITS _u(0xffffffff)

◆ DMA_CH12_TRANS_COUNT_COUNT_ACCESS

#define DMA_CH12_TRANS_COUNT_COUNT_ACCESS "RW"

◆ DMA_CH12_TRANS_COUNT_COUNT_BITS

#define DMA_CH12_TRANS_COUNT_COUNT_BITS _u(0x0fffffff)

◆ DMA_CH12_TRANS_COUNT_COUNT_LSB

#define DMA_CH12_TRANS_COUNT_COUNT_LSB _u(0)

◆ DMA_CH12_TRANS_COUNT_COUNT_MSB

#define DMA_CH12_TRANS_COUNT_COUNT_MSB _u(27)

◆ DMA_CH12_TRANS_COUNT_COUNT_RESET

#define DMA_CH12_TRANS_COUNT_COUNT_RESET _u(0x0000000)

◆ DMA_CH12_TRANS_COUNT_MODE_ACCESS

#define DMA_CH12_TRANS_COUNT_MODE_ACCESS "RW"

◆ DMA_CH12_TRANS_COUNT_MODE_BITS

#define DMA_CH12_TRANS_COUNT_MODE_BITS _u(0xf0000000)

◆ DMA_CH12_TRANS_COUNT_MODE_LSB

#define DMA_CH12_TRANS_COUNT_MODE_LSB _u(28)

◆ DMA_CH12_TRANS_COUNT_MODE_MSB

#define DMA_CH12_TRANS_COUNT_MODE_MSB _u(31)

◆ DMA_CH12_TRANS_COUNT_MODE_RESET

#define DMA_CH12_TRANS_COUNT_MODE_RESET _u(0x0)

◆ DMA_CH12_TRANS_COUNT_MODE_VALUE_ENDLESS

#define DMA_CH12_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf)

◆ DMA_CH12_TRANS_COUNT_MODE_VALUE_NORMAL

#define DMA_CH12_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0)

◆ DMA_CH12_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF

#define DMA_CH12_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1)

◆ DMA_CH12_TRANS_COUNT_OFFSET

#define DMA_CH12_TRANS_COUNT_OFFSET _u(0x00000308)

◆ DMA_CH12_TRANS_COUNT_RESET

#define DMA_CH12_TRANS_COUNT_RESET _u(0x00000000)

◆ DMA_CH12_WRITE_ADDR_ACCESS

#define DMA_CH12_WRITE_ADDR_ACCESS "RW"

◆ DMA_CH12_WRITE_ADDR_BITS

#define DMA_CH12_WRITE_ADDR_BITS _u(0xffffffff)

◆ DMA_CH12_WRITE_ADDR_LSB

#define DMA_CH12_WRITE_ADDR_LSB _u(0)

◆ DMA_CH12_WRITE_ADDR_MSB

#define DMA_CH12_WRITE_ADDR_MSB _u(31)

◆ DMA_CH12_WRITE_ADDR_OFFSET

#define DMA_CH12_WRITE_ADDR_OFFSET _u(0x00000304)

◆ DMA_CH12_WRITE_ADDR_RESET

#define DMA_CH12_WRITE_ADDR_RESET _u(0x00000000)

◆ DMA_CH13_AL1_CTRL_ACCESS

#define DMA_CH13_AL1_CTRL_ACCESS "RW"

◆ DMA_CH13_AL1_CTRL_BITS

#define DMA_CH13_AL1_CTRL_BITS _u(0xffffffff)

◆ DMA_CH13_AL1_CTRL_LSB

#define DMA_CH13_AL1_CTRL_LSB _u(0)

◆ DMA_CH13_AL1_CTRL_MSB

#define DMA_CH13_AL1_CTRL_MSB _u(31)

◆ DMA_CH13_AL1_CTRL_OFFSET

#define DMA_CH13_AL1_CTRL_OFFSET _u(0x00000350)

◆ DMA_CH13_AL1_CTRL_RESET

#define DMA_CH13_AL1_CTRL_RESET "-"

◆ DMA_CH13_AL1_READ_ADDR_ACCESS

#define DMA_CH13_AL1_READ_ADDR_ACCESS "RW"

◆ DMA_CH13_AL1_READ_ADDR_BITS

#define DMA_CH13_AL1_READ_ADDR_BITS _u(0xffffffff)

◆ DMA_CH13_AL1_READ_ADDR_LSB

#define DMA_CH13_AL1_READ_ADDR_LSB _u(0)

◆ DMA_CH13_AL1_READ_ADDR_MSB

#define DMA_CH13_AL1_READ_ADDR_MSB _u(31)

◆ DMA_CH13_AL1_READ_ADDR_OFFSET

#define DMA_CH13_AL1_READ_ADDR_OFFSET _u(0x00000354)

◆ DMA_CH13_AL1_READ_ADDR_RESET

#define DMA_CH13_AL1_READ_ADDR_RESET "-"

◆ DMA_CH13_AL1_TRANS_COUNT_TRIG_ACCESS

#define DMA_CH13_AL1_TRANS_COUNT_TRIG_ACCESS "RW"

◆ DMA_CH13_AL1_TRANS_COUNT_TRIG_BITS

#define DMA_CH13_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff)

◆ DMA_CH13_AL1_TRANS_COUNT_TRIG_LSB

#define DMA_CH13_AL1_TRANS_COUNT_TRIG_LSB _u(0)

◆ DMA_CH13_AL1_TRANS_COUNT_TRIG_MSB

#define DMA_CH13_AL1_TRANS_COUNT_TRIG_MSB _u(31)

◆ DMA_CH13_AL1_TRANS_COUNT_TRIG_OFFSET

#define DMA_CH13_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000035c)

◆ DMA_CH13_AL1_TRANS_COUNT_TRIG_RESET

#define DMA_CH13_AL1_TRANS_COUNT_TRIG_RESET "-"

◆ DMA_CH13_AL1_WRITE_ADDR_ACCESS

#define DMA_CH13_AL1_WRITE_ADDR_ACCESS "RW"

◆ DMA_CH13_AL1_WRITE_ADDR_BITS

#define DMA_CH13_AL1_WRITE_ADDR_BITS _u(0xffffffff)

◆ DMA_CH13_AL1_WRITE_ADDR_LSB

#define DMA_CH13_AL1_WRITE_ADDR_LSB _u(0)

◆ DMA_CH13_AL1_WRITE_ADDR_MSB

#define DMA_CH13_AL1_WRITE_ADDR_MSB _u(31)

◆ DMA_CH13_AL1_WRITE_ADDR_OFFSET

#define DMA_CH13_AL1_WRITE_ADDR_OFFSET _u(0x00000358)

◆ DMA_CH13_AL1_WRITE_ADDR_RESET

#define DMA_CH13_AL1_WRITE_ADDR_RESET "-"

◆ DMA_CH13_AL2_CTRL_ACCESS

#define DMA_CH13_AL2_CTRL_ACCESS "RW"

◆ DMA_CH13_AL2_CTRL_BITS

#define DMA_CH13_AL2_CTRL_BITS _u(0xffffffff)

◆ DMA_CH13_AL2_CTRL_LSB

#define DMA_CH13_AL2_CTRL_LSB _u(0)

◆ DMA_CH13_AL2_CTRL_MSB

#define DMA_CH13_AL2_CTRL_MSB _u(31)

◆ DMA_CH13_AL2_CTRL_OFFSET

#define DMA_CH13_AL2_CTRL_OFFSET _u(0x00000360)

◆ DMA_CH13_AL2_CTRL_RESET

#define DMA_CH13_AL2_CTRL_RESET "-"

◆ DMA_CH13_AL2_READ_ADDR_ACCESS

#define DMA_CH13_AL2_READ_ADDR_ACCESS "RW"

◆ DMA_CH13_AL2_READ_ADDR_BITS

#define DMA_CH13_AL2_READ_ADDR_BITS _u(0xffffffff)

◆ DMA_CH13_AL2_READ_ADDR_LSB

#define DMA_CH13_AL2_READ_ADDR_LSB _u(0)

◆ DMA_CH13_AL2_READ_ADDR_MSB

#define DMA_CH13_AL2_READ_ADDR_MSB _u(31)

◆ DMA_CH13_AL2_READ_ADDR_OFFSET

#define DMA_CH13_AL2_READ_ADDR_OFFSET _u(0x00000368)

◆ DMA_CH13_AL2_READ_ADDR_RESET

#define DMA_CH13_AL2_READ_ADDR_RESET "-"

◆ DMA_CH13_AL2_TRANS_COUNT_ACCESS

#define DMA_CH13_AL2_TRANS_COUNT_ACCESS "RW"

◆ DMA_CH13_AL2_TRANS_COUNT_BITS

#define DMA_CH13_AL2_TRANS_COUNT_BITS _u(0xffffffff)

◆ DMA_CH13_AL2_TRANS_COUNT_LSB

#define DMA_CH13_AL2_TRANS_COUNT_LSB _u(0)

◆ DMA_CH13_AL2_TRANS_COUNT_MSB

#define DMA_CH13_AL2_TRANS_COUNT_MSB _u(31)

◆ DMA_CH13_AL2_TRANS_COUNT_OFFSET

#define DMA_CH13_AL2_TRANS_COUNT_OFFSET _u(0x00000364)

◆ DMA_CH13_AL2_TRANS_COUNT_RESET

#define DMA_CH13_AL2_TRANS_COUNT_RESET "-"

◆ DMA_CH13_AL2_WRITE_ADDR_TRIG_ACCESS

#define DMA_CH13_AL2_WRITE_ADDR_TRIG_ACCESS "RW"

◆ DMA_CH13_AL2_WRITE_ADDR_TRIG_BITS

#define DMA_CH13_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff)

◆ DMA_CH13_AL2_WRITE_ADDR_TRIG_LSB

#define DMA_CH13_AL2_WRITE_ADDR_TRIG_LSB _u(0)

◆ DMA_CH13_AL2_WRITE_ADDR_TRIG_MSB

#define DMA_CH13_AL2_WRITE_ADDR_TRIG_MSB _u(31)

◆ DMA_CH13_AL2_WRITE_ADDR_TRIG_OFFSET

#define DMA_CH13_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x0000036c)

◆ DMA_CH13_AL2_WRITE_ADDR_TRIG_RESET

#define DMA_CH13_AL2_WRITE_ADDR_TRIG_RESET "-"

◆ DMA_CH13_AL3_CTRL_ACCESS

#define DMA_CH13_AL3_CTRL_ACCESS "RW"

◆ DMA_CH13_AL3_CTRL_BITS

#define DMA_CH13_AL3_CTRL_BITS _u(0xffffffff)

◆ DMA_CH13_AL3_CTRL_LSB

#define DMA_CH13_AL3_CTRL_LSB _u(0)

◆ DMA_CH13_AL3_CTRL_MSB

#define DMA_CH13_AL3_CTRL_MSB _u(31)

◆ DMA_CH13_AL3_CTRL_OFFSET

#define DMA_CH13_AL3_CTRL_OFFSET _u(0x00000370)

◆ DMA_CH13_AL3_CTRL_RESET

#define DMA_CH13_AL3_CTRL_RESET "-"

◆ DMA_CH13_AL3_READ_ADDR_TRIG_ACCESS

#define DMA_CH13_AL3_READ_ADDR_TRIG_ACCESS "RW"

◆ DMA_CH13_AL3_READ_ADDR_TRIG_BITS

#define DMA_CH13_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff)

◆ DMA_CH13_AL3_READ_ADDR_TRIG_LSB

#define DMA_CH13_AL3_READ_ADDR_TRIG_LSB _u(0)

◆ DMA_CH13_AL3_READ_ADDR_TRIG_MSB

#define DMA_CH13_AL3_READ_ADDR_TRIG_MSB _u(31)

◆ DMA_CH13_AL3_READ_ADDR_TRIG_OFFSET

#define DMA_CH13_AL3_READ_ADDR_TRIG_OFFSET _u(0x0000037c)

◆ DMA_CH13_AL3_READ_ADDR_TRIG_RESET

#define DMA_CH13_AL3_READ_ADDR_TRIG_RESET "-"

◆ DMA_CH13_AL3_TRANS_COUNT_ACCESS

#define DMA_CH13_AL3_TRANS_COUNT_ACCESS "RW"

◆ DMA_CH13_AL3_TRANS_COUNT_BITS

#define DMA_CH13_AL3_TRANS_COUNT_BITS _u(0xffffffff)

◆ DMA_CH13_AL3_TRANS_COUNT_LSB

#define DMA_CH13_AL3_TRANS_COUNT_LSB _u(0)

◆ DMA_CH13_AL3_TRANS_COUNT_MSB

#define DMA_CH13_AL3_TRANS_COUNT_MSB _u(31)

◆ DMA_CH13_AL3_TRANS_COUNT_OFFSET

#define DMA_CH13_AL3_TRANS_COUNT_OFFSET _u(0x00000378)

◆ DMA_CH13_AL3_TRANS_COUNT_RESET

#define DMA_CH13_AL3_TRANS_COUNT_RESET "-"

◆ DMA_CH13_AL3_WRITE_ADDR_ACCESS

#define DMA_CH13_AL3_WRITE_ADDR_ACCESS "RW"

◆ DMA_CH13_AL3_WRITE_ADDR_BITS

#define DMA_CH13_AL3_WRITE_ADDR_BITS _u(0xffffffff)

◆ DMA_CH13_AL3_WRITE_ADDR_LSB

#define DMA_CH13_AL3_WRITE_ADDR_LSB _u(0)

◆ DMA_CH13_AL3_WRITE_ADDR_MSB

#define DMA_CH13_AL3_WRITE_ADDR_MSB _u(31)

◆ DMA_CH13_AL3_WRITE_ADDR_OFFSET

#define DMA_CH13_AL3_WRITE_ADDR_OFFSET _u(0x00000374)

◆ DMA_CH13_AL3_WRITE_ADDR_RESET

#define DMA_CH13_AL3_WRITE_ADDR_RESET "-"

◆ DMA_CH13_CTRL_TRIG_AHB_ERROR_ACCESS

#define DMA_CH13_CTRL_TRIG_AHB_ERROR_ACCESS "RO"

◆ DMA_CH13_CTRL_TRIG_AHB_ERROR_BITS

#define DMA_CH13_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000)

◆ DMA_CH13_CTRL_TRIG_AHB_ERROR_LSB

#define DMA_CH13_CTRL_TRIG_AHB_ERROR_LSB _u(31)

◆ DMA_CH13_CTRL_TRIG_AHB_ERROR_MSB

#define DMA_CH13_CTRL_TRIG_AHB_ERROR_MSB _u(31)

◆ DMA_CH13_CTRL_TRIG_AHB_ERROR_RESET

#define DMA_CH13_CTRL_TRIG_AHB_ERROR_RESET _u(0x0)

◆ DMA_CH13_CTRL_TRIG_BITS

#define DMA_CH13_CTRL_TRIG_BITS _u(0xe7ffffff)

◆ DMA_CH13_CTRL_TRIG_BSWAP_ACCESS

#define DMA_CH13_CTRL_TRIG_BSWAP_ACCESS "RW"

◆ DMA_CH13_CTRL_TRIG_BSWAP_BITS

#define DMA_CH13_CTRL_TRIG_BSWAP_BITS _u(0x01000000)

◆ DMA_CH13_CTRL_TRIG_BSWAP_LSB

#define DMA_CH13_CTRL_TRIG_BSWAP_LSB _u(24)

◆ DMA_CH13_CTRL_TRIG_BSWAP_MSB

#define DMA_CH13_CTRL_TRIG_BSWAP_MSB _u(24)

◆ DMA_CH13_CTRL_TRIG_BSWAP_RESET

#define DMA_CH13_CTRL_TRIG_BSWAP_RESET _u(0x0)

◆ DMA_CH13_CTRL_TRIG_BUSY_ACCESS

#define DMA_CH13_CTRL_TRIG_BUSY_ACCESS "RO"

◆ DMA_CH13_CTRL_TRIG_BUSY_BITS

#define DMA_CH13_CTRL_TRIG_BUSY_BITS _u(0x04000000)

◆ DMA_CH13_CTRL_TRIG_BUSY_LSB

#define DMA_CH13_CTRL_TRIG_BUSY_LSB _u(26)

◆ DMA_CH13_CTRL_TRIG_BUSY_MSB

#define DMA_CH13_CTRL_TRIG_BUSY_MSB _u(26)

◆ DMA_CH13_CTRL_TRIG_BUSY_RESET

#define DMA_CH13_CTRL_TRIG_BUSY_RESET _u(0x0)

◆ DMA_CH13_CTRL_TRIG_CHAIN_TO_ACCESS

#define DMA_CH13_CTRL_TRIG_CHAIN_TO_ACCESS "RW"

◆ DMA_CH13_CTRL_TRIG_CHAIN_TO_BITS

#define DMA_CH13_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000)

◆ DMA_CH13_CTRL_TRIG_CHAIN_TO_LSB

#define DMA_CH13_CTRL_TRIG_CHAIN_TO_LSB _u(13)

◆ DMA_CH13_CTRL_TRIG_CHAIN_TO_MSB

#define DMA_CH13_CTRL_TRIG_CHAIN_TO_MSB _u(16)

◆ DMA_CH13_CTRL_TRIG_CHAIN_TO_RESET

#define DMA_CH13_CTRL_TRIG_CHAIN_TO_RESET _u(0x0)

◆ DMA_CH13_CTRL_TRIG_DATA_SIZE_ACCESS

#define DMA_CH13_CTRL_TRIG_DATA_SIZE_ACCESS "RW"

◆ DMA_CH13_CTRL_TRIG_DATA_SIZE_BITS

#define DMA_CH13_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c)

◆ DMA_CH13_CTRL_TRIG_DATA_SIZE_LSB

#define DMA_CH13_CTRL_TRIG_DATA_SIZE_LSB _u(2)

◆ DMA_CH13_CTRL_TRIG_DATA_SIZE_MSB

#define DMA_CH13_CTRL_TRIG_DATA_SIZE_MSB _u(3)

◆ DMA_CH13_CTRL_TRIG_DATA_SIZE_RESET

#define DMA_CH13_CTRL_TRIG_DATA_SIZE_RESET _u(0x0)

◆ DMA_CH13_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE

#define DMA_CH13_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0)

◆ DMA_CH13_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD

#define DMA_CH13_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1)

◆ DMA_CH13_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD

#define DMA_CH13_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2)

◆ DMA_CH13_CTRL_TRIG_EN_ACCESS

#define DMA_CH13_CTRL_TRIG_EN_ACCESS "RW"

◆ DMA_CH13_CTRL_TRIG_EN_BITS

#define DMA_CH13_CTRL_TRIG_EN_BITS _u(0x00000001)

◆ DMA_CH13_CTRL_TRIG_EN_LSB

#define DMA_CH13_CTRL_TRIG_EN_LSB _u(0)

◆ DMA_CH13_CTRL_TRIG_EN_MSB

#define DMA_CH13_CTRL_TRIG_EN_MSB _u(0)

◆ DMA_CH13_CTRL_TRIG_EN_RESET

#define DMA_CH13_CTRL_TRIG_EN_RESET _u(0x0)

◆ DMA_CH13_CTRL_TRIG_HIGH_PRIORITY_ACCESS

#define DMA_CH13_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW"

◆ DMA_CH13_CTRL_TRIG_HIGH_PRIORITY_BITS

#define DMA_CH13_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002)

◆ DMA_CH13_CTRL_TRIG_HIGH_PRIORITY_LSB

#define DMA_CH13_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1)

◆ DMA_CH13_CTRL_TRIG_HIGH_PRIORITY_MSB

#define DMA_CH13_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1)

◆ DMA_CH13_CTRL_TRIG_HIGH_PRIORITY_RESET

#define DMA_CH13_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0)

◆ DMA_CH13_CTRL_TRIG_INCR_READ_ACCESS

#define DMA_CH13_CTRL_TRIG_INCR_READ_ACCESS "RW"

◆ DMA_CH13_CTRL_TRIG_INCR_READ_BITS

#define DMA_CH13_CTRL_TRIG_INCR_READ_BITS _u(0x00000010)

◆ DMA_CH13_CTRL_TRIG_INCR_READ_LSB

#define DMA_CH13_CTRL_TRIG_INCR_READ_LSB _u(4)

◆ DMA_CH13_CTRL_TRIG_INCR_READ_MSB

#define DMA_CH13_CTRL_TRIG_INCR_READ_MSB _u(4)

◆ DMA_CH13_CTRL_TRIG_INCR_READ_RESET

#define DMA_CH13_CTRL_TRIG_INCR_READ_RESET _u(0x0)

◆ DMA_CH13_CTRL_TRIG_INCR_READ_REV_ACCESS

#define DMA_CH13_CTRL_TRIG_INCR_READ_REV_ACCESS "RW"

◆ DMA_CH13_CTRL_TRIG_INCR_READ_REV_BITS

#define DMA_CH13_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020)

◆ DMA_CH13_CTRL_TRIG_INCR_READ_REV_LSB

#define DMA_CH13_CTRL_TRIG_INCR_READ_REV_LSB _u(5)

◆ DMA_CH13_CTRL_TRIG_INCR_READ_REV_MSB

#define DMA_CH13_CTRL_TRIG_INCR_READ_REV_MSB _u(5)

◆ DMA_CH13_CTRL_TRIG_INCR_READ_REV_RESET

#define DMA_CH13_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0)

◆ DMA_CH13_CTRL_TRIG_INCR_WRITE_ACCESS

#define DMA_CH13_CTRL_TRIG_INCR_WRITE_ACCESS "RW"

◆ DMA_CH13_CTRL_TRIG_INCR_WRITE_BITS

#define DMA_CH13_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040)

◆ DMA_CH13_CTRL_TRIG_INCR_WRITE_LSB

#define DMA_CH13_CTRL_TRIG_INCR_WRITE_LSB _u(6)

◆ DMA_CH13_CTRL_TRIG_INCR_WRITE_MSB

#define DMA_CH13_CTRL_TRIG_INCR_WRITE_MSB _u(6)

◆ DMA_CH13_CTRL_TRIG_INCR_WRITE_RESET

#define DMA_CH13_CTRL_TRIG_INCR_WRITE_RESET _u(0x0)

◆ DMA_CH13_CTRL_TRIG_INCR_WRITE_REV_ACCESS

#define DMA_CH13_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW"

◆ DMA_CH13_CTRL_TRIG_INCR_WRITE_REV_BITS

#define DMA_CH13_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080)

◆ DMA_CH13_CTRL_TRIG_INCR_WRITE_REV_LSB

#define DMA_CH13_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7)

◆ DMA_CH13_CTRL_TRIG_INCR_WRITE_REV_MSB

#define DMA_CH13_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7)

◆ DMA_CH13_CTRL_TRIG_INCR_WRITE_REV_RESET

#define DMA_CH13_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0)

◆ DMA_CH13_CTRL_TRIG_IRQ_QUIET_ACCESS

#define DMA_CH13_CTRL_TRIG_IRQ_QUIET_ACCESS "RW"

◆ DMA_CH13_CTRL_TRIG_IRQ_QUIET_BITS

#define DMA_CH13_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000)

◆ DMA_CH13_CTRL_TRIG_IRQ_QUIET_LSB

#define DMA_CH13_CTRL_TRIG_IRQ_QUIET_LSB _u(23)

◆ DMA_CH13_CTRL_TRIG_IRQ_QUIET_MSB

#define DMA_CH13_CTRL_TRIG_IRQ_QUIET_MSB _u(23)

◆ DMA_CH13_CTRL_TRIG_IRQ_QUIET_RESET

#define DMA_CH13_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0)

◆ DMA_CH13_CTRL_TRIG_OFFSET

#define DMA_CH13_CTRL_TRIG_OFFSET _u(0x0000034c)

◆ DMA_CH13_CTRL_TRIG_READ_ERROR_ACCESS

#define DMA_CH13_CTRL_TRIG_READ_ERROR_ACCESS "WC"

◆ DMA_CH13_CTRL_TRIG_READ_ERROR_BITS

#define DMA_CH13_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000)

◆ DMA_CH13_CTRL_TRIG_READ_ERROR_LSB

#define DMA_CH13_CTRL_TRIG_READ_ERROR_LSB _u(30)

◆ DMA_CH13_CTRL_TRIG_READ_ERROR_MSB

#define DMA_CH13_CTRL_TRIG_READ_ERROR_MSB _u(30)

◆ DMA_CH13_CTRL_TRIG_READ_ERROR_RESET

#define DMA_CH13_CTRL_TRIG_READ_ERROR_RESET _u(0x0)

◆ DMA_CH13_CTRL_TRIG_RESET

#define DMA_CH13_CTRL_TRIG_RESET _u(0x00000000)

◆ DMA_CH13_CTRL_TRIG_RING_SEL_ACCESS

#define DMA_CH13_CTRL_TRIG_RING_SEL_ACCESS "RW"

◆ DMA_CH13_CTRL_TRIG_RING_SEL_BITS

#define DMA_CH13_CTRL_TRIG_RING_SEL_BITS _u(0x00001000)

◆ DMA_CH13_CTRL_TRIG_RING_SEL_LSB

#define DMA_CH13_CTRL_TRIG_RING_SEL_LSB _u(12)

◆ DMA_CH13_CTRL_TRIG_RING_SEL_MSB

#define DMA_CH13_CTRL_TRIG_RING_SEL_MSB _u(12)

◆ DMA_CH13_CTRL_TRIG_RING_SEL_RESET

#define DMA_CH13_CTRL_TRIG_RING_SEL_RESET _u(0x0)

◆ DMA_CH13_CTRL_TRIG_RING_SIZE_ACCESS

#define DMA_CH13_CTRL_TRIG_RING_SIZE_ACCESS "RW"

◆ DMA_CH13_CTRL_TRIG_RING_SIZE_BITS

#define DMA_CH13_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00)

◆ DMA_CH13_CTRL_TRIG_RING_SIZE_LSB

#define DMA_CH13_CTRL_TRIG_RING_SIZE_LSB _u(8)

◆ DMA_CH13_CTRL_TRIG_RING_SIZE_MSB

#define DMA_CH13_CTRL_TRIG_RING_SIZE_MSB _u(11)

◆ DMA_CH13_CTRL_TRIG_RING_SIZE_RESET

#define DMA_CH13_CTRL_TRIG_RING_SIZE_RESET _u(0x0)

◆ DMA_CH13_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE

#define DMA_CH13_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0)

◆ DMA_CH13_CTRL_TRIG_SNIFF_EN_ACCESS

#define DMA_CH13_CTRL_TRIG_SNIFF_EN_ACCESS "RW"

◆ DMA_CH13_CTRL_TRIG_SNIFF_EN_BITS

#define DMA_CH13_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000)

◆ DMA_CH13_CTRL_TRIG_SNIFF_EN_LSB

#define DMA_CH13_CTRL_TRIG_SNIFF_EN_LSB _u(25)

◆ DMA_CH13_CTRL_TRIG_SNIFF_EN_MSB

#define DMA_CH13_CTRL_TRIG_SNIFF_EN_MSB _u(25)

◆ DMA_CH13_CTRL_TRIG_SNIFF_EN_RESET

#define DMA_CH13_CTRL_TRIG_SNIFF_EN_RESET _u(0x0)

◆ DMA_CH13_CTRL_TRIG_TREQ_SEL_ACCESS

#define DMA_CH13_CTRL_TRIG_TREQ_SEL_ACCESS "RW"

◆ DMA_CH13_CTRL_TRIG_TREQ_SEL_BITS

#define DMA_CH13_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000)

◆ DMA_CH13_CTRL_TRIG_TREQ_SEL_LSB

#define DMA_CH13_CTRL_TRIG_TREQ_SEL_LSB _u(17)

◆ DMA_CH13_CTRL_TRIG_TREQ_SEL_MSB

#define DMA_CH13_CTRL_TRIG_TREQ_SEL_MSB _u(22)

◆ DMA_CH13_CTRL_TRIG_TREQ_SEL_RESET

#define DMA_CH13_CTRL_TRIG_TREQ_SEL_RESET _u(0x00)

◆ DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT

#define DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f)

◆ DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0

#define DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b)

◆ DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1

#define DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c)

◆ DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2

#define DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d)

◆ DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3

#define DMA_CH13_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e)

◆ DMA_CH13_CTRL_TRIG_WRITE_ERROR_ACCESS

#define DMA_CH13_CTRL_TRIG_WRITE_ERROR_ACCESS "WC"

◆ DMA_CH13_CTRL_TRIG_WRITE_ERROR_BITS

#define DMA_CH13_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000)

◆ DMA_CH13_CTRL_TRIG_WRITE_ERROR_LSB

#define DMA_CH13_CTRL_TRIG_WRITE_ERROR_LSB _u(29)

◆ DMA_CH13_CTRL_TRIG_WRITE_ERROR_MSB

#define DMA_CH13_CTRL_TRIG_WRITE_ERROR_MSB _u(29)

◆ DMA_CH13_CTRL_TRIG_WRITE_ERROR_RESET

#define DMA_CH13_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0)

◆ DMA_CH13_DBG_CTDREQ_ACCESS

#define DMA_CH13_DBG_CTDREQ_ACCESS "WC"

◆ DMA_CH13_DBG_CTDREQ_BITS

#define DMA_CH13_DBG_CTDREQ_BITS _u(0x0000003f)

◆ DMA_CH13_DBG_CTDREQ_LSB

#define DMA_CH13_DBG_CTDREQ_LSB _u(0)

◆ DMA_CH13_DBG_CTDREQ_MSB

#define DMA_CH13_DBG_CTDREQ_MSB _u(5)

◆ DMA_CH13_DBG_CTDREQ_OFFSET

#define DMA_CH13_DBG_CTDREQ_OFFSET _u(0x00000b40)

◆ DMA_CH13_DBG_CTDREQ_RESET

#define DMA_CH13_DBG_CTDREQ_RESET _u(0x00000000)

◆ DMA_CH13_DBG_TCR_ACCESS

#define DMA_CH13_DBG_TCR_ACCESS "RO"

◆ DMA_CH13_DBG_TCR_BITS

#define DMA_CH13_DBG_TCR_BITS _u(0xffffffff)

◆ DMA_CH13_DBG_TCR_LSB

#define DMA_CH13_DBG_TCR_LSB _u(0)

◆ DMA_CH13_DBG_TCR_MSB

#define DMA_CH13_DBG_TCR_MSB _u(31)

◆ DMA_CH13_DBG_TCR_OFFSET

#define DMA_CH13_DBG_TCR_OFFSET _u(0x00000b44)

◆ DMA_CH13_DBG_TCR_RESET

#define DMA_CH13_DBG_TCR_RESET _u(0x00000000)

◆ DMA_CH13_READ_ADDR_ACCESS

#define DMA_CH13_READ_ADDR_ACCESS "RW"

◆ DMA_CH13_READ_ADDR_BITS

#define DMA_CH13_READ_ADDR_BITS _u(0xffffffff)

◆ DMA_CH13_READ_ADDR_LSB

#define DMA_CH13_READ_ADDR_LSB _u(0)

◆ DMA_CH13_READ_ADDR_MSB

#define DMA_CH13_READ_ADDR_MSB _u(31)

◆ DMA_CH13_READ_ADDR_OFFSET

#define DMA_CH13_READ_ADDR_OFFSET _u(0x00000340)

◆ DMA_CH13_READ_ADDR_RESET

#define DMA_CH13_READ_ADDR_RESET _u(0x00000000)

◆ DMA_CH13_TRANS_COUNT_BITS

#define DMA_CH13_TRANS_COUNT_BITS _u(0xffffffff)

◆ DMA_CH13_TRANS_COUNT_COUNT_ACCESS

#define DMA_CH13_TRANS_COUNT_COUNT_ACCESS "RW"

◆ DMA_CH13_TRANS_COUNT_COUNT_BITS

#define DMA_CH13_TRANS_COUNT_COUNT_BITS _u(0x0fffffff)

◆ DMA_CH13_TRANS_COUNT_COUNT_LSB

#define DMA_CH13_TRANS_COUNT_COUNT_LSB _u(0)

◆ DMA_CH13_TRANS_COUNT_COUNT_MSB

#define DMA_CH13_TRANS_COUNT_COUNT_MSB _u(27)

◆ DMA_CH13_TRANS_COUNT_COUNT_RESET

#define DMA_CH13_TRANS_COUNT_COUNT_RESET _u(0x0000000)

◆ DMA_CH13_TRANS_COUNT_MODE_ACCESS

#define DMA_CH13_TRANS_COUNT_MODE_ACCESS "RW"

◆ DMA_CH13_TRANS_COUNT_MODE_BITS

#define DMA_CH13_TRANS_COUNT_MODE_BITS _u(0xf0000000)

◆ DMA_CH13_TRANS_COUNT_MODE_LSB

#define DMA_CH13_TRANS_COUNT_MODE_LSB _u(28)

◆ DMA_CH13_TRANS_COUNT_MODE_MSB

#define DMA_CH13_TRANS_COUNT_MODE_MSB _u(31)

◆ DMA_CH13_TRANS_COUNT_MODE_RESET

#define DMA_CH13_TRANS_COUNT_MODE_RESET _u(0x0)

◆ DMA_CH13_TRANS_COUNT_MODE_VALUE_ENDLESS

#define DMA_CH13_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf)

◆ DMA_CH13_TRANS_COUNT_MODE_VALUE_NORMAL

#define DMA_CH13_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0)

◆ DMA_CH13_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF

#define DMA_CH13_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1)

◆ DMA_CH13_TRANS_COUNT_OFFSET

#define DMA_CH13_TRANS_COUNT_OFFSET _u(0x00000348)

◆ DMA_CH13_TRANS_COUNT_RESET

#define DMA_CH13_TRANS_COUNT_RESET _u(0x00000000)

◆ DMA_CH13_WRITE_ADDR_ACCESS

#define DMA_CH13_WRITE_ADDR_ACCESS "RW"

◆ DMA_CH13_WRITE_ADDR_BITS

#define DMA_CH13_WRITE_ADDR_BITS _u(0xffffffff)

◆ DMA_CH13_WRITE_ADDR_LSB

#define DMA_CH13_WRITE_ADDR_LSB _u(0)

◆ DMA_CH13_WRITE_ADDR_MSB

#define DMA_CH13_WRITE_ADDR_MSB _u(31)

◆ DMA_CH13_WRITE_ADDR_OFFSET

#define DMA_CH13_WRITE_ADDR_OFFSET _u(0x00000344)

◆ DMA_CH13_WRITE_ADDR_RESET

#define DMA_CH13_WRITE_ADDR_RESET _u(0x00000000)

◆ DMA_CH14_AL1_CTRL_ACCESS

#define DMA_CH14_AL1_CTRL_ACCESS "RW"

◆ DMA_CH14_AL1_CTRL_BITS

#define DMA_CH14_AL1_CTRL_BITS _u(0xffffffff)

◆ DMA_CH14_AL1_CTRL_LSB

#define DMA_CH14_AL1_CTRL_LSB _u(0)

◆ DMA_CH14_AL1_CTRL_MSB

#define DMA_CH14_AL1_CTRL_MSB _u(31)

◆ DMA_CH14_AL1_CTRL_OFFSET

#define DMA_CH14_AL1_CTRL_OFFSET _u(0x00000390)

◆ DMA_CH14_AL1_CTRL_RESET

#define DMA_CH14_AL1_CTRL_RESET "-"

◆ DMA_CH14_AL1_READ_ADDR_ACCESS

#define DMA_CH14_AL1_READ_ADDR_ACCESS "RW"

◆ DMA_CH14_AL1_READ_ADDR_BITS

#define DMA_CH14_AL1_READ_ADDR_BITS _u(0xffffffff)

◆ DMA_CH14_AL1_READ_ADDR_LSB

#define DMA_CH14_AL1_READ_ADDR_LSB _u(0)

◆ DMA_CH14_AL1_READ_ADDR_MSB

#define DMA_CH14_AL1_READ_ADDR_MSB _u(31)

◆ DMA_CH14_AL1_READ_ADDR_OFFSET

#define DMA_CH14_AL1_READ_ADDR_OFFSET _u(0x00000394)

◆ DMA_CH14_AL1_READ_ADDR_RESET

#define DMA_CH14_AL1_READ_ADDR_RESET "-"

◆ DMA_CH14_AL1_TRANS_COUNT_TRIG_ACCESS

#define DMA_CH14_AL1_TRANS_COUNT_TRIG_ACCESS "RW"

◆ DMA_CH14_AL1_TRANS_COUNT_TRIG_BITS

#define DMA_CH14_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff)

◆ DMA_CH14_AL1_TRANS_COUNT_TRIG_LSB

#define DMA_CH14_AL1_TRANS_COUNT_TRIG_LSB _u(0)

◆ DMA_CH14_AL1_TRANS_COUNT_TRIG_MSB

#define DMA_CH14_AL1_TRANS_COUNT_TRIG_MSB _u(31)

◆ DMA_CH14_AL1_TRANS_COUNT_TRIG_OFFSET

#define DMA_CH14_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000039c)

◆ DMA_CH14_AL1_TRANS_COUNT_TRIG_RESET

#define DMA_CH14_AL1_TRANS_COUNT_TRIG_RESET "-"

◆ DMA_CH14_AL1_WRITE_ADDR_ACCESS

#define DMA_CH14_AL1_WRITE_ADDR_ACCESS "RW"

◆ DMA_CH14_AL1_WRITE_ADDR_BITS

#define DMA_CH14_AL1_WRITE_ADDR_BITS _u(0xffffffff)

◆ DMA_CH14_AL1_WRITE_ADDR_LSB

#define DMA_CH14_AL1_WRITE_ADDR_LSB _u(0)

◆ DMA_CH14_AL1_WRITE_ADDR_MSB

#define DMA_CH14_AL1_WRITE_ADDR_MSB _u(31)

◆ DMA_CH14_AL1_WRITE_ADDR_OFFSET

#define DMA_CH14_AL1_WRITE_ADDR_OFFSET _u(0x00000398)

◆ DMA_CH14_AL1_WRITE_ADDR_RESET

#define DMA_CH14_AL1_WRITE_ADDR_RESET "-"

◆ DMA_CH14_AL2_CTRL_ACCESS

#define DMA_CH14_AL2_CTRL_ACCESS "RW"

◆ DMA_CH14_AL2_CTRL_BITS

#define DMA_CH14_AL2_CTRL_BITS _u(0xffffffff)

◆ DMA_CH14_AL2_CTRL_LSB

#define DMA_CH14_AL2_CTRL_LSB _u(0)

◆ DMA_CH14_AL2_CTRL_MSB

#define DMA_CH14_AL2_CTRL_MSB _u(31)

◆ DMA_CH14_AL2_CTRL_OFFSET

#define DMA_CH14_AL2_CTRL_OFFSET _u(0x000003a0)

◆ DMA_CH14_AL2_CTRL_RESET

#define DMA_CH14_AL2_CTRL_RESET "-"

◆ DMA_CH14_AL2_READ_ADDR_ACCESS

#define DMA_CH14_AL2_READ_ADDR_ACCESS "RW"

◆ DMA_CH14_AL2_READ_ADDR_BITS

#define DMA_CH14_AL2_READ_ADDR_BITS _u(0xffffffff)

◆ DMA_CH14_AL2_READ_ADDR_LSB

#define DMA_CH14_AL2_READ_ADDR_LSB _u(0)

◆ DMA_CH14_AL2_READ_ADDR_MSB

#define DMA_CH14_AL2_READ_ADDR_MSB _u(31)

◆ DMA_CH14_AL2_READ_ADDR_OFFSET

#define DMA_CH14_AL2_READ_ADDR_OFFSET _u(0x000003a8)

◆ DMA_CH14_AL2_READ_ADDR_RESET

#define DMA_CH14_AL2_READ_ADDR_RESET "-"

◆ DMA_CH14_AL2_TRANS_COUNT_ACCESS

#define DMA_CH14_AL2_TRANS_COUNT_ACCESS "RW"

◆ DMA_CH14_AL2_TRANS_COUNT_BITS

#define DMA_CH14_AL2_TRANS_COUNT_BITS _u(0xffffffff)

◆ DMA_CH14_AL2_TRANS_COUNT_LSB

#define DMA_CH14_AL2_TRANS_COUNT_LSB _u(0)

◆ DMA_CH14_AL2_TRANS_COUNT_MSB

#define DMA_CH14_AL2_TRANS_COUNT_MSB _u(31)

◆ DMA_CH14_AL2_TRANS_COUNT_OFFSET

#define DMA_CH14_AL2_TRANS_COUNT_OFFSET _u(0x000003a4)

◆ DMA_CH14_AL2_TRANS_COUNT_RESET

#define DMA_CH14_AL2_TRANS_COUNT_RESET "-"

◆ DMA_CH14_AL2_WRITE_ADDR_TRIG_ACCESS

#define DMA_CH14_AL2_WRITE_ADDR_TRIG_ACCESS "RW"

◆ DMA_CH14_AL2_WRITE_ADDR_TRIG_BITS

#define DMA_CH14_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff)

◆ DMA_CH14_AL2_WRITE_ADDR_TRIG_LSB

#define DMA_CH14_AL2_WRITE_ADDR_TRIG_LSB _u(0)

◆ DMA_CH14_AL2_WRITE_ADDR_TRIG_MSB

#define DMA_CH14_AL2_WRITE_ADDR_TRIG_MSB _u(31)

◆ DMA_CH14_AL2_WRITE_ADDR_TRIG_OFFSET

#define DMA_CH14_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x000003ac)

◆ DMA_CH14_AL2_WRITE_ADDR_TRIG_RESET

#define DMA_CH14_AL2_WRITE_ADDR_TRIG_RESET "-"

◆ DMA_CH14_AL3_CTRL_ACCESS

#define DMA_CH14_AL3_CTRL_ACCESS "RW"

◆ DMA_CH14_AL3_CTRL_BITS

#define DMA_CH14_AL3_CTRL_BITS _u(0xffffffff)

◆ DMA_CH14_AL3_CTRL_LSB

#define DMA_CH14_AL3_CTRL_LSB _u(0)

◆ DMA_CH14_AL3_CTRL_MSB

#define DMA_CH14_AL3_CTRL_MSB _u(31)

◆ DMA_CH14_AL3_CTRL_OFFSET

#define DMA_CH14_AL3_CTRL_OFFSET _u(0x000003b0)

◆ DMA_CH14_AL3_CTRL_RESET

#define DMA_CH14_AL3_CTRL_RESET "-"

◆ DMA_CH14_AL3_READ_ADDR_TRIG_ACCESS

#define DMA_CH14_AL3_READ_ADDR_TRIG_ACCESS "RW"

◆ DMA_CH14_AL3_READ_ADDR_TRIG_BITS

#define DMA_CH14_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff)

◆ DMA_CH14_AL3_READ_ADDR_TRIG_LSB

#define DMA_CH14_AL3_READ_ADDR_TRIG_LSB _u(0)

◆ DMA_CH14_AL3_READ_ADDR_TRIG_MSB

#define DMA_CH14_AL3_READ_ADDR_TRIG_MSB _u(31)

◆ DMA_CH14_AL3_READ_ADDR_TRIG_OFFSET

#define DMA_CH14_AL3_READ_ADDR_TRIG_OFFSET _u(0x000003bc)

◆ DMA_CH14_AL3_READ_ADDR_TRIG_RESET

#define DMA_CH14_AL3_READ_ADDR_TRIG_RESET "-"

◆ DMA_CH14_AL3_TRANS_COUNT_ACCESS

#define DMA_CH14_AL3_TRANS_COUNT_ACCESS "RW"

◆ DMA_CH14_AL3_TRANS_COUNT_BITS

#define DMA_CH14_AL3_TRANS_COUNT_BITS _u(0xffffffff)

◆ DMA_CH14_AL3_TRANS_COUNT_LSB

#define DMA_CH14_AL3_TRANS_COUNT_LSB _u(0)

◆ DMA_CH14_AL3_TRANS_COUNT_MSB

#define DMA_CH14_AL3_TRANS_COUNT_MSB _u(31)

◆ DMA_CH14_AL3_TRANS_COUNT_OFFSET

#define DMA_CH14_AL3_TRANS_COUNT_OFFSET _u(0x000003b8)

◆ DMA_CH14_AL3_TRANS_COUNT_RESET

#define DMA_CH14_AL3_TRANS_COUNT_RESET "-"

◆ DMA_CH14_AL3_WRITE_ADDR_ACCESS

#define DMA_CH14_AL3_WRITE_ADDR_ACCESS "RW"

◆ DMA_CH14_AL3_WRITE_ADDR_BITS

#define DMA_CH14_AL3_WRITE_ADDR_BITS _u(0xffffffff)

◆ DMA_CH14_AL3_WRITE_ADDR_LSB

#define DMA_CH14_AL3_WRITE_ADDR_LSB _u(0)

◆ DMA_CH14_AL3_WRITE_ADDR_MSB

#define DMA_CH14_AL3_WRITE_ADDR_MSB _u(31)

◆ DMA_CH14_AL3_WRITE_ADDR_OFFSET

#define DMA_CH14_AL3_WRITE_ADDR_OFFSET _u(0x000003b4)

◆ DMA_CH14_AL3_WRITE_ADDR_RESET

#define DMA_CH14_AL3_WRITE_ADDR_RESET "-"

◆ DMA_CH14_CTRL_TRIG_AHB_ERROR_ACCESS

#define DMA_CH14_CTRL_TRIG_AHB_ERROR_ACCESS "RO"

◆ DMA_CH14_CTRL_TRIG_AHB_ERROR_BITS

#define DMA_CH14_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000)

◆ DMA_CH14_CTRL_TRIG_AHB_ERROR_LSB

#define DMA_CH14_CTRL_TRIG_AHB_ERROR_LSB _u(31)

◆ DMA_CH14_CTRL_TRIG_AHB_ERROR_MSB

#define DMA_CH14_CTRL_TRIG_AHB_ERROR_MSB _u(31)

◆ DMA_CH14_CTRL_TRIG_AHB_ERROR_RESET

#define DMA_CH14_CTRL_TRIG_AHB_ERROR_RESET _u(0x0)

◆ DMA_CH14_CTRL_TRIG_BITS

#define DMA_CH14_CTRL_TRIG_BITS _u(0xe7ffffff)

◆ DMA_CH14_CTRL_TRIG_BSWAP_ACCESS

#define DMA_CH14_CTRL_TRIG_BSWAP_ACCESS "RW"

◆ DMA_CH14_CTRL_TRIG_BSWAP_BITS

#define DMA_CH14_CTRL_TRIG_BSWAP_BITS _u(0x01000000)

◆ DMA_CH14_CTRL_TRIG_BSWAP_LSB

#define DMA_CH14_CTRL_TRIG_BSWAP_LSB _u(24)

◆ DMA_CH14_CTRL_TRIG_BSWAP_MSB

#define DMA_CH14_CTRL_TRIG_BSWAP_MSB _u(24)

◆ DMA_CH14_CTRL_TRIG_BSWAP_RESET

#define DMA_CH14_CTRL_TRIG_BSWAP_RESET _u(0x0)

◆ DMA_CH14_CTRL_TRIG_BUSY_ACCESS

#define DMA_CH14_CTRL_TRIG_BUSY_ACCESS "RO"

◆ DMA_CH14_CTRL_TRIG_BUSY_BITS

#define DMA_CH14_CTRL_TRIG_BUSY_BITS _u(0x04000000)

◆ DMA_CH14_CTRL_TRIG_BUSY_LSB

#define DMA_CH14_CTRL_TRIG_BUSY_LSB _u(26)

◆ DMA_CH14_CTRL_TRIG_BUSY_MSB

#define DMA_CH14_CTRL_TRIG_BUSY_MSB _u(26)

◆ DMA_CH14_CTRL_TRIG_BUSY_RESET

#define DMA_CH14_CTRL_TRIG_BUSY_RESET _u(0x0)

◆ DMA_CH14_CTRL_TRIG_CHAIN_TO_ACCESS

#define DMA_CH14_CTRL_TRIG_CHAIN_TO_ACCESS "RW"

◆ DMA_CH14_CTRL_TRIG_CHAIN_TO_BITS

#define DMA_CH14_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000)

◆ DMA_CH14_CTRL_TRIG_CHAIN_TO_LSB

#define DMA_CH14_CTRL_TRIG_CHAIN_TO_LSB _u(13)

◆ DMA_CH14_CTRL_TRIG_CHAIN_TO_MSB

#define DMA_CH14_CTRL_TRIG_CHAIN_TO_MSB _u(16)

◆ DMA_CH14_CTRL_TRIG_CHAIN_TO_RESET

#define DMA_CH14_CTRL_TRIG_CHAIN_TO_RESET _u(0x0)

◆ DMA_CH14_CTRL_TRIG_DATA_SIZE_ACCESS

#define DMA_CH14_CTRL_TRIG_DATA_SIZE_ACCESS "RW"

◆ DMA_CH14_CTRL_TRIG_DATA_SIZE_BITS

#define DMA_CH14_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c)

◆ DMA_CH14_CTRL_TRIG_DATA_SIZE_LSB

#define DMA_CH14_CTRL_TRIG_DATA_SIZE_LSB _u(2)

◆ DMA_CH14_CTRL_TRIG_DATA_SIZE_MSB

#define DMA_CH14_CTRL_TRIG_DATA_SIZE_MSB _u(3)

◆ DMA_CH14_CTRL_TRIG_DATA_SIZE_RESET

#define DMA_CH14_CTRL_TRIG_DATA_SIZE_RESET _u(0x0)

◆ DMA_CH14_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE

#define DMA_CH14_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0)

◆ DMA_CH14_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD

#define DMA_CH14_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1)

◆ DMA_CH14_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD

#define DMA_CH14_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2)

◆ DMA_CH14_CTRL_TRIG_EN_ACCESS

#define DMA_CH14_CTRL_TRIG_EN_ACCESS "RW"

◆ DMA_CH14_CTRL_TRIG_EN_BITS

#define DMA_CH14_CTRL_TRIG_EN_BITS _u(0x00000001)

◆ DMA_CH14_CTRL_TRIG_EN_LSB

#define DMA_CH14_CTRL_TRIG_EN_LSB _u(0)

◆ DMA_CH14_CTRL_TRIG_EN_MSB

#define DMA_CH14_CTRL_TRIG_EN_MSB _u(0)

◆ DMA_CH14_CTRL_TRIG_EN_RESET

#define DMA_CH14_CTRL_TRIG_EN_RESET _u(0x0)

◆ DMA_CH14_CTRL_TRIG_HIGH_PRIORITY_ACCESS

#define DMA_CH14_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW"

◆ DMA_CH14_CTRL_TRIG_HIGH_PRIORITY_BITS

#define DMA_CH14_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002)

◆ DMA_CH14_CTRL_TRIG_HIGH_PRIORITY_LSB

#define DMA_CH14_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1)

◆ DMA_CH14_CTRL_TRIG_HIGH_PRIORITY_MSB

#define DMA_CH14_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1)

◆ DMA_CH14_CTRL_TRIG_HIGH_PRIORITY_RESET

#define DMA_CH14_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0)

◆ DMA_CH14_CTRL_TRIG_INCR_READ_ACCESS

#define DMA_CH14_CTRL_TRIG_INCR_READ_ACCESS "RW"

◆ DMA_CH14_CTRL_TRIG_INCR_READ_BITS

#define DMA_CH14_CTRL_TRIG_INCR_READ_BITS _u(0x00000010)

◆ DMA_CH14_CTRL_TRIG_INCR_READ_LSB

#define DMA_CH14_CTRL_TRIG_INCR_READ_LSB _u(4)

◆ DMA_CH14_CTRL_TRIG_INCR_READ_MSB

#define DMA_CH14_CTRL_TRIG_INCR_READ_MSB _u(4)

◆ DMA_CH14_CTRL_TRIG_INCR_READ_RESET

#define DMA_CH14_CTRL_TRIG_INCR_READ_RESET _u(0x0)

◆ DMA_CH14_CTRL_TRIG_INCR_READ_REV_ACCESS

#define DMA_CH14_CTRL_TRIG_INCR_READ_REV_ACCESS "RW"

◆ DMA_CH14_CTRL_TRIG_INCR_READ_REV_BITS

#define DMA_CH14_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020)

◆ DMA_CH14_CTRL_TRIG_INCR_READ_REV_LSB

#define DMA_CH14_CTRL_TRIG_INCR_READ_REV_LSB _u(5)

◆ DMA_CH14_CTRL_TRIG_INCR_READ_REV_MSB

#define DMA_CH14_CTRL_TRIG_INCR_READ_REV_MSB _u(5)

◆ DMA_CH14_CTRL_TRIG_INCR_READ_REV_RESET

#define DMA_CH14_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0)

◆ DMA_CH14_CTRL_TRIG_INCR_WRITE_ACCESS

#define DMA_CH14_CTRL_TRIG_INCR_WRITE_ACCESS "RW"

◆ DMA_CH14_CTRL_TRIG_INCR_WRITE_BITS

#define DMA_CH14_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040)

◆ DMA_CH14_CTRL_TRIG_INCR_WRITE_LSB

#define DMA_CH14_CTRL_TRIG_INCR_WRITE_LSB _u(6)

◆ DMA_CH14_CTRL_TRIG_INCR_WRITE_MSB

#define DMA_CH14_CTRL_TRIG_INCR_WRITE_MSB _u(6)

◆ DMA_CH14_CTRL_TRIG_INCR_WRITE_RESET

#define DMA_CH14_CTRL_TRIG_INCR_WRITE_RESET _u(0x0)

◆ DMA_CH14_CTRL_TRIG_INCR_WRITE_REV_ACCESS

#define DMA_CH14_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW"

◆ DMA_CH14_CTRL_TRIG_INCR_WRITE_REV_BITS

#define DMA_CH14_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080)

◆ DMA_CH14_CTRL_TRIG_INCR_WRITE_REV_LSB

#define DMA_CH14_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7)

◆ DMA_CH14_CTRL_TRIG_INCR_WRITE_REV_MSB

#define DMA_CH14_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7)

◆ DMA_CH14_CTRL_TRIG_INCR_WRITE_REV_RESET

#define DMA_CH14_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0)

◆ DMA_CH14_CTRL_TRIG_IRQ_QUIET_ACCESS

#define DMA_CH14_CTRL_TRIG_IRQ_QUIET_ACCESS "RW"

◆ DMA_CH14_CTRL_TRIG_IRQ_QUIET_BITS

#define DMA_CH14_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000)

◆ DMA_CH14_CTRL_TRIG_IRQ_QUIET_LSB

#define DMA_CH14_CTRL_TRIG_IRQ_QUIET_LSB _u(23)

◆ DMA_CH14_CTRL_TRIG_IRQ_QUIET_MSB

#define DMA_CH14_CTRL_TRIG_IRQ_QUIET_MSB _u(23)

◆ DMA_CH14_CTRL_TRIG_IRQ_QUIET_RESET

#define DMA_CH14_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0)

◆ DMA_CH14_CTRL_TRIG_OFFSET

#define DMA_CH14_CTRL_TRIG_OFFSET _u(0x0000038c)

◆ DMA_CH14_CTRL_TRIG_READ_ERROR_ACCESS

#define DMA_CH14_CTRL_TRIG_READ_ERROR_ACCESS "WC"

◆ DMA_CH14_CTRL_TRIG_READ_ERROR_BITS

#define DMA_CH14_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000)

◆ DMA_CH14_CTRL_TRIG_READ_ERROR_LSB

#define DMA_CH14_CTRL_TRIG_READ_ERROR_LSB _u(30)

◆ DMA_CH14_CTRL_TRIG_READ_ERROR_MSB

#define DMA_CH14_CTRL_TRIG_READ_ERROR_MSB _u(30)

◆ DMA_CH14_CTRL_TRIG_READ_ERROR_RESET

#define DMA_CH14_CTRL_TRIG_READ_ERROR_RESET _u(0x0)

◆ DMA_CH14_CTRL_TRIG_RESET

#define DMA_CH14_CTRL_TRIG_RESET _u(0x00000000)

◆ DMA_CH14_CTRL_TRIG_RING_SEL_ACCESS

#define DMA_CH14_CTRL_TRIG_RING_SEL_ACCESS "RW"

◆ DMA_CH14_CTRL_TRIG_RING_SEL_BITS

#define DMA_CH14_CTRL_TRIG_RING_SEL_BITS _u(0x00001000)

◆ DMA_CH14_CTRL_TRIG_RING_SEL_LSB

#define DMA_CH14_CTRL_TRIG_RING_SEL_LSB _u(12)

◆ DMA_CH14_CTRL_TRIG_RING_SEL_MSB

#define DMA_CH14_CTRL_TRIG_RING_SEL_MSB _u(12)

◆ DMA_CH14_CTRL_TRIG_RING_SEL_RESET

#define DMA_CH14_CTRL_TRIG_RING_SEL_RESET _u(0x0)

◆ DMA_CH14_CTRL_TRIG_RING_SIZE_ACCESS

#define DMA_CH14_CTRL_TRIG_RING_SIZE_ACCESS "RW"

◆ DMA_CH14_CTRL_TRIG_RING_SIZE_BITS

#define DMA_CH14_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00)

◆ DMA_CH14_CTRL_TRIG_RING_SIZE_LSB

#define DMA_CH14_CTRL_TRIG_RING_SIZE_LSB _u(8)

◆ DMA_CH14_CTRL_TRIG_RING_SIZE_MSB

#define DMA_CH14_CTRL_TRIG_RING_SIZE_MSB _u(11)

◆ DMA_CH14_CTRL_TRIG_RING_SIZE_RESET

#define DMA_CH14_CTRL_TRIG_RING_SIZE_RESET _u(0x0)

◆ DMA_CH14_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE

#define DMA_CH14_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0)

◆ DMA_CH14_CTRL_TRIG_SNIFF_EN_ACCESS

#define DMA_CH14_CTRL_TRIG_SNIFF_EN_ACCESS "RW"

◆ DMA_CH14_CTRL_TRIG_SNIFF_EN_BITS

#define DMA_CH14_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000)

◆ DMA_CH14_CTRL_TRIG_SNIFF_EN_LSB

#define DMA_CH14_CTRL_TRIG_SNIFF_EN_LSB _u(25)

◆ DMA_CH14_CTRL_TRIG_SNIFF_EN_MSB

#define DMA_CH14_CTRL_TRIG_SNIFF_EN_MSB _u(25)

◆ DMA_CH14_CTRL_TRIG_SNIFF_EN_RESET

#define DMA_CH14_CTRL_TRIG_SNIFF_EN_RESET _u(0x0)

◆ DMA_CH14_CTRL_TRIG_TREQ_SEL_ACCESS

#define DMA_CH14_CTRL_TRIG_TREQ_SEL_ACCESS "RW"

◆ DMA_CH14_CTRL_TRIG_TREQ_SEL_BITS

#define DMA_CH14_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000)

◆ DMA_CH14_CTRL_TRIG_TREQ_SEL_LSB

#define DMA_CH14_CTRL_TRIG_TREQ_SEL_LSB _u(17)

◆ DMA_CH14_CTRL_TRIG_TREQ_SEL_MSB

#define DMA_CH14_CTRL_TRIG_TREQ_SEL_MSB _u(22)

◆ DMA_CH14_CTRL_TRIG_TREQ_SEL_RESET

#define DMA_CH14_CTRL_TRIG_TREQ_SEL_RESET _u(0x00)

◆ DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT

#define DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f)

◆ DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0

#define DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b)

◆ DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1

#define DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c)

◆ DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2

#define DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d)

◆ DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3

#define DMA_CH14_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e)

◆ DMA_CH14_CTRL_TRIG_WRITE_ERROR_ACCESS

#define DMA_CH14_CTRL_TRIG_WRITE_ERROR_ACCESS "WC"

◆ DMA_CH14_CTRL_TRIG_WRITE_ERROR_BITS

#define DMA_CH14_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000)

◆ DMA_CH14_CTRL_TRIG_WRITE_ERROR_LSB

#define DMA_CH14_CTRL_TRIG_WRITE_ERROR_LSB _u(29)

◆ DMA_CH14_CTRL_TRIG_WRITE_ERROR_MSB

#define DMA_CH14_CTRL_TRIG_WRITE_ERROR_MSB _u(29)

◆ DMA_CH14_CTRL_TRIG_WRITE_ERROR_RESET

#define DMA_CH14_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0)

◆ DMA_CH14_DBG_CTDREQ_ACCESS

#define DMA_CH14_DBG_CTDREQ_ACCESS "WC"

◆ DMA_CH14_DBG_CTDREQ_BITS

#define DMA_CH14_DBG_CTDREQ_BITS _u(0x0000003f)

◆ DMA_CH14_DBG_CTDREQ_LSB

#define DMA_CH14_DBG_CTDREQ_LSB _u(0)

◆ DMA_CH14_DBG_CTDREQ_MSB

#define DMA_CH14_DBG_CTDREQ_MSB _u(5)

◆ DMA_CH14_DBG_CTDREQ_OFFSET

#define DMA_CH14_DBG_CTDREQ_OFFSET _u(0x00000b80)

◆ DMA_CH14_DBG_CTDREQ_RESET

#define DMA_CH14_DBG_CTDREQ_RESET _u(0x00000000)

◆ DMA_CH14_DBG_TCR_ACCESS

#define DMA_CH14_DBG_TCR_ACCESS "RO"

◆ DMA_CH14_DBG_TCR_BITS

#define DMA_CH14_DBG_TCR_BITS _u(0xffffffff)

◆ DMA_CH14_DBG_TCR_LSB

#define DMA_CH14_DBG_TCR_LSB _u(0)

◆ DMA_CH14_DBG_TCR_MSB

#define DMA_CH14_DBG_TCR_MSB _u(31)

◆ DMA_CH14_DBG_TCR_OFFSET

#define DMA_CH14_DBG_TCR_OFFSET _u(0x00000b84)

◆ DMA_CH14_DBG_TCR_RESET

#define DMA_CH14_DBG_TCR_RESET _u(0x00000000)

◆ DMA_CH14_READ_ADDR_ACCESS

#define DMA_CH14_READ_ADDR_ACCESS "RW"

◆ DMA_CH14_READ_ADDR_BITS

#define DMA_CH14_READ_ADDR_BITS _u(0xffffffff)

◆ DMA_CH14_READ_ADDR_LSB

#define DMA_CH14_READ_ADDR_LSB _u(0)

◆ DMA_CH14_READ_ADDR_MSB

#define DMA_CH14_READ_ADDR_MSB _u(31)

◆ DMA_CH14_READ_ADDR_OFFSET

#define DMA_CH14_READ_ADDR_OFFSET _u(0x00000380)

◆ DMA_CH14_READ_ADDR_RESET

#define DMA_CH14_READ_ADDR_RESET _u(0x00000000)

◆ DMA_CH14_TRANS_COUNT_BITS

#define DMA_CH14_TRANS_COUNT_BITS _u(0xffffffff)

◆ DMA_CH14_TRANS_COUNT_COUNT_ACCESS

#define DMA_CH14_TRANS_COUNT_COUNT_ACCESS "RW"

◆ DMA_CH14_TRANS_COUNT_COUNT_BITS

#define DMA_CH14_TRANS_COUNT_COUNT_BITS _u(0x0fffffff)

◆ DMA_CH14_TRANS_COUNT_COUNT_LSB

#define DMA_CH14_TRANS_COUNT_COUNT_LSB _u(0)

◆ DMA_CH14_TRANS_COUNT_COUNT_MSB

#define DMA_CH14_TRANS_COUNT_COUNT_MSB _u(27)

◆ DMA_CH14_TRANS_COUNT_COUNT_RESET

#define DMA_CH14_TRANS_COUNT_COUNT_RESET _u(0x0000000)

◆ DMA_CH14_TRANS_COUNT_MODE_ACCESS

#define DMA_CH14_TRANS_COUNT_MODE_ACCESS "RW"

◆ DMA_CH14_TRANS_COUNT_MODE_BITS

#define DMA_CH14_TRANS_COUNT_MODE_BITS _u(0xf0000000)

◆ DMA_CH14_TRANS_COUNT_MODE_LSB

#define DMA_CH14_TRANS_COUNT_MODE_LSB _u(28)

◆ DMA_CH14_TRANS_COUNT_MODE_MSB

#define DMA_CH14_TRANS_COUNT_MODE_MSB _u(31)

◆ DMA_CH14_TRANS_COUNT_MODE_RESET

#define DMA_CH14_TRANS_COUNT_MODE_RESET _u(0x0)

◆ DMA_CH14_TRANS_COUNT_MODE_VALUE_ENDLESS

#define DMA_CH14_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf)

◆ DMA_CH14_TRANS_COUNT_MODE_VALUE_NORMAL

#define DMA_CH14_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0)

◆ DMA_CH14_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF

#define DMA_CH14_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1)

◆ DMA_CH14_TRANS_COUNT_OFFSET

#define DMA_CH14_TRANS_COUNT_OFFSET _u(0x00000388)

◆ DMA_CH14_TRANS_COUNT_RESET

#define DMA_CH14_TRANS_COUNT_RESET _u(0x00000000)

◆ DMA_CH14_WRITE_ADDR_ACCESS

#define DMA_CH14_WRITE_ADDR_ACCESS "RW"

◆ DMA_CH14_WRITE_ADDR_BITS

#define DMA_CH14_WRITE_ADDR_BITS _u(0xffffffff)

◆ DMA_CH14_WRITE_ADDR_LSB

#define DMA_CH14_WRITE_ADDR_LSB _u(0)

◆ DMA_CH14_WRITE_ADDR_MSB

#define DMA_CH14_WRITE_ADDR_MSB _u(31)

◆ DMA_CH14_WRITE_ADDR_OFFSET

#define DMA_CH14_WRITE_ADDR_OFFSET _u(0x00000384)

◆ DMA_CH14_WRITE_ADDR_RESET

#define DMA_CH14_WRITE_ADDR_RESET _u(0x00000000)

◆ DMA_CH15_AL1_CTRL_ACCESS

#define DMA_CH15_AL1_CTRL_ACCESS "RW"

◆ DMA_CH15_AL1_CTRL_BITS

#define DMA_CH15_AL1_CTRL_BITS _u(0xffffffff)

◆ DMA_CH15_AL1_CTRL_LSB

#define DMA_CH15_AL1_CTRL_LSB _u(0)

◆ DMA_CH15_AL1_CTRL_MSB

#define DMA_CH15_AL1_CTRL_MSB _u(31)

◆ DMA_CH15_AL1_CTRL_OFFSET

#define DMA_CH15_AL1_CTRL_OFFSET _u(0x000003d0)

◆ DMA_CH15_AL1_CTRL_RESET

#define DMA_CH15_AL1_CTRL_RESET "-"

◆ DMA_CH15_AL1_READ_ADDR_ACCESS

#define DMA_CH15_AL1_READ_ADDR_ACCESS "RW"

◆ DMA_CH15_AL1_READ_ADDR_BITS

#define DMA_CH15_AL1_READ_ADDR_BITS _u(0xffffffff)

◆ DMA_CH15_AL1_READ_ADDR_LSB

#define DMA_CH15_AL1_READ_ADDR_LSB _u(0)

◆ DMA_CH15_AL1_READ_ADDR_MSB

#define DMA_CH15_AL1_READ_ADDR_MSB _u(31)

◆ DMA_CH15_AL1_READ_ADDR_OFFSET

#define DMA_CH15_AL1_READ_ADDR_OFFSET _u(0x000003d4)

◆ DMA_CH15_AL1_READ_ADDR_RESET

#define DMA_CH15_AL1_READ_ADDR_RESET "-"

◆ DMA_CH15_AL1_TRANS_COUNT_TRIG_ACCESS

#define DMA_CH15_AL1_TRANS_COUNT_TRIG_ACCESS "RW"

◆ DMA_CH15_AL1_TRANS_COUNT_TRIG_BITS

#define DMA_CH15_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff)

◆ DMA_CH15_AL1_TRANS_COUNT_TRIG_LSB

#define DMA_CH15_AL1_TRANS_COUNT_TRIG_LSB _u(0)

◆ DMA_CH15_AL1_TRANS_COUNT_TRIG_MSB

#define DMA_CH15_AL1_TRANS_COUNT_TRIG_MSB _u(31)

◆ DMA_CH15_AL1_TRANS_COUNT_TRIG_OFFSET

#define DMA_CH15_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x000003dc)

◆ DMA_CH15_AL1_TRANS_COUNT_TRIG_RESET

#define DMA_CH15_AL1_TRANS_COUNT_TRIG_RESET "-"

◆ DMA_CH15_AL1_WRITE_ADDR_ACCESS

#define DMA_CH15_AL1_WRITE_ADDR_ACCESS "RW"

◆ DMA_CH15_AL1_WRITE_ADDR_BITS

#define DMA_CH15_AL1_WRITE_ADDR_BITS _u(0xffffffff)

◆ DMA_CH15_AL1_WRITE_ADDR_LSB

#define DMA_CH15_AL1_WRITE_ADDR_LSB _u(0)

◆ DMA_CH15_AL1_WRITE_ADDR_MSB

#define DMA_CH15_AL1_WRITE_ADDR_MSB _u(31)

◆ DMA_CH15_AL1_WRITE_ADDR_OFFSET

#define DMA_CH15_AL1_WRITE_ADDR_OFFSET _u(0x000003d8)

◆ DMA_CH15_AL1_WRITE_ADDR_RESET

#define DMA_CH15_AL1_WRITE_ADDR_RESET "-"

◆ DMA_CH15_AL2_CTRL_ACCESS

#define DMA_CH15_AL2_CTRL_ACCESS "RW"

◆ DMA_CH15_AL2_CTRL_BITS

#define DMA_CH15_AL2_CTRL_BITS _u(0xffffffff)

◆ DMA_CH15_AL2_CTRL_LSB

#define DMA_CH15_AL2_CTRL_LSB _u(0)

◆ DMA_CH15_AL2_CTRL_MSB

#define DMA_CH15_AL2_CTRL_MSB _u(31)

◆ DMA_CH15_AL2_CTRL_OFFSET

#define DMA_CH15_AL2_CTRL_OFFSET _u(0x000003e0)

◆ DMA_CH15_AL2_CTRL_RESET

#define DMA_CH15_AL2_CTRL_RESET "-"

◆ DMA_CH15_AL2_READ_ADDR_ACCESS

#define DMA_CH15_AL2_READ_ADDR_ACCESS "RW"

◆ DMA_CH15_AL2_READ_ADDR_BITS

#define DMA_CH15_AL2_READ_ADDR_BITS _u(0xffffffff)

◆ DMA_CH15_AL2_READ_ADDR_LSB

#define DMA_CH15_AL2_READ_ADDR_LSB _u(0)

◆ DMA_CH15_AL2_READ_ADDR_MSB

#define DMA_CH15_AL2_READ_ADDR_MSB _u(31)

◆ DMA_CH15_AL2_READ_ADDR_OFFSET

#define DMA_CH15_AL2_READ_ADDR_OFFSET _u(0x000003e8)

◆ DMA_CH15_AL2_READ_ADDR_RESET

#define DMA_CH15_AL2_READ_ADDR_RESET "-"

◆ DMA_CH15_AL2_TRANS_COUNT_ACCESS

#define DMA_CH15_AL2_TRANS_COUNT_ACCESS "RW"

◆ DMA_CH15_AL2_TRANS_COUNT_BITS

#define DMA_CH15_AL2_TRANS_COUNT_BITS _u(0xffffffff)

◆ DMA_CH15_AL2_TRANS_COUNT_LSB

#define DMA_CH15_AL2_TRANS_COUNT_LSB _u(0)

◆ DMA_CH15_AL2_TRANS_COUNT_MSB

#define DMA_CH15_AL2_TRANS_COUNT_MSB _u(31)

◆ DMA_CH15_AL2_TRANS_COUNT_OFFSET

#define DMA_CH15_AL2_TRANS_COUNT_OFFSET _u(0x000003e4)

◆ DMA_CH15_AL2_TRANS_COUNT_RESET

#define DMA_CH15_AL2_TRANS_COUNT_RESET "-"

◆ DMA_CH15_AL2_WRITE_ADDR_TRIG_ACCESS

#define DMA_CH15_AL2_WRITE_ADDR_TRIG_ACCESS "RW"

◆ DMA_CH15_AL2_WRITE_ADDR_TRIG_BITS

#define DMA_CH15_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff)

◆ DMA_CH15_AL2_WRITE_ADDR_TRIG_LSB

#define DMA_CH15_AL2_WRITE_ADDR_TRIG_LSB _u(0)

◆ DMA_CH15_AL2_WRITE_ADDR_TRIG_MSB

#define DMA_CH15_AL2_WRITE_ADDR_TRIG_MSB _u(31)

◆ DMA_CH15_AL2_WRITE_ADDR_TRIG_OFFSET

#define DMA_CH15_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x000003ec)

◆ DMA_CH15_AL2_WRITE_ADDR_TRIG_RESET

#define DMA_CH15_AL2_WRITE_ADDR_TRIG_RESET "-"

◆ DMA_CH15_AL3_CTRL_ACCESS

#define DMA_CH15_AL3_CTRL_ACCESS "RW"

◆ DMA_CH15_AL3_CTRL_BITS

#define DMA_CH15_AL3_CTRL_BITS _u(0xffffffff)

◆ DMA_CH15_AL3_CTRL_LSB

#define DMA_CH15_AL3_CTRL_LSB _u(0)

◆ DMA_CH15_AL3_CTRL_MSB

#define DMA_CH15_AL3_CTRL_MSB _u(31)

◆ DMA_CH15_AL3_CTRL_OFFSET

#define DMA_CH15_AL3_CTRL_OFFSET _u(0x000003f0)

◆ DMA_CH15_AL3_CTRL_RESET

#define DMA_CH15_AL3_CTRL_RESET "-"

◆ DMA_CH15_AL3_READ_ADDR_TRIG_ACCESS

#define DMA_CH15_AL3_READ_ADDR_TRIG_ACCESS "RW"

◆ DMA_CH15_AL3_READ_ADDR_TRIG_BITS

#define DMA_CH15_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff)

◆ DMA_CH15_AL3_READ_ADDR_TRIG_LSB

#define DMA_CH15_AL3_READ_ADDR_TRIG_LSB _u(0)

◆ DMA_CH15_AL3_READ_ADDR_TRIG_MSB

#define DMA_CH15_AL3_READ_ADDR_TRIG_MSB _u(31)

◆ DMA_CH15_AL3_READ_ADDR_TRIG_OFFSET

#define DMA_CH15_AL3_READ_ADDR_TRIG_OFFSET _u(0x000003fc)

◆ DMA_CH15_AL3_READ_ADDR_TRIG_RESET

#define DMA_CH15_AL3_READ_ADDR_TRIG_RESET "-"

◆ DMA_CH15_AL3_TRANS_COUNT_ACCESS

#define DMA_CH15_AL3_TRANS_COUNT_ACCESS "RW"

◆ DMA_CH15_AL3_TRANS_COUNT_BITS

#define DMA_CH15_AL3_TRANS_COUNT_BITS _u(0xffffffff)

◆ DMA_CH15_AL3_TRANS_COUNT_LSB

#define DMA_CH15_AL3_TRANS_COUNT_LSB _u(0)

◆ DMA_CH15_AL3_TRANS_COUNT_MSB

#define DMA_CH15_AL3_TRANS_COUNT_MSB _u(31)

◆ DMA_CH15_AL3_TRANS_COUNT_OFFSET

#define DMA_CH15_AL3_TRANS_COUNT_OFFSET _u(0x000003f8)

◆ DMA_CH15_AL3_TRANS_COUNT_RESET

#define DMA_CH15_AL3_TRANS_COUNT_RESET "-"

◆ DMA_CH15_AL3_WRITE_ADDR_ACCESS

#define DMA_CH15_AL3_WRITE_ADDR_ACCESS "RW"

◆ DMA_CH15_AL3_WRITE_ADDR_BITS

#define DMA_CH15_AL3_WRITE_ADDR_BITS _u(0xffffffff)

◆ DMA_CH15_AL3_WRITE_ADDR_LSB

#define DMA_CH15_AL3_WRITE_ADDR_LSB _u(0)

◆ DMA_CH15_AL3_WRITE_ADDR_MSB

#define DMA_CH15_AL3_WRITE_ADDR_MSB _u(31)

◆ DMA_CH15_AL3_WRITE_ADDR_OFFSET

#define DMA_CH15_AL3_WRITE_ADDR_OFFSET _u(0x000003f4)

◆ DMA_CH15_AL3_WRITE_ADDR_RESET

#define DMA_CH15_AL3_WRITE_ADDR_RESET "-"

◆ DMA_CH15_CTRL_TRIG_AHB_ERROR_ACCESS

#define DMA_CH15_CTRL_TRIG_AHB_ERROR_ACCESS "RO"

◆ DMA_CH15_CTRL_TRIG_AHB_ERROR_BITS

#define DMA_CH15_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000)

◆ DMA_CH15_CTRL_TRIG_AHB_ERROR_LSB

#define DMA_CH15_CTRL_TRIG_AHB_ERROR_LSB _u(31)

◆ DMA_CH15_CTRL_TRIG_AHB_ERROR_MSB

#define DMA_CH15_CTRL_TRIG_AHB_ERROR_MSB _u(31)

◆ DMA_CH15_CTRL_TRIG_AHB_ERROR_RESET

#define DMA_CH15_CTRL_TRIG_AHB_ERROR_RESET _u(0x0)

◆ DMA_CH15_CTRL_TRIG_BITS

#define DMA_CH15_CTRL_TRIG_BITS _u(0xe7ffffff)

◆ DMA_CH15_CTRL_TRIG_BSWAP_ACCESS

#define DMA_CH15_CTRL_TRIG_BSWAP_ACCESS "RW"

◆ DMA_CH15_CTRL_TRIG_BSWAP_BITS

#define DMA_CH15_CTRL_TRIG_BSWAP_BITS _u(0x01000000)

◆ DMA_CH15_CTRL_TRIG_BSWAP_LSB

#define DMA_CH15_CTRL_TRIG_BSWAP_LSB _u(24)

◆ DMA_CH15_CTRL_TRIG_BSWAP_MSB

#define DMA_CH15_CTRL_TRIG_BSWAP_MSB _u(24)

◆ DMA_CH15_CTRL_TRIG_BSWAP_RESET

#define DMA_CH15_CTRL_TRIG_BSWAP_RESET _u(0x0)

◆ DMA_CH15_CTRL_TRIG_BUSY_ACCESS

#define DMA_CH15_CTRL_TRIG_BUSY_ACCESS "RO"

◆ DMA_CH15_CTRL_TRIG_BUSY_BITS

#define DMA_CH15_CTRL_TRIG_BUSY_BITS _u(0x04000000)

◆ DMA_CH15_CTRL_TRIG_BUSY_LSB

#define DMA_CH15_CTRL_TRIG_BUSY_LSB _u(26)

◆ DMA_CH15_CTRL_TRIG_BUSY_MSB

#define DMA_CH15_CTRL_TRIG_BUSY_MSB _u(26)

◆ DMA_CH15_CTRL_TRIG_BUSY_RESET

#define DMA_CH15_CTRL_TRIG_BUSY_RESET _u(0x0)

◆ DMA_CH15_CTRL_TRIG_CHAIN_TO_ACCESS

#define DMA_CH15_CTRL_TRIG_CHAIN_TO_ACCESS "RW"

◆ DMA_CH15_CTRL_TRIG_CHAIN_TO_BITS

#define DMA_CH15_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000)

◆ DMA_CH15_CTRL_TRIG_CHAIN_TO_LSB

#define DMA_CH15_CTRL_TRIG_CHAIN_TO_LSB _u(13)

◆ DMA_CH15_CTRL_TRIG_CHAIN_TO_MSB

#define DMA_CH15_CTRL_TRIG_CHAIN_TO_MSB _u(16)

◆ DMA_CH15_CTRL_TRIG_CHAIN_TO_RESET

#define DMA_CH15_CTRL_TRIG_CHAIN_TO_RESET _u(0x0)

◆ DMA_CH15_CTRL_TRIG_DATA_SIZE_ACCESS

#define DMA_CH15_CTRL_TRIG_DATA_SIZE_ACCESS "RW"

◆ DMA_CH15_CTRL_TRIG_DATA_SIZE_BITS

#define DMA_CH15_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c)

◆ DMA_CH15_CTRL_TRIG_DATA_SIZE_LSB

#define DMA_CH15_CTRL_TRIG_DATA_SIZE_LSB _u(2)

◆ DMA_CH15_CTRL_TRIG_DATA_SIZE_MSB

#define DMA_CH15_CTRL_TRIG_DATA_SIZE_MSB _u(3)

◆ DMA_CH15_CTRL_TRIG_DATA_SIZE_RESET

#define DMA_CH15_CTRL_TRIG_DATA_SIZE_RESET _u(0x0)

◆ DMA_CH15_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE

#define DMA_CH15_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0)

◆ DMA_CH15_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD

#define DMA_CH15_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1)

◆ DMA_CH15_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD

#define DMA_CH15_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2)

◆ DMA_CH15_CTRL_TRIG_EN_ACCESS

#define DMA_CH15_CTRL_TRIG_EN_ACCESS "RW"

◆ DMA_CH15_CTRL_TRIG_EN_BITS

#define DMA_CH15_CTRL_TRIG_EN_BITS _u(0x00000001)

◆ DMA_CH15_CTRL_TRIG_EN_LSB

#define DMA_CH15_CTRL_TRIG_EN_LSB _u(0)

◆ DMA_CH15_CTRL_TRIG_EN_MSB

#define DMA_CH15_CTRL_TRIG_EN_MSB _u(0)

◆ DMA_CH15_CTRL_TRIG_EN_RESET

#define DMA_CH15_CTRL_TRIG_EN_RESET _u(0x0)

◆ DMA_CH15_CTRL_TRIG_HIGH_PRIORITY_ACCESS

#define DMA_CH15_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW"

◆ DMA_CH15_CTRL_TRIG_HIGH_PRIORITY_BITS

#define DMA_CH15_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002)

◆ DMA_CH15_CTRL_TRIG_HIGH_PRIORITY_LSB

#define DMA_CH15_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1)

◆ DMA_CH15_CTRL_TRIG_HIGH_PRIORITY_MSB

#define DMA_CH15_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1)

◆ DMA_CH15_CTRL_TRIG_HIGH_PRIORITY_RESET

#define DMA_CH15_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0)

◆ DMA_CH15_CTRL_TRIG_INCR_READ_ACCESS

#define DMA_CH15_CTRL_TRIG_INCR_READ_ACCESS "RW"

◆ DMA_CH15_CTRL_TRIG_INCR_READ_BITS

#define DMA_CH15_CTRL_TRIG_INCR_READ_BITS _u(0x00000010)

◆ DMA_CH15_CTRL_TRIG_INCR_READ_LSB

#define DMA_CH15_CTRL_TRIG_INCR_READ_LSB _u(4)

◆ DMA_CH15_CTRL_TRIG_INCR_READ_MSB

#define DMA_CH15_CTRL_TRIG_INCR_READ_MSB _u(4)

◆ DMA_CH15_CTRL_TRIG_INCR_READ_RESET

#define DMA_CH15_CTRL_TRIG_INCR_READ_RESET _u(0x0)

◆ DMA_CH15_CTRL_TRIG_INCR_READ_REV_ACCESS

#define DMA_CH15_CTRL_TRIG_INCR_READ_REV_ACCESS "RW"

◆ DMA_CH15_CTRL_TRIG_INCR_READ_REV_BITS

#define DMA_CH15_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020)

◆ DMA_CH15_CTRL_TRIG_INCR_READ_REV_LSB

#define DMA_CH15_CTRL_TRIG_INCR_READ_REV_LSB _u(5)

◆ DMA_CH15_CTRL_TRIG_INCR_READ_REV_MSB

#define DMA_CH15_CTRL_TRIG_INCR_READ_REV_MSB _u(5)

◆ DMA_CH15_CTRL_TRIG_INCR_READ_REV_RESET

#define DMA_CH15_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0)

◆ DMA_CH15_CTRL_TRIG_INCR_WRITE_ACCESS

#define DMA_CH15_CTRL_TRIG_INCR_WRITE_ACCESS "RW"

◆ DMA_CH15_CTRL_TRIG_INCR_WRITE_BITS

#define DMA_CH15_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040)

◆ DMA_CH15_CTRL_TRIG_INCR_WRITE_LSB

#define DMA_CH15_CTRL_TRIG_INCR_WRITE_LSB _u(6)

◆ DMA_CH15_CTRL_TRIG_INCR_WRITE_MSB

#define DMA_CH15_CTRL_TRIG_INCR_WRITE_MSB _u(6)

◆ DMA_CH15_CTRL_TRIG_INCR_WRITE_RESET

#define DMA_CH15_CTRL_TRIG_INCR_WRITE_RESET _u(0x0)

◆ DMA_CH15_CTRL_TRIG_INCR_WRITE_REV_ACCESS

#define DMA_CH15_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW"

◆ DMA_CH15_CTRL_TRIG_INCR_WRITE_REV_BITS

#define DMA_CH15_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080)

◆ DMA_CH15_CTRL_TRIG_INCR_WRITE_REV_LSB

#define DMA_CH15_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7)

◆ DMA_CH15_CTRL_TRIG_INCR_WRITE_REV_MSB

#define DMA_CH15_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7)

◆ DMA_CH15_CTRL_TRIG_INCR_WRITE_REV_RESET

#define DMA_CH15_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0)

◆ DMA_CH15_CTRL_TRIG_IRQ_QUIET_ACCESS

#define DMA_CH15_CTRL_TRIG_IRQ_QUIET_ACCESS "RW"

◆ DMA_CH15_CTRL_TRIG_IRQ_QUIET_BITS

#define DMA_CH15_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000)

◆ DMA_CH15_CTRL_TRIG_IRQ_QUIET_LSB

#define DMA_CH15_CTRL_TRIG_IRQ_QUIET_LSB _u(23)

◆ DMA_CH15_CTRL_TRIG_IRQ_QUIET_MSB

#define DMA_CH15_CTRL_TRIG_IRQ_QUIET_MSB _u(23)

◆ DMA_CH15_CTRL_TRIG_IRQ_QUIET_RESET

#define DMA_CH15_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0)

◆ DMA_CH15_CTRL_TRIG_OFFSET

#define DMA_CH15_CTRL_TRIG_OFFSET _u(0x000003cc)

◆ DMA_CH15_CTRL_TRIG_READ_ERROR_ACCESS

#define DMA_CH15_CTRL_TRIG_READ_ERROR_ACCESS "WC"

◆ DMA_CH15_CTRL_TRIG_READ_ERROR_BITS

#define DMA_CH15_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000)

◆ DMA_CH15_CTRL_TRIG_READ_ERROR_LSB

#define DMA_CH15_CTRL_TRIG_READ_ERROR_LSB _u(30)

◆ DMA_CH15_CTRL_TRIG_READ_ERROR_MSB

#define DMA_CH15_CTRL_TRIG_READ_ERROR_MSB _u(30)

◆ DMA_CH15_CTRL_TRIG_READ_ERROR_RESET

#define DMA_CH15_CTRL_TRIG_READ_ERROR_RESET _u(0x0)

◆ DMA_CH15_CTRL_TRIG_RESET

#define DMA_CH15_CTRL_TRIG_RESET _u(0x00000000)

◆ DMA_CH15_CTRL_TRIG_RING_SEL_ACCESS

#define DMA_CH15_CTRL_TRIG_RING_SEL_ACCESS "RW"

◆ DMA_CH15_CTRL_TRIG_RING_SEL_BITS

#define DMA_CH15_CTRL_TRIG_RING_SEL_BITS _u(0x00001000)

◆ DMA_CH15_CTRL_TRIG_RING_SEL_LSB

#define DMA_CH15_CTRL_TRIG_RING_SEL_LSB _u(12)

◆ DMA_CH15_CTRL_TRIG_RING_SEL_MSB

#define DMA_CH15_CTRL_TRIG_RING_SEL_MSB _u(12)

◆ DMA_CH15_CTRL_TRIG_RING_SEL_RESET

#define DMA_CH15_CTRL_TRIG_RING_SEL_RESET _u(0x0)

◆ DMA_CH15_CTRL_TRIG_RING_SIZE_ACCESS

#define DMA_CH15_CTRL_TRIG_RING_SIZE_ACCESS "RW"

◆ DMA_CH15_CTRL_TRIG_RING_SIZE_BITS

#define DMA_CH15_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00)

◆ DMA_CH15_CTRL_TRIG_RING_SIZE_LSB

#define DMA_CH15_CTRL_TRIG_RING_SIZE_LSB _u(8)

◆ DMA_CH15_CTRL_TRIG_RING_SIZE_MSB

#define DMA_CH15_CTRL_TRIG_RING_SIZE_MSB _u(11)

◆ DMA_CH15_CTRL_TRIG_RING_SIZE_RESET

#define DMA_CH15_CTRL_TRIG_RING_SIZE_RESET _u(0x0)

◆ DMA_CH15_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE

#define DMA_CH15_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0)

◆ DMA_CH15_CTRL_TRIG_SNIFF_EN_ACCESS

#define DMA_CH15_CTRL_TRIG_SNIFF_EN_ACCESS "RW"

◆ DMA_CH15_CTRL_TRIG_SNIFF_EN_BITS

#define DMA_CH15_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000)

◆ DMA_CH15_CTRL_TRIG_SNIFF_EN_LSB

#define DMA_CH15_CTRL_TRIG_SNIFF_EN_LSB _u(25)

◆ DMA_CH15_CTRL_TRIG_SNIFF_EN_MSB

#define DMA_CH15_CTRL_TRIG_SNIFF_EN_MSB _u(25)

◆ DMA_CH15_CTRL_TRIG_SNIFF_EN_RESET

#define DMA_CH15_CTRL_TRIG_SNIFF_EN_RESET _u(0x0)

◆ DMA_CH15_CTRL_TRIG_TREQ_SEL_ACCESS

#define DMA_CH15_CTRL_TRIG_TREQ_SEL_ACCESS "RW"

◆ DMA_CH15_CTRL_TRIG_TREQ_SEL_BITS

#define DMA_CH15_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000)

◆ DMA_CH15_CTRL_TRIG_TREQ_SEL_LSB

#define DMA_CH15_CTRL_TRIG_TREQ_SEL_LSB _u(17)

◆ DMA_CH15_CTRL_TRIG_TREQ_SEL_MSB

#define DMA_CH15_CTRL_TRIG_TREQ_SEL_MSB _u(22)

◆ DMA_CH15_CTRL_TRIG_TREQ_SEL_RESET

#define DMA_CH15_CTRL_TRIG_TREQ_SEL_RESET _u(0x00)

◆ DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT

#define DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f)

◆ DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0

#define DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b)

◆ DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1

#define DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c)

◆ DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2

#define DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d)

◆ DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3

#define DMA_CH15_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e)

◆ DMA_CH15_CTRL_TRIG_WRITE_ERROR_ACCESS

#define DMA_CH15_CTRL_TRIG_WRITE_ERROR_ACCESS "WC"

◆ DMA_CH15_CTRL_TRIG_WRITE_ERROR_BITS

#define DMA_CH15_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000)

◆ DMA_CH15_CTRL_TRIG_WRITE_ERROR_LSB

#define DMA_CH15_CTRL_TRIG_WRITE_ERROR_LSB _u(29)

◆ DMA_CH15_CTRL_TRIG_WRITE_ERROR_MSB

#define DMA_CH15_CTRL_TRIG_WRITE_ERROR_MSB _u(29)

◆ DMA_CH15_CTRL_TRIG_WRITE_ERROR_RESET

#define DMA_CH15_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0)

◆ DMA_CH15_DBG_CTDREQ_ACCESS

#define DMA_CH15_DBG_CTDREQ_ACCESS "WC"

◆ DMA_CH15_DBG_CTDREQ_BITS

#define DMA_CH15_DBG_CTDREQ_BITS _u(0x0000003f)

◆ DMA_CH15_DBG_CTDREQ_LSB

#define DMA_CH15_DBG_CTDREQ_LSB _u(0)

◆ DMA_CH15_DBG_CTDREQ_MSB

#define DMA_CH15_DBG_CTDREQ_MSB _u(5)

◆ DMA_CH15_DBG_CTDREQ_OFFSET

#define DMA_CH15_DBG_CTDREQ_OFFSET _u(0x00000bc0)

◆ DMA_CH15_DBG_CTDREQ_RESET

#define DMA_CH15_DBG_CTDREQ_RESET _u(0x00000000)

◆ DMA_CH15_DBG_TCR_ACCESS

#define DMA_CH15_DBG_TCR_ACCESS "RO"

◆ DMA_CH15_DBG_TCR_BITS

#define DMA_CH15_DBG_TCR_BITS _u(0xffffffff)

◆ DMA_CH15_DBG_TCR_LSB

#define DMA_CH15_DBG_TCR_LSB _u(0)

◆ DMA_CH15_DBG_TCR_MSB

#define DMA_CH15_DBG_TCR_MSB _u(31)

◆ DMA_CH15_DBG_TCR_OFFSET

#define DMA_CH15_DBG_TCR_OFFSET _u(0x00000bc4)

◆ DMA_CH15_DBG_TCR_RESET

#define DMA_CH15_DBG_TCR_RESET _u(0x00000000)

◆ DMA_CH15_READ_ADDR_ACCESS

#define DMA_CH15_READ_ADDR_ACCESS "RW"

◆ DMA_CH15_READ_ADDR_BITS

#define DMA_CH15_READ_ADDR_BITS _u(0xffffffff)

◆ DMA_CH15_READ_ADDR_LSB

#define DMA_CH15_READ_ADDR_LSB _u(0)

◆ DMA_CH15_READ_ADDR_MSB

#define DMA_CH15_READ_ADDR_MSB _u(31)

◆ DMA_CH15_READ_ADDR_OFFSET

#define DMA_CH15_READ_ADDR_OFFSET _u(0x000003c0)

◆ DMA_CH15_READ_ADDR_RESET

#define DMA_CH15_READ_ADDR_RESET _u(0x00000000)

◆ DMA_CH15_TRANS_COUNT_BITS

#define DMA_CH15_TRANS_COUNT_BITS _u(0xffffffff)

◆ DMA_CH15_TRANS_COUNT_COUNT_ACCESS

#define DMA_CH15_TRANS_COUNT_COUNT_ACCESS "RW"

◆ DMA_CH15_TRANS_COUNT_COUNT_BITS

#define DMA_CH15_TRANS_COUNT_COUNT_BITS _u(0x0fffffff)

◆ DMA_CH15_TRANS_COUNT_COUNT_LSB

#define DMA_CH15_TRANS_COUNT_COUNT_LSB _u(0)

◆ DMA_CH15_TRANS_COUNT_COUNT_MSB

#define DMA_CH15_TRANS_COUNT_COUNT_MSB _u(27)

◆ DMA_CH15_TRANS_COUNT_COUNT_RESET

#define DMA_CH15_TRANS_COUNT_COUNT_RESET _u(0x0000000)

◆ DMA_CH15_TRANS_COUNT_MODE_ACCESS

#define DMA_CH15_TRANS_COUNT_MODE_ACCESS "RW"

◆ DMA_CH15_TRANS_COUNT_MODE_BITS

#define DMA_CH15_TRANS_COUNT_MODE_BITS _u(0xf0000000)

◆ DMA_CH15_TRANS_COUNT_MODE_LSB

#define DMA_CH15_TRANS_COUNT_MODE_LSB _u(28)

◆ DMA_CH15_TRANS_COUNT_MODE_MSB

#define DMA_CH15_TRANS_COUNT_MODE_MSB _u(31)

◆ DMA_CH15_TRANS_COUNT_MODE_RESET

#define DMA_CH15_TRANS_COUNT_MODE_RESET _u(0x0)

◆ DMA_CH15_TRANS_COUNT_MODE_VALUE_ENDLESS

#define DMA_CH15_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf)

◆ DMA_CH15_TRANS_COUNT_MODE_VALUE_NORMAL

#define DMA_CH15_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0)

◆ DMA_CH15_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF

#define DMA_CH15_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1)

◆ DMA_CH15_TRANS_COUNT_OFFSET

#define DMA_CH15_TRANS_COUNT_OFFSET _u(0x000003c8)

◆ DMA_CH15_TRANS_COUNT_RESET

#define DMA_CH15_TRANS_COUNT_RESET _u(0x00000000)

◆ DMA_CH15_WRITE_ADDR_ACCESS

#define DMA_CH15_WRITE_ADDR_ACCESS "RW"

◆ DMA_CH15_WRITE_ADDR_BITS

#define DMA_CH15_WRITE_ADDR_BITS _u(0xffffffff)

◆ DMA_CH15_WRITE_ADDR_LSB

#define DMA_CH15_WRITE_ADDR_LSB _u(0)

◆ DMA_CH15_WRITE_ADDR_MSB

#define DMA_CH15_WRITE_ADDR_MSB _u(31)

◆ DMA_CH15_WRITE_ADDR_OFFSET

#define DMA_CH15_WRITE_ADDR_OFFSET _u(0x000003c4)

◆ DMA_CH15_WRITE_ADDR_RESET

#define DMA_CH15_WRITE_ADDR_RESET _u(0x00000000)

◆ DMA_CH1_AL1_CTRL_ACCESS

#define DMA_CH1_AL1_CTRL_ACCESS "RW"

◆ DMA_CH1_AL1_CTRL_BITS

#define DMA_CH1_AL1_CTRL_BITS _u(0xffffffff)

◆ DMA_CH1_AL1_CTRL_LSB

#define DMA_CH1_AL1_CTRL_LSB _u(0)

◆ DMA_CH1_AL1_CTRL_MSB

#define DMA_CH1_AL1_CTRL_MSB _u(31)

◆ DMA_CH1_AL1_CTRL_OFFSET

#define DMA_CH1_AL1_CTRL_OFFSET _u(0x00000050)

◆ DMA_CH1_AL1_CTRL_RESET

#define DMA_CH1_AL1_CTRL_RESET "-"

◆ DMA_CH1_AL1_READ_ADDR_ACCESS

#define DMA_CH1_AL1_READ_ADDR_ACCESS "RW"

◆ DMA_CH1_AL1_READ_ADDR_BITS

#define DMA_CH1_AL1_READ_ADDR_BITS _u(0xffffffff)

◆ DMA_CH1_AL1_READ_ADDR_LSB

#define DMA_CH1_AL1_READ_ADDR_LSB _u(0)

◆ DMA_CH1_AL1_READ_ADDR_MSB

#define DMA_CH1_AL1_READ_ADDR_MSB _u(31)

◆ DMA_CH1_AL1_READ_ADDR_OFFSET

#define DMA_CH1_AL1_READ_ADDR_OFFSET _u(0x00000054)

◆ DMA_CH1_AL1_READ_ADDR_RESET

#define DMA_CH1_AL1_READ_ADDR_RESET "-"

◆ DMA_CH1_AL1_TRANS_COUNT_TRIG_ACCESS

#define DMA_CH1_AL1_TRANS_COUNT_TRIG_ACCESS "RW"

◆ DMA_CH1_AL1_TRANS_COUNT_TRIG_BITS

#define DMA_CH1_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff)

◆ DMA_CH1_AL1_TRANS_COUNT_TRIG_LSB

#define DMA_CH1_AL1_TRANS_COUNT_TRIG_LSB _u(0)

◆ DMA_CH1_AL1_TRANS_COUNT_TRIG_MSB

#define DMA_CH1_AL1_TRANS_COUNT_TRIG_MSB _u(31)

◆ DMA_CH1_AL1_TRANS_COUNT_TRIG_OFFSET

#define DMA_CH1_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000005c)

◆ DMA_CH1_AL1_TRANS_COUNT_TRIG_RESET

#define DMA_CH1_AL1_TRANS_COUNT_TRIG_RESET "-"

◆ DMA_CH1_AL1_WRITE_ADDR_ACCESS

#define DMA_CH1_AL1_WRITE_ADDR_ACCESS "RW"

◆ DMA_CH1_AL1_WRITE_ADDR_BITS

#define DMA_CH1_AL1_WRITE_ADDR_BITS _u(0xffffffff)

◆ DMA_CH1_AL1_WRITE_ADDR_LSB

#define DMA_CH1_AL1_WRITE_ADDR_LSB _u(0)

◆ DMA_CH1_AL1_WRITE_ADDR_MSB

#define DMA_CH1_AL1_WRITE_ADDR_MSB _u(31)

◆ DMA_CH1_AL1_WRITE_ADDR_OFFSET

#define DMA_CH1_AL1_WRITE_ADDR_OFFSET _u(0x00000058)

◆ DMA_CH1_AL1_WRITE_ADDR_RESET

#define DMA_CH1_AL1_WRITE_ADDR_RESET "-"

◆ DMA_CH1_AL2_CTRL_ACCESS

#define DMA_CH1_AL2_CTRL_ACCESS "RW"

◆ DMA_CH1_AL2_CTRL_BITS

#define DMA_CH1_AL2_CTRL_BITS _u(0xffffffff)

◆ DMA_CH1_AL2_CTRL_LSB

#define DMA_CH1_AL2_CTRL_LSB _u(0)

◆ DMA_CH1_AL2_CTRL_MSB

#define DMA_CH1_AL2_CTRL_MSB _u(31)

◆ DMA_CH1_AL2_CTRL_OFFSET

#define DMA_CH1_AL2_CTRL_OFFSET _u(0x00000060)

◆ DMA_CH1_AL2_CTRL_RESET

#define DMA_CH1_AL2_CTRL_RESET "-"

◆ DMA_CH1_AL2_READ_ADDR_ACCESS

#define DMA_CH1_AL2_READ_ADDR_ACCESS "RW"

◆ DMA_CH1_AL2_READ_ADDR_BITS

#define DMA_CH1_AL2_READ_ADDR_BITS _u(0xffffffff)

◆ DMA_CH1_AL2_READ_ADDR_LSB

#define DMA_CH1_AL2_READ_ADDR_LSB _u(0)

◆ DMA_CH1_AL2_READ_ADDR_MSB

#define DMA_CH1_AL2_READ_ADDR_MSB _u(31)

◆ DMA_CH1_AL2_READ_ADDR_OFFSET

#define DMA_CH1_AL2_READ_ADDR_OFFSET _u(0x00000068)

◆ DMA_CH1_AL2_READ_ADDR_RESET

#define DMA_CH1_AL2_READ_ADDR_RESET "-"

◆ DMA_CH1_AL2_TRANS_COUNT_ACCESS

#define DMA_CH1_AL2_TRANS_COUNT_ACCESS "RW"

◆ DMA_CH1_AL2_TRANS_COUNT_BITS

#define DMA_CH1_AL2_TRANS_COUNT_BITS _u(0xffffffff)

◆ DMA_CH1_AL2_TRANS_COUNT_LSB

#define DMA_CH1_AL2_TRANS_COUNT_LSB _u(0)

◆ DMA_CH1_AL2_TRANS_COUNT_MSB

#define DMA_CH1_AL2_TRANS_COUNT_MSB _u(31)

◆ DMA_CH1_AL2_TRANS_COUNT_OFFSET

#define DMA_CH1_AL2_TRANS_COUNT_OFFSET _u(0x00000064)

◆ DMA_CH1_AL2_TRANS_COUNT_RESET

#define DMA_CH1_AL2_TRANS_COUNT_RESET "-"

◆ DMA_CH1_AL2_WRITE_ADDR_TRIG_ACCESS

#define DMA_CH1_AL2_WRITE_ADDR_TRIG_ACCESS "RW"

◆ DMA_CH1_AL2_WRITE_ADDR_TRIG_BITS

#define DMA_CH1_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff)

◆ DMA_CH1_AL2_WRITE_ADDR_TRIG_LSB

#define DMA_CH1_AL2_WRITE_ADDR_TRIG_LSB _u(0)

◆ DMA_CH1_AL2_WRITE_ADDR_TRIG_MSB

#define DMA_CH1_AL2_WRITE_ADDR_TRIG_MSB _u(31)

◆ DMA_CH1_AL2_WRITE_ADDR_TRIG_OFFSET

#define DMA_CH1_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x0000006c)

◆ DMA_CH1_AL2_WRITE_ADDR_TRIG_RESET

#define DMA_CH1_AL2_WRITE_ADDR_TRIG_RESET "-"

◆ DMA_CH1_AL3_CTRL_ACCESS

#define DMA_CH1_AL3_CTRL_ACCESS "RW"

◆ DMA_CH1_AL3_CTRL_BITS

#define DMA_CH1_AL3_CTRL_BITS _u(0xffffffff)

◆ DMA_CH1_AL3_CTRL_LSB

#define DMA_CH1_AL3_CTRL_LSB _u(0)

◆ DMA_CH1_AL3_CTRL_MSB

#define DMA_CH1_AL3_CTRL_MSB _u(31)

◆ DMA_CH1_AL3_CTRL_OFFSET

#define DMA_CH1_AL3_CTRL_OFFSET _u(0x00000070)

◆ DMA_CH1_AL3_CTRL_RESET

#define DMA_CH1_AL3_CTRL_RESET "-"

◆ DMA_CH1_AL3_READ_ADDR_TRIG_ACCESS

#define DMA_CH1_AL3_READ_ADDR_TRIG_ACCESS "RW"

◆ DMA_CH1_AL3_READ_ADDR_TRIG_BITS

#define DMA_CH1_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff)

◆ DMA_CH1_AL3_READ_ADDR_TRIG_LSB

#define DMA_CH1_AL3_READ_ADDR_TRIG_LSB _u(0)

◆ DMA_CH1_AL3_READ_ADDR_TRIG_MSB

#define DMA_CH1_AL3_READ_ADDR_TRIG_MSB _u(31)

◆ DMA_CH1_AL3_READ_ADDR_TRIG_OFFSET

#define DMA_CH1_AL3_READ_ADDR_TRIG_OFFSET _u(0x0000007c)

◆ DMA_CH1_AL3_READ_ADDR_TRIG_RESET

#define DMA_CH1_AL3_READ_ADDR_TRIG_RESET "-"

◆ DMA_CH1_AL3_TRANS_COUNT_ACCESS

#define DMA_CH1_AL3_TRANS_COUNT_ACCESS "RW"

◆ DMA_CH1_AL3_TRANS_COUNT_BITS

#define DMA_CH1_AL3_TRANS_COUNT_BITS _u(0xffffffff)

◆ DMA_CH1_AL3_TRANS_COUNT_LSB

#define DMA_CH1_AL3_TRANS_COUNT_LSB _u(0)

◆ DMA_CH1_AL3_TRANS_COUNT_MSB

#define DMA_CH1_AL3_TRANS_COUNT_MSB _u(31)

◆ DMA_CH1_AL3_TRANS_COUNT_OFFSET

#define DMA_CH1_AL3_TRANS_COUNT_OFFSET _u(0x00000078)

◆ DMA_CH1_AL3_TRANS_COUNT_RESET

#define DMA_CH1_AL3_TRANS_COUNT_RESET "-"

◆ DMA_CH1_AL3_WRITE_ADDR_ACCESS

#define DMA_CH1_AL3_WRITE_ADDR_ACCESS "RW"

◆ DMA_CH1_AL3_WRITE_ADDR_BITS

#define DMA_CH1_AL3_WRITE_ADDR_BITS _u(0xffffffff)

◆ DMA_CH1_AL3_WRITE_ADDR_LSB

#define DMA_CH1_AL3_WRITE_ADDR_LSB _u(0)

◆ DMA_CH1_AL3_WRITE_ADDR_MSB

#define DMA_CH1_AL3_WRITE_ADDR_MSB _u(31)

◆ DMA_CH1_AL3_WRITE_ADDR_OFFSET

#define DMA_CH1_AL3_WRITE_ADDR_OFFSET _u(0x00000074)

◆ DMA_CH1_AL3_WRITE_ADDR_RESET

#define DMA_CH1_AL3_WRITE_ADDR_RESET "-"

◆ DMA_CH1_CTRL_TRIG_AHB_ERROR_ACCESS

#define DMA_CH1_CTRL_TRIG_AHB_ERROR_ACCESS "RO"

◆ DMA_CH1_CTRL_TRIG_AHB_ERROR_BITS

#define DMA_CH1_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000)

◆ DMA_CH1_CTRL_TRIG_AHB_ERROR_LSB

#define DMA_CH1_CTRL_TRIG_AHB_ERROR_LSB _u(31)

◆ DMA_CH1_CTRL_TRIG_AHB_ERROR_MSB

#define DMA_CH1_CTRL_TRIG_AHB_ERROR_MSB _u(31)

◆ DMA_CH1_CTRL_TRIG_AHB_ERROR_RESET

#define DMA_CH1_CTRL_TRIG_AHB_ERROR_RESET _u(0x0)

◆ DMA_CH1_CTRL_TRIG_BITS

#define DMA_CH1_CTRL_TRIG_BITS _u(0xe7ffffff)

◆ DMA_CH1_CTRL_TRIG_BSWAP_ACCESS

#define DMA_CH1_CTRL_TRIG_BSWAP_ACCESS "RW"

◆ DMA_CH1_CTRL_TRIG_BSWAP_BITS

#define DMA_CH1_CTRL_TRIG_BSWAP_BITS _u(0x01000000)

◆ DMA_CH1_CTRL_TRIG_BSWAP_LSB

#define DMA_CH1_CTRL_TRIG_BSWAP_LSB _u(24)

◆ DMA_CH1_CTRL_TRIG_BSWAP_MSB

#define DMA_CH1_CTRL_TRIG_BSWAP_MSB _u(24)

◆ DMA_CH1_CTRL_TRIG_BSWAP_RESET

#define DMA_CH1_CTRL_TRIG_BSWAP_RESET _u(0x0)

◆ DMA_CH1_CTRL_TRIG_BUSY_ACCESS

#define DMA_CH1_CTRL_TRIG_BUSY_ACCESS "RO"

◆ DMA_CH1_CTRL_TRIG_BUSY_BITS

#define DMA_CH1_CTRL_TRIG_BUSY_BITS _u(0x04000000)

◆ DMA_CH1_CTRL_TRIG_BUSY_LSB

#define DMA_CH1_CTRL_TRIG_BUSY_LSB _u(26)

◆ DMA_CH1_CTRL_TRIG_BUSY_MSB

#define DMA_CH1_CTRL_TRIG_BUSY_MSB _u(26)

◆ DMA_CH1_CTRL_TRIG_BUSY_RESET

#define DMA_CH1_CTRL_TRIG_BUSY_RESET _u(0x0)

◆ DMA_CH1_CTRL_TRIG_CHAIN_TO_ACCESS

#define DMA_CH1_CTRL_TRIG_CHAIN_TO_ACCESS "RW"

◆ DMA_CH1_CTRL_TRIG_CHAIN_TO_BITS

#define DMA_CH1_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000)

◆ DMA_CH1_CTRL_TRIG_CHAIN_TO_LSB

#define DMA_CH1_CTRL_TRIG_CHAIN_TO_LSB _u(13)

◆ DMA_CH1_CTRL_TRIG_CHAIN_TO_MSB

#define DMA_CH1_CTRL_TRIG_CHAIN_TO_MSB _u(16)

◆ DMA_CH1_CTRL_TRIG_CHAIN_TO_RESET

#define DMA_CH1_CTRL_TRIG_CHAIN_TO_RESET _u(0x0)

◆ DMA_CH1_CTRL_TRIG_DATA_SIZE_ACCESS

#define DMA_CH1_CTRL_TRIG_DATA_SIZE_ACCESS "RW"

◆ DMA_CH1_CTRL_TRIG_DATA_SIZE_BITS

#define DMA_CH1_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c)

◆ DMA_CH1_CTRL_TRIG_DATA_SIZE_LSB

#define DMA_CH1_CTRL_TRIG_DATA_SIZE_LSB _u(2)

◆ DMA_CH1_CTRL_TRIG_DATA_SIZE_MSB

#define DMA_CH1_CTRL_TRIG_DATA_SIZE_MSB _u(3)

◆ DMA_CH1_CTRL_TRIG_DATA_SIZE_RESET

#define DMA_CH1_CTRL_TRIG_DATA_SIZE_RESET _u(0x0)

◆ DMA_CH1_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE

#define DMA_CH1_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0)

◆ DMA_CH1_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD

#define DMA_CH1_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1)

◆ DMA_CH1_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD

#define DMA_CH1_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2)

◆ DMA_CH1_CTRL_TRIG_EN_ACCESS

#define DMA_CH1_CTRL_TRIG_EN_ACCESS "RW"

◆ DMA_CH1_CTRL_TRIG_EN_BITS

#define DMA_CH1_CTRL_TRIG_EN_BITS _u(0x00000001)

◆ DMA_CH1_CTRL_TRIG_EN_LSB

#define DMA_CH1_CTRL_TRIG_EN_LSB _u(0)

◆ DMA_CH1_CTRL_TRIG_EN_MSB

#define DMA_CH1_CTRL_TRIG_EN_MSB _u(0)

◆ DMA_CH1_CTRL_TRIG_EN_RESET

#define DMA_CH1_CTRL_TRIG_EN_RESET _u(0x0)

◆ DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_ACCESS

#define DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW"

◆ DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_BITS

#define DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002)

◆ DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_LSB

#define DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1)

◆ DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_MSB

#define DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1)

◆ DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_RESET

#define DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0)

◆ DMA_CH1_CTRL_TRIG_INCR_READ_ACCESS

#define DMA_CH1_CTRL_TRIG_INCR_READ_ACCESS "RW"

◆ DMA_CH1_CTRL_TRIG_INCR_READ_BITS

#define DMA_CH1_CTRL_TRIG_INCR_READ_BITS _u(0x00000010)

◆ DMA_CH1_CTRL_TRIG_INCR_READ_LSB

#define DMA_CH1_CTRL_TRIG_INCR_READ_LSB _u(4)

◆ DMA_CH1_CTRL_TRIG_INCR_READ_MSB

#define DMA_CH1_CTRL_TRIG_INCR_READ_MSB _u(4)

◆ DMA_CH1_CTRL_TRIG_INCR_READ_RESET

#define DMA_CH1_CTRL_TRIG_INCR_READ_RESET _u(0x0)

◆ DMA_CH1_CTRL_TRIG_INCR_READ_REV_ACCESS

#define DMA_CH1_CTRL_TRIG_INCR_READ_REV_ACCESS "RW"

◆ DMA_CH1_CTRL_TRIG_INCR_READ_REV_BITS

#define DMA_CH1_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020)

◆ DMA_CH1_CTRL_TRIG_INCR_READ_REV_LSB

#define DMA_CH1_CTRL_TRIG_INCR_READ_REV_LSB _u(5)

◆ DMA_CH1_CTRL_TRIG_INCR_READ_REV_MSB

#define DMA_CH1_CTRL_TRIG_INCR_READ_REV_MSB _u(5)

◆ DMA_CH1_CTRL_TRIG_INCR_READ_REV_RESET

#define DMA_CH1_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0)

◆ DMA_CH1_CTRL_TRIG_INCR_WRITE_ACCESS

#define DMA_CH1_CTRL_TRIG_INCR_WRITE_ACCESS "RW"

◆ DMA_CH1_CTRL_TRIG_INCR_WRITE_BITS

#define DMA_CH1_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040)

◆ DMA_CH1_CTRL_TRIG_INCR_WRITE_LSB

#define DMA_CH1_CTRL_TRIG_INCR_WRITE_LSB _u(6)

◆ DMA_CH1_CTRL_TRIG_INCR_WRITE_MSB

#define DMA_CH1_CTRL_TRIG_INCR_WRITE_MSB _u(6)

◆ DMA_CH1_CTRL_TRIG_INCR_WRITE_RESET

#define DMA_CH1_CTRL_TRIG_INCR_WRITE_RESET _u(0x0)

◆ DMA_CH1_CTRL_TRIG_INCR_WRITE_REV_ACCESS

#define DMA_CH1_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW"

◆ DMA_CH1_CTRL_TRIG_INCR_WRITE_REV_BITS

#define DMA_CH1_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080)

◆ DMA_CH1_CTRL_TRIG_INCR_WRITE_REV_LSB

#define DMA_CH1_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7)

◆ DMA_CH1_CTRL_TRIG_INCR_WRITE_REV_MSB

#define DMA_CH1_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7)

◆ DMA_CH1_CTRL_TRIG_INCR_WRITE_REV_RESET

#define DMA_CH1_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0)

◆ DMA_CH1_CTRL_TRIG_IRQ_QUIET_ACCESS

#define DMA_CH1_CTRL_TRIG_IRQ_QUIET_ACCESS "RW"

◆ DMA_CH1_CTRL_TRIG_IRQ_QUIET_BITS

#define DMA_CH1_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000)

◆ DMA_CH1_CTRL_TRIG_IRQ_QUIET_LSB

#define DMA_CH1_CTRL_TRIG_IRQ_QUIET_LSB _u(23)

◆ DMA_CH1_CTRL_TRIG_IRQ_QUIET_MSB

#define DMA_CH1_CTRL_TRIG_IRQ_QUIET_MSB _u(23)

◆ DMA_CH1_CTRL_TRIG_IRQ_QUIET_RESET

#define DMA_CH1_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0)

◆ DMA_CH1_CTRL_TRIG_OFFSET

#define DMA_CH1_CTRL_TRIG_OFFSET _u(0x0000004c)

◆ DMA_CH1_CTRL_TRIG_READ_ERROR_ACCESS

#define DMA_CH1_CTRL_TRIG_READ_ERROR_ACCESS "WC"

◆ DMA_CH1_CTRL_TRIG_READ_ERROR_BITS

#define DMA_CH1_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000)

◆ DMA_CH1_CTRL_TRIG_READ_ERROR_LSB

#define DMA_CH1_CTRL_TRIG_READ_ERROR_LSB _u(30)

◆ DMA_CH1_CTRL_TRIG_READ_ERROR_MSB

#define DMA_CH1_CTRL_TRIG_READ_ERROR_MSB _u(30)

◆ DMA_CH1_CTRL_TRIG_READ_ERROR_RESET

#define DMA_CH1_CTRL_TRIG_READ_ERROR_RESET _u(0x0)

◆ DMA_CH1_CTRL_TRIG_RESET

#define DMA_CH1_CTRL_TRIG_RESET _u(0x00000000)

◆ DMA_CH1_CTRL_TRIG_RING_SEL_ACCESS

#define DMA_CH1_CTRL_TRIG_RING_SEL_ACCESS "RW"

◆ DMA_CH1_CTRL_TRIG_RING_SEL_BITS

#define DMA_CH1_CTRL_TRIG_RING_SEL_BITS _u(0x00001000)

◆ DMA_CH1_CTRL_TRIG_RING_SEL_LSB

#define DMA_CH1_CTRL_TRIG_RING_SEL_LSB _u(12)

◆ DMA_CH1_CTRL_TRIG_RING_SEL_MSB

#define DMA_CH1_CTRL_TRIG_RING_SEL_MSB _u(12)

◆ DMA_CH1_CTRL_TRIG_RING_SEL_RESET

#define DMA_CH1_CTRL_TRIG_RING_SEL_RESET _u(0x0)

◆ DMA_CH1_CTRL_TRIG_RING_SIZE_ACCESS

#define DMA_CH1_CTRL_TRIG_RING_SIZE_ACCESS "RW"

◆ DMA_CH1_CTRL_TRIG_RING_SIZE_BITS

#define DMA_CH1_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00)

◆ DMA_CH1_CTRL_TRIG_RING_SIZE_LSB

#define DMA_CH1_CTRL_TRIG_RING_SIZE_LSB _u(8)

◆ DMA_CH1_CTRL_TRIG_RING_SIZE_MSB

#define DMA_CH1_CTRL_TRIG_RING_SIZE_MSB _u(11)

◆ DMA_CH1_CTRL_TRIG_RING_SIZE_RESET

#define DMA_CH1_CTRL_TRIG_RING_SIZE_RESET _u(0x0)

◆ DMA_CH1_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE

#define DMA_CH1_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0)

◆ DMA_CH1_CTRL_TRIG_SNIFF_EN_ACCESS

#define DMA_CH1_CTRL_TRIG_SNIFF_EN_ACCESS "RW"

◆ DMA_CH1_CTRL_TRIG_SNIFF_EN_BITS

#define DMA_CH1_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000)

◆ DMA_CH1_CTRL_TRIG_SNIFF_EN_LSB

#define DMA_CH1_CTRL_TRIG_SNIFF_EN_LSB _u(25)

◆ DMA_CH1_CTRL_TRIG_SNIFF_EN_MSB

#define DMA_CH1_CTRL_TRIG_SNIFF_EN_MSB _u(25)

◆ DMA_CH1_CTRL_TRIG_SNIFF_EN_RESET

#define DMA_CH1_CTRL_TRIG_SNIFF_EN_RESET _u(0x0)

◆ DMA_CH1_CTRL_TRIG_TREQ_SEL_ACCESS

#define DMA_CH1_CTRL_TRIG_TREQ_SEL_ACCESS "RW"

◆ DMA_CH1_CTRL_TRIG_TREQ_SEL_BITS

#define DMA_CH1_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000)

◆ DMA_CH1_CTRL_TRIG_TREQ_SEL_LSB

#define DMA_CH1_CTRL_TRIG_TREQ_SEL_LSB _u(17)

◆ DMA_CH1_CTRL_TRIG_TREQ_SEL_MSB

#define DMA_CH1_CTRL_TRIG_TREQ_SEL_MSB _u(22)

◆ DMA_CH1_CTRL_TRIG_TREQ_SEL_RESET

#define DMA_CH1_CTRL_TRIG_TREQ_SEL_RESET _u(0x00)

◆ DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT

#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f)

◆ DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0

#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b)

◆ DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1

#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c)

◆ DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2

#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d)

◆ DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3

#define DMA_CH1_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e)

◆ DMA_CH1_CTRL_TRIG_WRITE_ERROR_ACCESS

#define DMA_CH1_CTRL_TRIG_WRITE_ERROR_ACCESS "WC"

◆ DMA_CH1_CTRL_TRIG_WRITE_ERROR_BITS

#define DMA_CH1_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000)

◆ DMA_CH1_CTRL_TRIG_WRITE_ERROR_LSB

#define DMA_CH1_CTRL_TRIG_WRITE_ERROR_LSB _u(29)

◆ DMA_CH1_CTRL_TRIG_WRITE_ERROR_MSB

#define DMA_CH1_CTRL_TRIG_WRITE_ERROR_MSB _u(29)

◆ DMA_CH1_CTRL_TRIG_WRITE_ERROR_RESET

#define DMA_CH1_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0)

◆ DMA_CH1_DBG_CTDREQ_ACCESS

#define DMA_CH1_DBG_CTDREQ_ACCESS "WC"

◆ DMA_CH1_DBG_CTDREQ_BITS

#define DMA_CH1_DBG_CTDREQ_BITS _u(0x0000003f)

◆ DMA_CH1_DBG_CTDREQ_LSB

#define DMA_CH1_DBG_CTDREQ_LSB _u(0)

◆ DMA_CH1_DBG_CTDREQ_MSB

#define DMA_CH1_DBG_CTDREQ_MSB _u(5)

◆ DMA_CH1_DBG_CTDREQ_OFFSET

#define DMA_CH1_DBG_CTDREQ_OFFSET _u(0x00000840)

◆ DMA_CH1_DBG_CTDREQ_RESET

#define DMA_CH1_DBG_CTDREQ_RESET _u(0x00000000)

◆ DMA_CH1_DBG_TCR_ACCESS

#define DMA_CH1_DBG_TCR_ACCESS "RO"

◆ DMA_CH1_DBG_TCR_BITS

#define DMA_CH1_DBG_TCR_BITS _u(0xffffffff)

◆ DMA_CH1_DBG_TCR_LSB

#define DMA_CH1_DBG_TCR_LSB _u(0)

◆ DMA_CH1_DBG_TCR_MSB

#define DMA_CH1_DBG_TCR_MSB _u(31)

◆ DMA_CH1_DBG_TCR_OFFSET

#define DMA_CH1_DBG_TCR_OFFSET _u(0x00000844)

◆ DMA_CH1_DBG_TCR_RESET

#define DMA_CH1_DBG_TCR_RESET _u(0x00000000)

◆ DMA_CH1_READ_ADDR_ACCESS

#define DMA_CH1_READ_ADDR_ACCESS "RW"

◆ DMA_CH1_READ_ADDR_BITS

#define DMA_CH1_READ_ADDR_BITS _u(0xffffffff)

◆ DMA_CH1_READ_ADDR_LSB

#define DMA_CH1_READ_ADDR_LSB _u(0)

◆ DMA_CH1_READ_ADDR_MSB

#define DMA_CH1_READ_ADDR_MSB _u(31)

◆ DMA_CH1_READ_ADDR_OFFSET

#define DMA_CH1_READ_ADDR_OFFSET _u(0x00000040)

◆ DMA_CH1_READ_ADDR_RESET

#define DMA_CH1_READ_ADDR_RESET _u(0x00000000)

◆ DMA_CH1_TRANS_COUNT_BITS

#define DMA_CH1_TRANS_COUNT_BITS _u(0xffffffff)

◆ DMA_CH1_TRANS_COUNT_COUNT_ACCESS

#define DMA_CH1_TRANS_COUNT_COUNT_ACCESS "RW"

◆ DMA_CH1_TRANS_COUNT_COUNT_BITS

#define DMA_CH1_TRANS_COUNT_COUNT_BITS _u(0x0fffffff)

◆ DMA_CH1_TRANS_COUNT_COUNT_LSB

#define DMA_CH1_TRANS_COUNT_COUNT_LSB _u(0)

◆ DMA_CH1_TRANS_COUNT_COUNT_MSB

#define DMA_CH1_TRANS_COUNT_COUNT_MSB _u(27)

◆ DMA_CH1_TRANS_COUNT_COUNT_RESET

#define DMA_CH1_TRANS_COUNT_COUNT_RESET _u(0x0000000)

◆ DMA_CH1_TRANS_COUNT_MODE_ACCESS

#define DMA_CH1_TRANS_COUNT_MODE_ACCESS "RW"

◆ DMA_CH1_TRANS_COUNT_MODE_BITS

#define DMA_CH1_TRANS_COUNT_MODE_BITS _u(0xf0000000)

◆ DMA_CH1_TRANS_COUNT_MODE_LSB

#define DMA_CH1_TRANS_COUNT_MODE_LSB _u(28)

◆ DMA_CH1_TRANS_COUNT_MODE_MSB

#define DMA_CH1_TRANS_COUNT_MODE_MSB _u(31)

◆ DMA_CH1_TRANS_COUNT_MODE_RESET

#define DMA_CH1_TRANS_COUNT_MODE_RESET _u(0x0)

◆ DMA_CH1_TRANS_COUNT_MODE_VALUE_ENDLESS

#define DMA_CH1_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf)

◆ DMA_CH1_TRANS_COUNT_MODE_VALUE_NORMAL

#define DMA_CH1_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0)

◆ DMA_CH1_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF

#define DMA_CH1_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1)

◆ DMA_CH1_TRANS_COUNT_OFFSET

#define DMA_CH1_TRANS_COUNT_OFFSET _u(0x00000048)

◆ DMA_CH1_TRANS_COUNT_RESET

#define DMA_CH1_TRANS_COUNT_RESET _u(0x00000000)

◆ DMA_CH1_WRITE_ADDR_ACCESS

#define DMA_CH1_WRITE_ADDR_ACCESS "RW"

◆ DMA_CH1_WRITE_ADDR_BITS

#define DMA_CH1_WRITE_ADDR_BITS _u(0xffffffff)

◆ DMA_CH1_WRITE_ADDR_LSB

#define DMA_CH1_WRITE_ADDR_LSB _u(0)

◆ DMA_CH1_WRITE_ADDR_MSB

#define DMA_CH1_WRITE_ADDR_MSB _u(31)

◆ DMA_CH1_WRITE_ADDR_OFFSET

#define DMA_CH1_WRITE_ADDR_OFFSET _u(0x00000044)

◆ DMA_CH1_WRITE_ADDR_RESET

#define DMA_CH1_WRITE_ADDR_RESET _u(0x00000000)

◆ DMA_CH2_AL1_CTRL_ACCESS

#define DMA_CH2_AL1_CTRL_ACCESS "RW"

◆ DMA_CH2_AL1_CTRL_BITS

#define DMA_CH2_AL1_CTRL_BITS _u(0xffffffff)

◆ DMA_CH2_AL1_CTRL_LSB

#define DMA_CH2_AL1_CTRL_LSB _u(0)

◆ DMA_CH2_AL1_CTRL_MSB

#define DMA_CH2_AL1_CTRL_MSB _u(31)

◆ DMA_CH2_AL1_CTRL_OFFSET

#define DMA_CH2_AL1_CTRL_OFFSET _u(0x00000090)

◆ DMA_CH2_AL1_CTRL_RESET

#define DMA_CH2_AL1_CTRL_RESET "-"

◆ DMA_CH2_AL1_READ_ADDR_ACCESS

#define DMA_CH2_AL1_READ_ADDR_ACCESS "RW"

◆ DMA_CH2_AL1_READ_ADDR_BITS

#define DMA_CH2_AL1_READ_ADDR_BITS _u(0xffffffff)

◆ DMA_CH2_AL1_READ_ADDR_LSB

#define DMA_CH2_AL1_READ_ADDR_LSB _u(0)

◆ DMA_CH2_AL1_READ_ADDR_MSB

#define DMA_CH2_AL1_READ_ADDR_MSB _u(31)

◆ DMA_CH2_AL1_READ_ADDR_OFFSET

#define DMA_CH2_AL1_READ_ADDR_OFFSET _u(0x00000094)

◆ DMA_CH2_AL1_READ_ADDR_RESET

#define DMA_CH2_AL1_READ_ADDR_RESET "-"

◆ DMA_CH2_AL1_TRANS_COUNT_TRIG_ACCESS

#define DMA_CH2_AL1_TRANS_COUNT_TRIG_ACCESS "RW"

◆ DMA_CH2_AL1_TRANS_COUNT_TRIG_BITS

#define DMA_CH2_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff)

◆ DMA_CH2_AL1_TRANS_COUNT_TRIG_LSB

#define DMA_CH2_AL1_TRANS_COUNT_TRIG_LSB _u(0)

◆ DMA_CH2_AL1_TRANS_COUNT_TRIG_MSB

#define DMA_CH2_AL1_TRANS_COUNT_TRIG_MSB _u(31)

◆ DMA_CH2_AL1_TRANS_COUNT_TRIG_OFFSET

#define DMA_CH2_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000009c)

◆ DMA_CH2_AL1_TRANS_COUNT_TRIG_RESET

#define DMA_CH2_AL1_TRANS_COUNT_TRIG_RESET "-"

◆ DMA_CH2_AL1_WRITE_ADDR_ACCESS

#define DMA_CH2_AL1_WRITE_ADDR_ACCESS "RW"

◆ DMA_CH2_AL1_WRITE_ADDR_BITS

#define DMA_CH2_AL1_WRITE_ADDR_BITS _u(0xffffffff)

◆ DMA_CH2_AL1_WRITE_ADDR_LSB

#define DMA_CH2_AL1_WRITE_ADDR_LSB _u(0)

◆ DMA_CH2_AL1_WRITE_ADDR_MSB

#define DMA_CH2_AL1_WRITE_ADDR_MSB _u(31)

◆ DMA_CH2_AL1_WRITE_ADDR_OFFSET

#define DMA_CH2_AL1_WRITE_ADDR_OFFSET _u(0x00000098)

◆ DMA_CH2_AL1_WRITE_ADDR_RESET

#define DMA_CH2_AL1_WRITE_ADDR_RESET "-"

◆ DMA_CH2_AL2_CTRL_ACCESS

#define DMA_CH2_AL2_CTRL_ACCESS "RW"

◆ DMA_CH2_AL2_CTRL_BITS

#define DMA_CH2_AL2_CTRL_BITS _u(0xffffffff)

◆ DMA_CH2_AL2_CTRL_LSB

#define DMA_CH2_AL2_CTRL_LSB _u(0)

◆ DMA_CH2_AL2_CTRL_MSB

#define DMA_CH2_AL2_CTRL_MSB _u(31)

◆ DMA_CH2_AL2_CTRL_OFFSET

#define DMA_CH2_AL2_CTRL_OFFSET _u(0x000000a0)

◆ DMA_CH2_AL2_CTRL_RESET

#define DMA_CH2_AL2_CTRL_RESET "-"

◆ DMA_CH2_AL2_READ_ADDR_ACCESS

#define DMA_CH2_AL2_READ_ADDR_ACCESS "RW"

◆ DMA_CH2_AL2_READ_ADDR_BITS

#define DMA_CH2_AL2_READ_ADDR_BITS _u(0xffffffff)

◆ DMA_CH2_AL2_READ_ADDR_LSB

#define DMA_CH2_AL2_READ_ADDR_LSB _u(0)

◆ DMA_CH2_AL2_READ_ADDR_MSB

#define DMA_CH2_AL2_READ_ADDR_MSB _u(31)

◆ DMA_CH2_AL2_READ_ADDR_OFFSET

#define DMA_CH2_AL2_READ_ADDR_OFFSET _u(0x000000a8)

◆ DMA_CH2_AL2_READ_ADDR_RESET

#define DMA_CH2_AL2_READ_ADDR_RESET "-"

◆ DMA_CH2_AL2_TRANS_COUNT_ACCESS

#define DMA_CH2_AL2_TRANS_COUNT_ACCESS "RW"

◆ DMA_CH2_AL2_TRANS_COUNT_BITS

#define DMA_CH2_AL2_TRANS_COUNT_BITS _u(0xffffffff)

◆ DMA_CH2_AL2_TRANS_COUNT_LSB

#define DMA_CH2_AL2_TRANS_COUNT_LSB _u(0)

◆ DMA_CH2_AL2_TRANS_COUNT_MSB

#define DMA_CH2_AL2_TRANS_COUNT_MSB _u(31)

◆ DMA_CH2_AL2_TRANS_COUNT_OFFSET

#define DMA_CH2_AL2_TRANS_COUNT_OFFSET _u(0x000000a4)

◆ DMA_CH2_AL2_TRANS_COUNT_RESET

#define DMA_CH2_AL2_TRANS_COUNT_RESET "-"

◆ DMA_CH2_AL2_WRITE_ADDR_TRIG_ACCESS

#define DMA_CH2_AL2_WRITE_ADDR_TRIG_ACCESS "RW"

◆ DMA_CH2_AL2_WRITE_ADDR_TRIG_BITS

#define DMA_CH2_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff)

◆ DMA_CH2_AL2_WRITE_ADDR_TRIG_LSB

#define DMA_CH2_AL2_WRITE_ADDR_TRIG_LSB _u(0)

◆ DMA_CH2_AL2_WRITE_ADDR_TRIG_MSB

#define DMA_CH2_AL2_WRITE_ADDR_TRIG_MSB _u(31)

◆ DMA_CH2_AL2_WRITE_ADDR_TRIG_OFFSET

#define DMA_CH2_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x000000ac)

◆ DMA_CH2_AL2_WRITE_ADDR_TRIG_RESET

#define DMA_CH2_AL2_WRITE_ADDR_TRIG_RESET "-"

◆ DMA_CH2_AL3_CTRL_ACCESS

#define DMA_CH2_AL3_CTRL_ACCESS "RW"

◆ DMA_CH2_AL3_CTRL_BITS

#define DMA_CH2_AL3_CTRL_BITS _u(0xffffffff)

◆ DMA_CH2_AL3_CTRL_LSB

#define DMA_CH2_AL3_CTRL_LSB _u(0)

◆ DMA_CH2_AL3_CTRL_MSB

#define DMA_CH2_AL3_CTRL_MSB _u(31)

◆ DMA_CH2_AL3_CTRL_OFFSET

#define DMA_CH2_AL3_CTRL_OFFSET _u(0x000000b0)

◆ DMA_CH2_AL3_CTRL_RESET

#define DMA_CH2_AL3_CTRL_RESET "-"

◆ DMA_CH2_AL3_READ_ADDR_TRIG_ACCESS

#define DMA_CH2_AL3_READ_ADDR_TRIG_ACCESS "RW"

◆ DMA_CH2_AL3_READ_ADDR_TRIG_BITS

#define DMA_CH2_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff)

◆ DMA_CH2_AL3_READ_ADDR_TRIG_LSB

#define DMA_CH2_AL3_READ_ADDR_TRIG_LSB _u(0)

◆ DMA_CH2_AL3_READ_ADDR_TRIG_MSB

#define DMA_CH2_AL3_READ_ADDR_TRIG_MSB _u(31)

◆ DMA_CH2_AL3_READ_ADDR_TRIG_OFFSET

#define DMA_CH2_AL3_READ_ADDR_TRIG_OFFSET _u(0x000000bc)

◆ DMA_CH2_AL3_READ_ADDR_TRIG_RESET

#define DMA_CH2_AL3_READ_ADDR_TRIG_RESET "-"

◆ DMA_CH2_AL3_TRANS_COUNT_ACCESS

#define DMA_CH2_AL3_TRANS_COUNT_ACCESS "RW"

◆ DMA_CH2_AL3_TRANS_COUNT_BITS

#define DMA_CH2_AL3_TRANS_COUNT_BITS _u(0xffffffff)

◆ DMA_CH2_AL3_TRANS_COUNT_LSB

#define DMA_CH2_AL3_TRANS_COUNT_LSB _u(0)

◆ DMA_CH2_AL3_TRANS_COUNT_MSB

#define DMA_CH2_AL3_TRANS_COUNT_MSB _u(31)

◆ DMA_CH2_AL3_TRANS_COUNT_OFFSET

#define DMA_CH2_AL3_TRANS_COUNT_OFFSET _u(0x000000b8)

◆ DMA_CH2_AL3_TRANS_COUNT_RESET

#define DMA_CH2_AL3_TRANS_COUNT_RESET "-"

◆ DMA_CH2_AL3_WRITE_ADDR_ACCESS

#define DMA_CH2_AL3_WRITE_ADDR_ACCESS "RW"

◆ DMA_CH2_AL3_WRITE_ADDR_BITS

#define DMA_CH2_AL3_WRITE_ADDR_BITS _u(0xffffffff)

◆ DMA_CH2_AL3_WRITE_ADDR_LSB

#define DMA_CH2_AL3_WRITE_ADDR_LSB _u(0)

◆ DMA_CH2_AL3_WRITE_ADDR_MSB

#define DMA_CH2_AL3_WRITE_ADDR_MSB _u(31)

◆ DMA_CH2_AL3_WRITE_ADDR_OFFSET

#define DMA_CH2_AL3_WRITE_ADDR_OFFSET _u(0x000000b4)

◆ DMA_CH2_AL3_WRITE_ADDR_RESET

#define DMA_CH2_AL3_WRITE_ADDR_RESET "-"

◆ DMA_CH2_CTRL_TRIG_AHB_ERROR_ACCESS

#define DMA_CH2_CTRL_TRIG_AHB_ERROR_ACCESS "RO"

◆ DMA_CH2_CTRL_TRIG_AHB_ERROR_BITS

#define DMA_CH2_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000)

◆ DMA_CH2_CTRL_TRIG_AHB_ERROR_LSB

#define DMA_CH2_CTRL_TRIG_AHB_ERROR_LSB _u(31)

◆ DMA_CH2_CTRL_TRIG_AHB_ERROR_MSB

#define DMA_CH2_CTRL_TRIG_AHB_ERROR_MSB _u(31)

◆ DMA_CH2_CTRL_TRIG_AHB_ERROR_RESET

#define DMA_CH2_CTRL_TRIG_AHB_ERROR_RESET _u(0x0)

◆ DMA_CH2_CTRL_TRIG_BITS

#define DMA_CH2_CTRL_TRIG_BITS _u(0xe7ffffff)

◆ DMA_CH2_CTRL_TRIG_BSWAP_ACCESS

#define DMA_CH2_CTRL_TRIG_BSWAP_ACCESS "RW"

◆ DMA_CH2_CTRL_TRIG_BSWAP_BITS

#define DMA_CH2_CTRL_TRIG_BSWAP_BITS _u(0x01000000)

◆ DMA_CH2_CTRL_TRIG_BSWAP_LSB

#define DMA_CH2_CTRL_TRIG_BSWAP_LSB _u(24)

◆ DMA_CH2_CTRL_TRIG_BSWAP_MSB

#define DMA_CH2_CTRL_TRIG_BSWAP_MSB _u(24)

◆ DMA_CH2_CTRL_TRIG_BSWAP_RESET

#define DMA_CH2_CTRL_TRIG_BSWAP_RESET _u(0x0)

◆ DMA_CH2_CTRL_TRIG_BUSY_ACCESS

#define DMA_CH2_CTRL_TRIG_BUSY_ACCESS "RO"

◆ DMA_CH2_CTRL_TRIG_BUSY_BITS

#define DMA_CH2_CTRL_TRIG_BUSY_BITS _u(0x04000000)

◆ DMA_CH2_CTRL_TRIG_BUSY_LSB

#define DMA_CH2_CTRL_TRIG_BUSY_LSB _u(26)

◆ DMA_CH2_CTRL_TRIG_BUSY_MSB

#define DMA_CH2_CTRL_TRIG_BUSY_MSB _u(26)

◆ DMA_CH2_CTRL_TRIG_BUSY_RESET

#define DMA_CH2_CTRL_TRIG_BUSY_RESET _u(0x0)

◆ DMA_CH2_CTRL_TRIG_CHAIN_TO_ACCESS

#define DMA_CH2_CTRL_TRIG_CHAIN_TO_ACCESS "RW"

◆ DMA_CH2_CTRL_TRIG_CHAIN_TO_BITS

#define DMA_CH2_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000)

◆ DMA_CH2_CTRL_TRIG_CHAIN_TO_LSB

#define DMA_CH2_CTRL_TRIG_CHAIN_TO_LSB _u(13)

◆ DMA_CH2_CTRL_TRIG_CHAIN_TO_MSB

#define DMA_CH2_CTRL_TRIG_CHAIN_TO_MSB _u(16)

◆ DMA_CH2_CTRL_TRIG_CHAIN_TO_RESET

#define DMA_CH2_CTRL_TRIG_CHAIN_TO_RESET _u(0x0)

◆ DMA_CH2_CTRL_TRIG_DATA_SIZE_ACCESS

#define DMA_CH2_CTRL_TRIG_DATA_SIZE_ACCESS "RW"

◆ DMA_CH2_CTRL_TRIG_DATA_SIZE_BITS

#define DMA_CH2_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c)

◆ DMA_CH2_CTRL_TRIG_DATA_SIZE_LSB

#define DMA_CH2_CTRL_TRIG_DATA_SIZE_LSB _u(2)

◆ DMA_CH2_CTRL_TRIG_DATA_SIZE_MSB

#define DMA_CH2_CTRL_TRIG_DATA_SIZE_MSB _u(3)

◆ DMA_CH2_CTRL_TRIG_DATA_SIZE_RESET

#define DMA_CH2_CTRL_TRIG_DATA_SIZE_RESET _u(0x0)

◆ DMA_CH2_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE

#define DMA_CH2_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0)

◆ DMA_CH2_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD

#define DMA_CH2_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1)

◆ DMA_CH2_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD

#define DMA_CH2_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2)

◆ DMA_CH2_CTRL_TRIG_EN_ACCESS

#define DMA_CH2_CTRL_TRIG_EN_ACCESS "RW"

◆ DMA_CH2_CTRL_TRIG_EN_BITS

#define DMA_CH2_CTRL_TRIG_EN_BITS _u(0x00000001)

◆ DMA_CH2_CTRL_TRIG_EN_LSB

#define DMA_CH2_CTRL_TRIG_EN_LSB _u(0)

◆ DMA_CH2_CTRL_TRIG_EN_MSB

#define DMA_CH2_CTRL_TRIG_EN_MSB _u(0)

◆ DMA_CH2_CTRL_TRIG_EN_RESET

#define DMA_CH2_CTRL_TRIG_EN_RESET _u(0x0)

◆ DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_ACCESS

#define DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW"

◆ DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_BITS

#define DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002)

◆ DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_LSB

#define DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1)

◆ DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_MSB

#define DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1)

◆ DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_RESET

#define DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0)

◆ DMA_CH2_CTRL_TRIG_INCR_READ_ACCESS

#define DMA_CH2_CTRL_TRIG_INCR_READ_ACCESS "RW"

◆ DMA_CH2_CTRL_TRIG_INCR_READ_BITS

#define DMA_CH2_CTRL_TRIG_INCR_READ_BITS _u(0x00000010)

◆ DMA_CH2_CTRL_TRIG_INCR_READ_LSB

#define DMA_CH2_CTRL_TRIG_INCR_READ_LSB _u(4)

◆ DMA_CH2_CTRL_TRIG_INCR_READ_MSB

#define DMA_CH2_CTRL_TRIG_INCR_READ_MSB _u(4)

◆ DMA_CH2_CTRL_TRIG_INCR_READ_RESET

#define DMA_CH2_CTRL_TRIG_INCR_READ_RESET _u(0x0)

◆ DMA_CH2_CTRL_TRIG_INCR_READ_REV_ACCESS

#define DMA_CH2_CTRL_TRIG_INCR_READ_REV_ACCESS "RW"

◆ DMA_CH2_CTRL_TRIG_INCR_READ_REV_BITS

#define DMA_CH2_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020)

◆ DMA_CH2_CTRL_TRIG_INCR_READ_REV_LSB

#define DMA_CH2_CTRL_TRIG_INCR_READ_REV_LSB _u(5)

◆ DMA_CH2_CTRL_TRIG_INCR_READ_REV_MSB

#define DMA_CH2_CTRL_TRIG_INCR_READ_REV_MSB _u(5)

◆ DMA_CH2_CTRL_TRIG_INCR_READ_REV_RESET

#define DMA_CH2_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0)

◆ DMA_CH2_CTRL_TRIG_INCR_WRITE_ACCESS

#define DMA_CH2_CTRL_TRIG_INCR_WRITE_ACCESS "RW"

◆ DMA_CH2_CTRL_TRIG_INCR_WRITE_BITS

#define DMA_CH2_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040)

◆ DMA_CH2_CTRL_TRIG_INCR_WRITE_LSB

#define DMA_CH2_CTRL_TRIG_INCR_WRITE_LSB _u(6)

◆ DMA_CH2_CTRL_TRIG_INCR_WRITE_MSB

#define DMA_CH2_CTRL_TRIG_INCR_WRITE_MSB _u(6)

◆ DMA_CH2_CTRL_TRIG_INCR_WRITE_RESET

#define DMA_CH2_CTRL_TRIG_INCR_WRITE_RESET _u(0x0)

◆ DMA_CH2_CTRL_TRIG_INCR_WRITE_REV_ACCESS

#define DMA_CH2_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW"

◆ DMA_CH2_CTRL_TRIG_INCR_WRITE_REV_BITS

#define DMA_CH2_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080)

◆ DMA_CH2_CTRL_TRIG_INCR_WRITE_REV_LSB

#define DMA_CH2_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7)

◆ DMA_CH2_CTRL_TRIG_INCR_WRITE_REV_MSB

#define DMA_CH2_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7)

◆ DMA_CH2_CTRL_TRIG_INCR_WRITE_REV_RESET

#define DMA_CH2_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0)

◆ DMA_CH2_CTRL_TRIG_IRQ_QUIET_ACCESS

#define DMA_CH2_CTRL_TRIG_IRQ_QUIET_ACCESS "RW"

◆ DMA_CH2_CTRL_TRIG_IRQ_QUIET_BITS

#define DMA_CH2_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000)

◆ DMA_CH2_CTRL_TRIG_IRQ_QUIET_LSB

#define DMA_CH2_CTRL_TRIG_IRQ_QUIET_LSB _u(23)

◆ DMA_CH2_CTRL_TRIG_IRQ_QUIET_MSB

#define DMA_CH2_CTRL_TRIG_IRQ_QUIET_MSB _u(23)

◆ DMA_CH2_CTRL_TRIG_IRQ_QUIET_RESET

#define DMA_CH2_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0)

◆ DMA_CH2_CTRL_TRIG_OFFSET

#define DMA_CH2_CTRL_TRIG_OFFSET _u(0x0000008c)

◆ DMA_CH2_CTRL_TRIG_READ_ERROR_ACCESS

#define DMA_CH2_CTRL_TRIG_READ_ERROR_ACCESS "WC"

◆ DMA_CH2_CTRL_TRIG_READ_ERROR_BITS

#define DMA_CH2_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000)

◆ DMA_CH2_CTRL_TRIG_READ_ERROR_LSB

#define DMA_CH2_CTRL_TRIG_READ_ERROR_LSB _u(30)

◆ DMA_CH2_CTRL_TRIG_READ_ERROR_MSB

#define DMA_CH2_CTRL_TRIG_READ_ERROR_MSB _u(30)

◆ DMA_CH2_CTRL_TRIG_READ_ERROR_RESET

#define DMA_CH2_CTRL_TRIG_READ_ERROR_RESET _u(0x0)

◆ DMA_CH2_CTRL_TRIG_RESET

#define DMA_CH2_CTRL_TRIG_RESET _u(0x00000000)

◆ DMA_CH2_CTRL_TRIG_RING_SEL_ACCESS

#define DMA_CH2_CTRL_TRIG_RING_SEL_ACCESS "RW"

◆ DMA_CH2_CTRL_TRIG_RING_SEL_BITS

#define DMA_CH2_CTRL_TRIG_RING_SEL_BITS _u(0x00001000)

◆ DMA_CH2_CTRL_TRIG_RING_SEL_LSB

#define DMA_CH2_CTRL_TRIG_RING_SEL_LSB _u(12)

◆ DMA_CH2_CTRL_TRIG_RING_SEL_MSB

#define DMA_CH2_CTRL_TRIG_RING_SEL_MSB _u(12)

◆ DMA_CH2_CTRL_TRIG_RING_SEL_RESET

#define DMA_CH2_CTRL_TRIG_RING_SEL_RESET _u(0x0)

◆ DMA_CH2_CTRL_TRIG_RING_SIZE_ACCESS

#define DMA_CH2_CTRL_TRIG_RING_SIZE_ACCESS "RW"

◆ DMA_CH2_CTRL_TRIG_RING_SIZE_BITS

#define DMA_CH2_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00)

◆ DMA_CH2_CTRL_TRIG_RING_SIZE_LSB

#define DMA_CH2_CTRL_TRIG_RING_SIZE_LSB _u(8)

◆ DMA_CH2_CTRL_TRIG_RING_SIZE_MSB

#define DMA_CH2_CTRL_TRIG_RING_SIZE_MSB _u(11)

◆ DMA_CH2_CTRL_TRIG_RING_SIZE_RESET

#define DMA_CH2_CTRL_TRIG_RING_SIZE_RESET _u(0x0)

◆ DMA_CH2_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE

#define DMA_CH2_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0)

◆ DMA_CH2_CTRL_TRIG_SNIFF_EN_ACCESS

#define DMA_CH2_CTRL_TRIG_SNIFF_EN_ACCESS "RW"

◆ DMA_CH2_CTRL_TRIG_SNIFF_EN_BITS

#define DMA_CH2_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000)

◆ DMA_CH2_CTRL_TRIG_SNIFF_EN_LSB

#define DMA_CH2_CTRL_TRIG_SNIFF_EN_LSB _u(25)

◆ DMA_CH2_CTRL_TRIG_SNIFF_EN_MSB

#define DMA_CH2_CTRL_TRIG_SNIFF_EN_MSB _u(25)

◆ DMA_CH2_CTRL_TRIG_SNIFF_EN_RESET

#define DMA_CH2_CTRL_TRIG_SNIFF_EN_RESET _u(0x0)

◆ DMA_CH2_CTRL_TRIG_TREQ_SEL_ACCESS

#define DMA_CH2_CTRL_TRIG_TREQ_SEL_ACCESS "RW"

◆ DMA_CH2_CTRL_TRIG_TREQ_SEL_BITS

#define DMA_CH2_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000)

◆ DMA_CH2_CTRL_TRIG_TREQ_SEL_LSB

#define DMA_CH2_CTRL_TRIG_TREQ_SEL_LSB _u(17)

◆ DMA_CH2_CTRL_TRIG_TREQ_SEL_MSB

#define DMA_CH2_CTRL_TRIG_TREQ_SEL_MSB _u(22)

◆ DMA_CH2_CTRL_TRIG_TREQ_SEL_RESET

#define DMA_CH2_CTRL_TRIG_TREQ_SEL_RESET _u(0x00)

◆ DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT

#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f)

◆ DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0

#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b)

◆ DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1

#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c)

◆ DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2

#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d)

◆ DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3

#define DMA_CH2_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e)

◆ DMA_CH2_CTRL_TRIG_WRITE_ERROR_ACCESS

#define DMA_CH2_CTRL_TRIG_WRITE_ERROR_ACCESS "WC"

◆ DMA_CH2_CTRL_TRIG_WRITE_ERROR_BITS

#define DMA_CH2_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000)

◆ DMA_CH2_CTRL_TRIG_WRITE_ERROR_LSB

#define DMA_CH2_CTRL_TRIG_WRITE_ERROR_LSB _u(29)

◆ DMA_CH2_CTRL_TRIG_WRITE_ERROR_MSB

#define DMA_CH2_CTRL_TRIG_WRITE_ERROR_MSB _u(29)

◆ DMA_CH2_CTRL_TRIG_WRITE_ERROR_RESET

#define DMA_CH2_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0)

◆ DMA_CH2_DBG_CTDREQ_ACCESS

#define DMA_CH2_DBG_CTDREQ_ACCESS "WC"

◆ DMA_CH2_DBG_CTDREQ_BITS

#define DMA_CH2_DBG_CTDREQ_BITS _u(0x0000003f)

◆ DMA_CH2_DBG_CTDREQ_LSB

#define DMA_CH2_DBG_CTDREQ_LSB _u(0)

◆ DMA_CH2_DBG_CTDREQ_MSB

#define DMA_CH2_DBG_CTDREQ_MSB _u(5)

◆ DMA_CH2_DBG_CTDREQ_OFFSET

#define DMA_CH2_DBG_CTDREQ_OFFSET _u(0x00000880)

◆ DMA_CH2_DBG_CTDREQ_RESET

#define DMA_CH2_DBG_CTDREQ_RESET _u(0x00000000)

◆ DMA_CH2_DBG_TCR_ACCESS

#define DMA_CH2_DBG_TCR_ACCESS "RO"

◆ DMA_CH2_DBG_TCR_BITS

#define DMA_CH2_DBG_TCR_BITS _u(0xffffffff)

◆ DMA_CH2_DBG_TCR_LSB

#define DMA_CH2_DBG_TCR_LSB _u(0)

◆ DMA_CH2_DBG_TCR_MSB

#define DMA_CH2_DBG_TCR_MSB _u(31)

◆ DMA_CH2_DBG_TCR_OFFSET

#define DMA_CH2_DBG_TCR_OFFSET _u(0x00000884)

◆ DMA_CH2_DBG_TCR_RESET

#define DMA_CH2_DBG_TCR_RESET _u(0x00000000)

◆ DMA_CH2_READ_ADDR_ACCESS

#define DMA_CH2_READ_ADDR_ACCESS "RW"

◆ DMA_CH2_READ_ADDR_BITS

#define DMA_CH2_READ_ADDR_BITS _u(0xffffffff)

◆ DMA_CH2_READ_ADDR_LSB

#define DMA_CH2_READ_ADDR_LSB _u(0)

◆ DMA_CH2_READ_ADDR_MSB

#define DMA_CH2_READ_ADDR_MSB _u(31)

◆ DMA_CH2_READ_ADDR_OFFSET

#define DMA_CH2_READ_ADDR_OFFSET _u(0x00000080)

◆ DMA_CH2_READ_ADDR_RESET

#define DMA_CH2_READ_ADDR_RESET _u(0x00000000)

◆ DMA_CH2_TRANS_COUNT_BITS

#define DMA_CH2_TRANS_COUNT_BITS _u(0xffffffff)

◆ DMA_CH2_TRANS_COUNT_COUNT_ACCESS

#define DMA_CH2_TRANS_COUNT_COUNT_ACCESS "RW"

◆ DMA_CH2_TRANS_COUNT_COUNT_BITS

#define DMA_CH2_TRANS_COUNT_COUNT_BITS _u(0x0fffffff)

◆ DMA_CH2_TRANS_COUNT_COUNT_LSB

#define DMA_CH2_TRANS_COUNT_COUNT_LSB _u(0)

◆ DMA_CH2_TRANS_COUNT_COUNT_MSB

#define DMA_CH2_TRANS_COUNT_COUNT_MSB _u(27)

◆ DMA_CH2_TRANS_COUNT_COUNT_RESET

#define DMA_CH2_TRANS_COUNT_COUNT_RESET _u(0x0000000)

◆ DMA_CH2_TRANS_COUNT_MODE_ACCESS

#define DMA_CH2_TRANS_COUNT_MODE_ACCESS "RW"

◆ DMA_CH2_TRANS_COUNT_MODE_BITS

#define DMA_CH2_TRANS_COUNT_MODE_BITS _u(0xf0000000)

◆ DMA_CH2_TRANS_COUNT_MODE_LSB

#define DMA_CH2_TRANS_COUNT_MODE_LSB _u(28)

◆ DMA_CH2_TRANS_COUNT_MODE_MSB

#define DMA_CH2_TRANS_COUNT_MODE_MSB _u(31)

◆ DMA_CH2_TRANS_COUNT_MODE_RESET

#define DMA_CH2_TRANS_COUNT_MODE_RESET _u(0x0)

◆ DMA_CH2_TRANS_COUNT_MODE_VALUE_ENDLESS

#define DMA_CH2_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf)

◆ DMA_CH2_TRANS_COUNT_MODE_VALUE_NORMAL

#define DMA_CH2_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0)

◆ DMA_CH2_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF

#define DMA_CH2_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1)

◆ DMA_CH2_TRANS_COUNT_OFFSET

#define DMA_CH2_TRANS_COUNT_OFFSET _u(0x00000088)

◆ DMA_CH2_TRANS_COUNT_RESET

#define DMA_CH2_TRANS_COUNT_RESET _u(0x00000000)

◆ DMA_CH2_WRITE_ADDR_ACCESS

#define DMA_CH2_WRITE_ADDR_ACCESS "RW"

◆ DMA_CH2_WRITE_ADDR_BITS

#define DMA_CH2_WRITE_ADDR_BITS _u(0xffffffff)

◆ DMA_CH2_WRITE_ADDR_LSB

#define DMA_CH2_WRITE_ADDR_LSB _u(0)

◆ DMA_CH2_WRITE_ADDR_MSB

#define DMA_CH2_WRITE_ADDR_MSB _u(31)

◆ DMA_CH2_WRITE_ADDR_OFFSET

#define DMA_CH2_WRITE_ADDR_OFFSET _u(0x00000084)

◆ DMA_CH2_WRITE_ADDR_RESET

#define DMA_CH2_WRITE_ADDR_RESET _u(0x00000000)

◆ DMA_CH3_AL1_CTRL_ACCESS

#define DMA_CH3_AL1_CTRL_ACCESS "RW"

◆ DMA_CH3_AL1_CTRL_BITS

#define DMA_CH3_AL1_CTRL_BITS _u(0xffffffff)

◆ DMA_CH3_AL1_CTRL_LSB

#define DMA_CH3_AL1_CTRL_LSB _u(0)

◆ DMA_CH3_AL1_CTRL_MSB

#define DMA_CH3_AL1_CTRL_MSB _u(31)

◆ DMA_CH3_AL1_CTRL_OFFSET

#define DMA_CH3_AL1_CTRL_OFFSET _u(0x000000d0)

◆ DMA_CH3_AL1_CTRL_RESET

#define DMA_CH3_AL1_CTRL_RESET "-"

◆ DMA_CH3_AL1_READ_ADDR_ACCESS

#define DMA_CH3_AL1_READ_ADDR_ACCESS "RW"

◆ DMA_CH3_AL1_READ_ADDR_BITS

#define DMA_CH3_AL1_READ_ADDR_BITS _u(0xffffffff)

◆ DMA_CH3_AL1_READ_ADDR_LSB

#define DMA_CH3_AL1_READ_ADDR_LSB _u(0)

◆ DMA_CH3_AL1_READ_ADDR_MSB

#define DMA_CH3_AL1_READ_ADDR_MSB _u(31)

◆ DMA_CH3_AL1_READ_ADDR_OFFSET

#define DMA_CH3_AL1_READ_ADDR_OFFSET _u(0x000000d4)

◆ DMA_CH3_AL1_READ_ADDR_RESET

#define DMA_CH3_AL1_READ_ADDR_RESET "-"

◆ DMA_CH3_AL1_TRANS_COUNT_TRIG_ACCESS

#define DMA_CH3_AL1_TRANS_COUNT_TRIG_ACCESS "RW"

◆ DMA_CH3_AL1_TRANS_COUNT_TRIG_BITS

#define DMA_CH3_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff)

◆ DMA_CH3_AL1_TRANS_COUNT_TRIG_LSB

#define DMA_CH3_AL1_TRANS_COUNT_TRIG_LSB _u(0)

◆ DMA_CH3_AL1_TRANS_COUNT_TRIG_MSB

#define DMA_CH3_AL1_TRANS_COUNT_TRIG_MSB _u(31)

◆ DMA_CH3_AL1_TRANS_COUNT_TRIG_OFFSET

#define DMA_CH3_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x000000dc)

◆ DMA_CH3_AL1_TRANS_COUNT_TRIG_RESET

#define DMA_CH3_AL1_TRANS_COUNT_TRIG_RESET "-"

◆ DMA_CH3_AL1_WRITE_ADDR_ACCESS

#define DMA_CH3_AL1_WRITE_ADDR_ACCESS "RW"

◆ DMA_CH3_AL1_WRITE_ADDR_BITS

#define DMA_CH3_AL1_WRITE_ADDR_BITS _u(0xffffffff)

◆ DMA_CH3_AL1_WRITE_ADDR_LSB

#define DMA_CH3_AL1_WRITE_ADDR_LSB _u(0)

◆ DMA_CH3_AL1_WRITE_ADDR_MSB

#define DMA_CH3_AL1_WRITE_ADDR_MSB _u(31)

◆ DMA_CH3_AL1_WRITE_ADDR_OFFSET

#define DMA_CH3_AL1_WRITE_ADDR_OFFSET _u(0x000000d8)

◆ DMA_CH3_AL1_WRITE_ADDR_RESET

#define DMA_CH3_AL1_WRITE_ADDR_RESET "-"

◆ DMA_CH3_AL2_CTRL_ACCESS

#define DMA_CH3_AL2_CTRL_ACCESS "RW"

◆ DMA_CH3_AL2_CTRL_BITS

#define DMA_CH3_AL2_CTRL_BITS _u(0xffffffff)

◆ DMA_CH3_AL2_CTRL_LSB

#define DMA_CH3_AL2_CTRL_LSB _u(0)

◆ DMA_CH3_AL2_CTRL_MSB

#define DMA_CH3_AL2_CTRL_MSB _u(31)

◆ DMA_CH3_AL2_CTRL_OFFSET

#define DMA_CH3_AL2_CTRL_OFFSET _u(0x000000e0)

◆ DMA_CH3_AL2_CTRL_RESET

#define DMA_CH3_AL2_CTRL_RESET "-"

◆ DMA_CH3_AL2_READ_ADDR_ACCESS

#define DMA_CH3_AL2_READ_ADDR_ACCESS "RW"

◆ DMA_CH3_AL2_READ_ADDR_BITS

#define DMA_CH3_AL2_READ_ADDR_BITS _u(0xffffffff)

◆ DMA_CH3_AL2_READ_ADDR_LSB

#define DMA_CH3_AL2_READ_ADDR_LSB _u(0)

◆ DMA_CH3_AL2_READ_ADDR_MSB

#define DMA_CH3_AL2_READ_ADDR_MSB _u(31)

◆ DMA_CH3_AL2_READ_ADDR_OFFSET

#define DMA_CH3_AL2_READ_ADDR_OFFSET _u(0x000000e8)

◆ DMA_CH3_AL2_READ_ADDR_RESET

#define DMA_CH3_AL2_READ_ADDR_RESET "-"

◆ DMA_CH3_AL2_TRANS_COUNT_ACCESS

#define DMA_CH3_AL2_TRANS_COUNT_ACCESS "RW"

◆ DMA_CH3_AL2_TRANS_COUNT_BITS

#define DMA_CH3_AL2_TRANS_COUNT_BITS _u(0xffffffff)

◆ DMA_CH3_AL2_TRANS_COUNT_LSB

#define DMA_CH3_AL2_TRANS_COUNT_LSB _u(0)

◆ DMA_CH3_AL2_TRANS_COUNT_MSB

#define DMA_CH3_AL2_TRANS_COUNT_MSB _u(31)

◆ DMA_CH3_AL2_TRANS_COUNT_OFFSET

#define DMA_CH3_AL2_TRANS_COUNT_OFFSET _u(0x000000e4)

◆ DMA_CH3_AL2_TRANS_COUNT_RESET

#define DMA_CH3_AL2_TRANS_COUNT_RESET "-"

◆ DMA_CH3_AL2_WRITE_ADDR_TRIG_ACCESS

#define DMA_CH3_AL2_WRITE_ADDR_TRIG_ACCESS "RW"

◆ DMA_CH3_AL2_WRITE_ADDR_TRIG_BITS

#define DMA_CH3_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff)

◆ DMA_CH3_AL2_WRITE_ADDR_TRIG_LSB

#define DMA_CH3_AL2_WRITE_ADDR_TRIG_LSB _u(0)

◆ DMA_CH3_AL2_WRITE_ADDR_TRIG_MSB

#define DMA_CH3_AL2_WRITE_ADDR_TRIG_MSB _u(31)

◆ DMA_CH3_AL2_WRITE_ADDR_TRIG_OFFSET

#define DMA_CH3_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x000000ec)

◆ DMA_CH3_AL2_WRITE_ADDR_TRIG_RESET

#define DMA_CH3_AL2_WRITE_ADDR_TRIG_RESET "-"

◆ DMA_CH3_AL3_CTRL_ACCESS

#define DMA_CH3_AL3_CTRL_ACCESS "RW"

◆ DMA_CH3_AL3_CTRL_BITS

#define DMA_CH3_AL3_CTRL_BITS _u(0xffffffff)

◆ DMA_CH3_AL3_CTRL_LSB

#define DMA_CH3_AL3_CTRL_LSB _u(0)

◆ DMA_CH3_AL3_CTRL_MSB

#define DMA_CH3_AL3_CTRL_MSB _u(31)

◆ DMA_CH3_AL3_CTRL_OFFSET

#define DMA_CH3_AL3_CTRL_OFFSET _u(0x000000f0)

◆ DMA_CH3_AL3_CTRL_RESET

#define DMA_CH3_AL3_CTRL_RESET "-"

◆ DMA_CH3_AL3_READ_ADDR_TRIG_ACCESS

#define DMA_CH3_AL3_READ_ADDR_TRIG_ACCESS "RW"

◆ DMA_CH3_AL3_READ_ADDR_TRIG_BITS

#define DMA_CH3_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff)

◆ DMA_CH3_AL3_READ_ADDR_TRIG_LSB

#define DMA_CH3_AL3_READ_ADDR_TRIG_LSB _u(0)

◆ DMA_CH3_AL3_READ_ADDR_TRIG_MSB

#define DMA_CH3_AL3_READ_ADDR_TRIG_MSB _u(31)

◆ DMA_CH3_AL3_READ_ADDR_TRIG_OFFSET

#define DMA_CH3_AL3_READ_ADDR_TRIG_OFFSET _u(0x000000fc)

◆ DMA_CH3_AL3_READ_ADDR_TRIG_RESET

#define DMA_CH3_AL3_READ_ADDR_TRIG_RESET "-"

◆ DMA_CH3_AL3_TRANS_COUNT_ACCESS

#define DMA_CH3_AL3_TRANS_COUNT_ACCESS "RW"

◆ DMA_CH3_AL3_TRANS_COUNT_BITS

#define DMA_CH3_AL3_TRANS_COUNT_BITS _u(0xffffffff)

◆ DMA_CH3_AL3_TRANS_COUNT_LSB

#define DMA_CH3_AL3_TRANS_COUNT_LSB _u(0)

◆ DMA_CH3_AL3_TRANS_COUNT_MSB

#define DMA_CH3_AL3_TRANS_COUNT_MSB _u(31)

◆ DMA_CH3_AL3_TRANS_COUNT_OFFSET

#define DMA_CH3_AL3_TRANS_COUNT_OFFSET _u(0x000000f8)

◆ DMA_CH3_AL3_TRANS_COUNT_RESET

#define DMA_CH3_AL3_TRANS_COUNT_RESET "-"

◆ DMA_CH3_AL3_WRITE_ADDR_ACCESS

#define DMA_CH3_AL3_WRITE_ADDR_ACCESS "RW"

◆ DMA_CH3_AL3_WRITE_ADDR_BITS

#define DMA_CH3_AL3_WRITE_ADDR_BITS _u(0xffffffff)

◆ DMA_CH3_AL3_WRITE_ADDR_LSB

#define DMA_CH3_AL3_WRITE_ADDR_LSB _u(0)

◆ DMA_CH3_AL3_WRITE_ADDR_MSB

#define DMA_CH3_AL3_WRITE_ADDR_MSB _u(31)

◆ DMA_CH3_AL3_WRITE_ADDR_OFFSET

#define DMA_CH3_AL3_WRITE_ADDR_OFFSET _u(0x000000f4)

◆ DMA_CH3_AL3_WRITE_ADDR_RESET

#define DMA_CH3_AL3_WRITE_ADDR_RESET "-"

◆ DMA_CH3_CTRL_TRIG_AHB_ERROR_ACCESS

#define DMA_CH3_CTRL_TRIG_AHB_ERROR_ACCESS "RO"

◆ DMA_CH3_CTRL_TRIG_AHB_ERROR_BITS

#define DMA_CH3_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000)

◆ DMA_CH3_CTRL_TRIG_AHB_ERROR_LSB

#define DMA_CH3_CTRL_TRIG_AHB_ERROR_LSB _u(31)

◆ DMA_CH3_CTRL_TRIG_AHB_ERROR_MSB

#define DMA_CH3_CTRL_TRIG_AHB_ERROR_MSB _u(31)

◆ DMA_CH3_CTRL_TRIG_AHB_ERROR_RESET

#define DMA_CH3_CTRL_TRIG_AHB_ERROR_RESET _u(0x0)

◆ DMA_CH3_CTRL_TRIG_BITS

#define DMA_CH3_CTRL_TRIG_BITS _u(0xe7ffffff)

◆ DMA_CH3_CTRL_TRIG_BSWAP_ACCESS

#define DMA_CH3_CTRL_TRIG_BSWAP_ACCESS "RW"

◆ DMA_CH3_CTRL_TRIG_BSWAP_BITS

#define DMA_CH3_CTRL_TRIG_BSWAP_BITS _u(0x01000000)

◆ DMA_CH3_CTRL_TRIG_BSWAP_LSB

#define DMA_CH3_CTRL_TRIG_BSWAP_LSB _u(24)

◆ DMA_CH3_CTRL_TRIG_BSWAP_MSB

#define DMA_CH3_CTRL_TRIG_BSWAP_MSB _u(24)

◆ DMA_CH3_CTRL_TRIG_BSWAP_RESET

#define DMA_CH3_CTRL_TRIG_BSWAP_RESET _u(0x0)

◆ DMA_CH3_CTRL_TRIG_BUSY_ACCESS

#define DMA_CH3_CTRL_TRIG_BUSY_ACCESS "RO"

◆ DMA_CH3_CTRL_TRIG_BUSY_BITS

#define DMA_CH3_CTRL_TRIG_BUSY_BITS _u(0x04000000)

◆ DMA_CH3_CTRL_TRIG_BUSY_LSB

#define DMA_CH3_CTRL_TRIG_BUSY_LSB _u(26)

◆ DMA_CH3_CTRL_TRIG_BUSY_MSB

#define DMA_CH3_CTRL_TRIG_BUSY_MSB _u(26)

◆ DMA_CH3_CTRL_TRIG_BUSY_RESET

#define DMA_CH3_CTRL_TRIG_BUSY_RESET _u(0x0)

◆ DMA_CH3_CTRL_TRIG_CHAIN_TO_ACCESS

#define DMA_CH3_CTRL_TRIG_CHAIN_TO_ACCESS "RW"

◆ DMA_CH3_CTRL_TRIG_CHAIN_TO_BITS

#define DMA_CH3_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000)

◆ DMA_CH3_CTRL_TRIG_CHAIN_TO_LSB

#define DMA_CH3_CTRL_TRIG_CHAIN_TO_LSB _u(13)

◆ DMA_CH3_CTRL_TRIG_CHAIN_TO_MSB

#define DMA_CH3_CTRL_TRIG_CHAIN_TO_MSB _u(16)

◆ DMA_CH3_CTRL_TRIG_CHAIN_TO_RESET

#define DMA_CH3_CTRL_TRIG_CHAIN_TO_RESET _u(0x0)

◆ DMA_CH3_CTRL_TRIG_DATA_SIZE_ACCESS

#define DMA_CH3_CTRL_TRIG_DATA_SIZE_ACCESS "RW"

◆ DMA_CH3_CTRL_TRIG_DATA_SIZE_BITS

#define DMA_CH3_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c)

◆ DMA_CH3_CTRL_TRIG_DATA_SIZE_LSB

#define DMA_CH3_CTRL_TRIG_DATA_SIZE_LSB _u(2)

◆ DMA_CH3_CTRL_TRIG_DATA_SIZE_MSB

#define DMA_CH3_CTRL_TRIG_DATA_SIZE_MSB _u(3)

◆ DMA_CH3_CTRL_TRIG_DATA_SIZE_RESET

#define DMA_CH3_CTRL_TRIG_DATA_SIZE_RESET _u(0x0)

◆ DMA_CH3_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE

#define DMA_CH3_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0)

◆ DMA_CH3_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD

#define DMA_CH3_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1)

◆ DMA_CH3_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD

#define DMA_CH3_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2)

◆ DMA_CH3_CTRL_TRIG_EN_ACCESS

#define DMA_CH3_CTRL_TRIG_EN_ACCESS "RW"

◆ DMA_CH3_CTRL_TRIG_EN_BITS

#define DMA_CH3_CTRL_TRIG_EN_BITS _u(0x00000001)

◆ DMA_CH3_CTRL_TRIG_EN_LSB

#define DMA_CH3_CTRL_TRIG_EN_LSB _u(0)

◆ DMA_CH3_CTRL_TRIG_EN_MSB

#define DMA_CH3_CTRL_TRIG_EN_MSB _u(0)

◆ DMA_CH3_CTRL_TRIG_EN_RESET

#define DMA_CH3_CTRL_TRIG_EN_RESET _u(0x0)

◆ DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_ACCESS

#define DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW"

◆ DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_BITS

#define DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002)

◆ DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_LSB

#define DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1)

◆ DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_MSB

#define DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1)

◆ DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_RESET

#define DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0)

◆ DMA_CH3_CTRL_TRIG_INCR_READ_ACCESS

#define DMA_CH3_CTRL_TRIG_INCR_READ_ACCESS "RW"

◆ DMA_CH3_CTRL_TRIG_INCR_READ_BITS

#define DMA_CH3_CTRL_TRIG_INCR_READ_BITS _u(0x00000010)

◆ DMA_CH3_CTRL_TRIG_INCR_READ_LSB

#define DMA_CH3_CTRL_TRIG_INCR_READ_LSB _u(4)

◆ DMA_CH3_CTRL_TRIG_INCR_READ_MSB

#define DMA_CH3_CTRL_TRIG_INCR_READ_MSB _u(4)

◆ DMA_CH3_CTRL_TRIG_INCR_READ_RESET

#define DMA_CH3_CTRL_TRIG_INCR_READ_RESET _u(0x0)

◆ DMA_CH3_CTRL_TRIG_INCR_READ_REV_ACCESS

#define DMA_CH3_CTRL_TRIG_INCR_READ_REV_ACCESS "RW"

◆ DMA_CH3_CTRL_TRIG_INCR_READ_REV_BITS

#define DMA_CH3_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020)

◆ DMA_CH3_CTRL_TRIG_INCR_READ_REV_LSB

#define DMA_CH3_CTRL_TRIG_INCR_READ_REV_LSB _u(5)

◆ DMA_CH3_CTRL_TRIG_INCR_READ_REV_MSB

#define DMA_CH3_CTRL_TRIG_INCR_READ_REV_MSB _u(5)

◆ DMA_CH3_CTRL_TRIG_INCR_READ_REV_RESET

#define DMA_CH3_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0)

◆ DMA_CH3_CTRL_TRIG_INCR_WRITE_ACCESS

#define DMA_CH3_CTRL_TRIG_INCR_WRITE_ACCESS "RW"

◆ DMA_CH3_CTRL_TRIG_INCR_WRITE_BITS

#define DMA_CH3_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040)

◆ DMA_CH3_CTRL_TRIG_INCR_WRITE_LSB

#define DMA_CH3_CTRL_TRIG_INCR_WRITE_LSB _u(6)

◆ DMA_CH3_CTRL_TRIG_INCR_WRITE_MSB

#define DMA_CH3_CTRL_TRIG_INCR_WRITE_MSB _u(6)

◆ DMA_CH3_CTRL_TRIG_INCR_WRITE_RESET

#define DMA_CH3_CTRL_TRIG_INCR_WRITE_RESET _u(0x0)

◆ DMA_CH3_CTRL_TRIG_INCR_WRITE_REV_ACCESS

#define DMA_CH3_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW"

◆ DMA_CH3_CTRL_TRIG_INCR_WRITE_REV_BITS

#define DMA_CH3_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080)

◆ DMA_CH3_CTRL_TRIG_INCR_WRITE_REV_LSB

#define DMA_CH3_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7)

◆ DMA_CH3_CTRL_TRIG_INCR_WRITE_REV_MSB

#define DMA_CH3_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7)

◆ DMA_CH3_CTRL_TRIG_INCR_WRITE_REV_RESET

#define DMA_CH3_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0)

◆ DMA_CH3_CTRL_TRIG_IRQ_QUIET_ACCESS

#define DMA_CH3_CTRL_TRIG_IRQ_QUIET_ACCESS "RW"

◆ DMA_CH3_CTRL_TRIG_IRQ_QUIET_BITS

#define DMA_CH3_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000)

◆ DMA_CH3_CTRL_TRIG_IRQ_QUIET_LSB

#define DMA_CH3_CTRL_TRIG_IRQ_QUIET_LSB _u(23)

◆ DMA_CH3_CTRL_TRIG_IRQ_QUIET_MSB

#define DMA_CH3_CTRL_TRIG_IRQ_QUIET_MSB _u(23)

◆ DMA_CH3_CTRL_TRIG_IRQ_QUIET_RESET

#define DMA_CH3_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0)

◆ DMA_CH3_CTRL_TRIG_OFFSET

#define DMA_CH3_CTRL_TRIG_OFFSET _u(0x000000cc)

◆ DMA_CH3_CTRL_TRIG_READ_ERROR_ACCESS

#define DMA_CH3_CTRL_TRIG_READ_ERROR_ACCESS "WC"

◆ DMA_CH3_CTRL_TRIG_READ_ERROR_BITS

#define DMA_CH3_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000)

◆ DMA_CH3_CTRL_TRIG_READ_ERROR_LSB

#define DMA_CH3_CTRL_TRIG_READ_ERROR_LSB _u(30)

◆ DMA_CH3_CTRL_TRIG_READ_ERROR_MSB

#define DMA_CH3_CTRL_TRIG_READ_ERROR_MSB _u(30)

◆ DMA_CH3_CTRL_TRIG_READ_ERROR_RESET

#define DMA_CH3_CTRL_TRIG_READ_ERROR_RESET _u(0x0)

◆ DMA_CH3_CTRL_TRIG_RESET

#define DMA_CH3_CTRL_TRIG_RESET _u(0x00000000)

◆ DMA_CH3_CTRL_TRIG_RING_SEL_ACCESS

#define DMA_CH3_CTRL_TRIG_RING_SEL_ACCESS "RW"

◆ DMA_CH3_CTRL_TRIG_RING_SEL_BITS

#define DMA_CH3_CTRL_TRIG_RING_SEL_BITS _u(0x00001000)

◆ DMA_CH3_CTRL_TRIG_RING_SEL_LSB

#define DMA_CH3_CTRL_TRIG_RING_SEL_LSB _u(12)

◆ DMA_CH3_CTRL_TRIG_RING_SEL_MSB

#define DMA_CH3_CTRL_TRIG_RING_SEL_MSB _u(12)

◆ DMA_CH3_CTRL_TRIG_RING_SEL_RESET

#define DMA_CH3_CTRL_TRIG_RING_SEL_RESET _u(0x0)

◆ DMA_CH3_CTRL_TRIG_RING_SIZE_ACCESS

#define DMA_CH3_CTRL_TRIG_RING_SIZE_ACCESS "RW"

◆ DMA_CH3_CTRL_TRIG_RING_SIZE_BITS

#define DMA_CH3_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00)

◆ DMA_CH3_CTRL_TRIG_RING_SIZE_LSB

#define DMA_CH3_CTRL_TRIG_RING_SIZE_LSB _u(8)

◆ DMA_CH3_CTRL_TRIG_RING_SIZE_MSB

#define DMA_CH3_CTRL_TRIG_RING_SIZE_MSB _u(11)

◆ DMA_CH3_CTRL_TRIG_RING_SIZE_RESET

#define DMA_CH3_CTRL_TRIG_RING_SIZE_RESET _u(0x0)

◆ DMA_CH3_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE

#define DMA_CH3_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0)

◆ DMA_CH3_CTRL_TRIG_SNIFF_EN_ACCESS

#define DMA_CH3_CTRL_TRIG_SNIFF_EN_ACCESS "RW"

◆ DMA_CH3_CTRL_TRIG_SNIFF_EN_BITS

#define DMA_CH3_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000)

◆ DMA_CH3_CTRL_TRIG_SNIFF_EN_LSB

#define DMA_CH3_CTRL_TRIG_SNIFF_EN_LSB _u(25)

◆ DMA_CH3_CTRL_TRIG_SNIFF_EN_MSB

#define DMA_CH3_CTRL_TRIG_SNIFF_EN_MSB _u(25)

◆ DMA_CH3_CTRL_TRIG_SNIFF_EN_RESET

#define DMA_CH3_CTRL_TRIG_SNIFF_EN_RESET _u(0x0)

◆ DMA_CH3_CTRL_TRIG_TREQ_SEL_ACCESS

#define DMA_CH3_CTRL_TRIG_TREQ_SEL_ACCESS "RW"

◆ DMA_CH3_CTRL_TRIG_TREQ_SEL_BITS

#define DMA_CH3_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000)

◆ DMA_CH3_CTRL_TRIG_TREQ_SEL_LSB

#define DMA_CH3_CTRL_TRIG_TREQ_SEL_LSB _u(17)

◆ DMA_CH3_CTRL_TRIG_TREQ_SEL_MSB

#define DMA_CH3_CTRL_TRIG_TREQ_SEL_MSB _u(22)

◆ DMA_CH3_CTRL_TRIG_TREQ_SEL_RESET

#define DMA_CH3_CTRL_TRIG_TREQ_SEL_RESET _u(0x00)

◆ DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT

#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f)

◆ DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0

#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b)

◆ DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1

#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c)

◆ DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2

#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d)

◆ DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3

#define DMA_CH3_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e)

◆ DMA_CH3_CTRL_TRIG_WRITE_ERROR_ACCESS

#define DMA_CH3_CTRL_TRIG_WRITE_ERROR_ACCESS "WC"

◆ DMA_CH3_CTRL_TRIG_WRITE_ERROR_BITS

#define DMA_CH3_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000)

◆ DMA_CH3_CTRL_TRIG_WRITE_ERROR_LSB

#define DMA_CH3_CTRL_TRIG_WRITE_ERROR_LSB _u(29)

◆ DMA_CH3_CTRL_TRIG_WRITE_ERROR_MSB

#define DMA_CH3_CTRL_TRIG_WRITE_ERROR_MSB _u(29)

◆ DMA_CH3_CTRL_TRIG_WRITE_ERROR_RESET

#define DMA_CH3_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0)

◆ DMA_CH3_DBG_CTDREQ_ACCESS

#define DMA_CH3_DBG_CTDREQ_ACCESS "WC"

◆ DMA_CH3_DBG_CTDREQ_BITS

#define DMA_CH3_DBG_CTDREQ_BITS _u(0x0000003f)

◆ DMA_CH3_DBG_CTDREQ_LSB

#define DMA_CH3_DBG_CTDREQ_LSB _u(0)

◆ DMA_CH3_DBG_CTDREQ_MSB

#define DMA_CH3_DBG_CTDREQ_MSB _u(5)

◆ DMA_CH3_DBG_CTDREQ_OFFSET

#define DMA_CH3_DBG_CTDREQ_OFFSET _u(0x000008c0)

◆ DMA_CH3_DBG_CTDREQ_RESET

#define DMA_CH3_DBG_CTDREQ_RESET _u(0x00000000)

◆ DMA_CH3_DBG_TCR_ACCESS

#define DMA_CH3_DBG_TCR_ACCESS "RO"

◆ DMA_CH3_DBG_TCR_BITS

#define DMA_CH3_DBG_TCR_BITS _u(0xffffffff)

◆ DMA_CH3_DBG_TCR_LSB

#define DMA_CH3_DBG_TCR_LSB _u(0)

◆ DMA_CH3_DBG_TCR_MSB

#define DMA_CH3_DBG_TCR_MSB _u(31)

◆ DMA_CH3_DBG_TCR_OFFSET

#define DMA_CH3_DBG_TCR_OFFSET _u(0x000008c4)

◆ DMA_CH3_DBG_TCR_RESET

#define DMA_CH3_DBG_TCR_RESET _u(0x00000000)

◆ DMA_CH3_READ_ADDR_ACCESS

#define DMA_CH3_READ_ADDR_ACCESS "RW"

◆ DMA_CH3_READ_ADDR_BITS

#define DMA_CH3_READ_ADDR_BITS _u(0xffffffff)

◆ DMA_CH3_READ_ADDR_LSB

#define DMA_CH3_READ_ADDR_LSB _u(0)

◆ DMA_CH3_READ_ADDR_MSB

#define DMA_CH3_READ_ADDR_MSB _u(31)

◆ DMA_CH3_READ_ADDR_OFFSET

#define DMA_CH3_READ_ADDR_OFFSET _u(0x000000c0)

◆ DMA_CH3_READ_ADDR_RESET

#define DMA_CH3_READ_ADDR_RESET _u(0x00000000)

◆ DMA_CH3_TRANS_COUNT_BITS

#define DMA_CH3_TRANS_COUNT_BITS _u(0xffffffff)

◆ DMA_CH3_TRANS_COUNT_COUNT_ACCESS

#define DMA_CH3_TRANS_COUNT_COUNT_ACCESS "RW"

◆ DMA_CH3_TRANS_COUNT_COUNT_BITS

#define DMA_CH3_TRANS_COUNT_COUNT_BITS _u(0x0fffffff)

◆ DMA_CH3_TRANS_COUNT_COUNT_LSB

#define DMA_CH3_TRANS_COUNT_COUNT_LSB _u(0)

◆ DMA_CH3_TRANS_COUNT_COUNT_MSB

#define DMA_CH3_TRANS_COUNT_COUNT_MSB _u(27)

◆ DMA_CH3_TRANS_COUNT_COUNT_RESET

#define DMA_CH3_TRANS_COUNT_COUNT_RESET _u(0x0000000)

◆ DMA_CH3_TRANS_COUNT_MODE_ACCESS

#define DMA_CH3_TRANS_COUNT_MODE_ACCESS "RW"

◆ DMA_CH3_TRANS_COUNT_MODE_BITS

#define DMA_CH3_TRANS_COUNT_MODE_BITS _u(0xf0000000)

◆ DMA_CH3_TRANS_COUNT_MODE_LSB

#define DMA_CH3_TRANS_COUNT_MODE_LSB _u(28)

◆ DMA_CH3_TRANS_COUNT_MODE_MSB

#define DMA_CH3_TRANS_COUNT_MODE_MSB _u(31)

◆ DMA_CH3_TRANS_COUNT_MODE_RESET

#define DMA_CH3_TRANS_COUNT_MODE_RESET _u(0x0)

◆ DMA_CH3_TRANS_COUNT_MODE_VALUE_ENDLESS

#define DMA_CH3_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf)

◆ DMA_CH3_TRANS_COUNT_MODE_VALUE_NORMAL

#define DMA_CH3_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0)

◆ DMA_CH3_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF

#define DMA_CH3_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1)

◆ DMA_CH3_TRANS_COUNT_OFFSET

#define DMA_CH3_TRANS_COUNT_OFFSET _u(0x000000c8)

◆ DMA_CH3_TRANS_COUNT_RESET

#define DMA_CH3_TRANS_COUNT_RESET _u(0x00000000)

◆ DMA_CH3_WRITE_ADDR_ACCESS

#define DMA_CH3_WRITE_ADDR_ACCESS "RW"

◆ DMA_CH3_WRITE_ADDR_BITS

#define DMA_CH3_WRITE_ADDR_BITS _u(0xffffffff)

◆ DMA_CH3_WRITE_ADDR_LSB

#define DMA_CH3_WRITE_ADDR_LSB _u(0)

◆ DMA_CH3_WRITE_ADDR_MSB

#define DMA_CH3_WRITE_ADDR_MSB _u(31)

◆ DMA_CH3_WRITE_ADDR_OFFSET

#define DMA_CH3_WRITE_ADDR_OFFSET _u(0x000000c4)

◆ DMA_CH3_WRITE_ADDR_RESET

#define DMA_CH3_WRITE_ADDR_RESET _u(0x00000000)

◆ DMA_CH4_AL1_CTRL_ACCESS

#define DMA_CH4_AL1_CTRL_ACCESS "RW"

◆ DMA_CH4_AL1_CTRL_BITS

#define DMA_CH4_AL1_CTRL_BITS _u(0xffffffff)

◆ DMA_CH4_AL1_CTRL_LSB

#define DMA_CH4_AL1_CTRL_LSB _u(0)

◆ DMA_CH4_AL1_CTRL_MSB

#define DMA_CH4_AL1_CTRL_MSB _u(31)

◆ DMA_CH4_AL1_CTRL_OFFSET

#define DMA_CH4_AL1_CTRL_OFFSET _u(0x00000110)

◆ DMA_CH4_AL1_CTRL_RESET

#define DMA_CH4_AL1_CTRL_RESET "-"

◆ DMA_CH4_AL1_READ_ADDR_ACCESS

#define DMA_CH4_AL1_READ_ADDR_ACCESS "RW"

◆ DMA_CH4_AL1_READ_ADDR_BITS

#define DMA_CH4_AL1_READ_ADDR_BITS _u(0xffffffff)

◆ DMA_CH4_AL1_READ_ADDR_LSB

#define DMA_CH4_AL1_READ_ADDR_LSB _u(0)

◆ DMA_CH4_AL1_READ_ADDR_MSB

#define DMA_CH4_AL1_READ_ADDR_MSB _u(31)

◆ DMA_CH4_AL1_READ_ADDR_OFFSET

#define DMA_CH4_AL1_READ_ADDR_OFFSET _u(0x00000114)

◆ DMA_CH4_AL1_READ_ADDR_RESET

#define DMA_CH4_AL1_READ_ADDR_RESET "-"

◆ DMA_CH4_AL1_TRANS_COUNT_TRIG_ACCESS

#define DMA_CH4_AL1_TRANS_COUNT_TRIG_ACCESS "RW"

◆ DMA_CH4_AL1_TRANS_COUNT_TRIG_BITS

#define DMA_CH4_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff)

◆ DMA_CH4_AL1_TRANS_COUNT_TRIG_LSB

#define DMA_CH4_AL1_TRANS_COUNT_TRIG_LSB _u(0)

◆ DMA_CH4_AL1_TRANS_COUNT_TRIG_MSB

#define DMA_CH4_AL1_TRANS_COUNT_TRIG_MSB _u(31)

◆ DMA_CH4_AL1_TRANS_COUNT_TRIG_OFFSET

#define DMA_CH4_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000011c)

◆ DMA_CH4_AL1_TRANS_COUNT_TRIG_RESET

#define DMA_CH4_AL1_TRANS_COUNT_TRIG_RESET "-"

◆ DMA_CH4_AL1_WRITE_ADDR_ACCESS

#define DMA_CH4_AL1_WRITE_ADDR_ACCESS "RW"

◆ DMA_CH4_AL1_WRITE_ADDR_BITS

#define DMA_CH4_AL1_WRITE_ADDR_BITS _u(0xffffffff)

◆ DMA_CH4_AL1_WRITE_ADDR_LSB

#define DMA_CH4_AL1_WRITE_ADDR_LSB _u(0)

◆ DMA_CH4_AL1_WRITE_ADDR_MSB

#define DMA_CH4_AL1_WRITE_ADDR_MSB _u(31)

◆ DMA_CH4_AL1_WRITE_ADDR_OFFSET

#define DMA_CH4_AL1_WRITE_ADDR_OFFSET _u(0x00000118)

◆ DMA_CH4_AL1_WRITE_ADDR_RESET

#define DMA_CH4_AL1_WRITE_ADDR_RESET "-"

◆ DMA_CH4_AL2_CTRL_ACCESS

#define DMA_CH4_AL2_CTRL_ACCESS "RW"

◆ DMA_CH4_AL2_CTRL_BITS

#define DMA_CH4_AL2_CTRL_BITS _u(0xffffffff)

◆ DMA_CH4_AL2_CTRL_LSB

#define DMA_CH4_AL2_CTRL_LSB _u(0)

◆ DMA_CH4_AL2_CTRL_MSB

#define DMA_CH4_AL2_CTRL_MSB _u(31)

◆ DMA_CH4_AL2_CTRL_OFFSET

#define DMA_CH4_AL2_CTRL_OFFSET _u(0x00000120)

◆ DMA_CH4_AL2_CTRL_RESET

#define DMA_CH4_AL2_CTRL_RESET "-"

◆ DMA_CH4_AL2_READ_ADDR_ACCESS

#define DMA_CH4_AL2_READ_ADDR_ACCESS "RW"

◆ DMA_CH4_AL2_READ_ADDR_BITS

#define DMA_CH4_AL2_READ_ADDR_BITS _u(0xffffffff)

◆ DMA_CH4_AL2_READ_ADDR_LSB

#define DMA_CH4_AL2_READ_ADDR_LSB _u(0)

◆ DMA_CH4_AL2_READ_ADDR_MSB

#define DMA_CH4_AL2_READ_ADDR_MSB _u(31)

◆ DMA_CH4_AL2_READ_ADDR_OFFSET

#define DMA_CH4_AL2_READ_ADDR_OFFSET _u(0x00000128)

◆ DMA_CH4_AL2_READ_ADDR_RESET

#define DMA_CH4_AL2_READ_ADDR_RESET "-"

◆ DMA_CH4_AL2_TRANS_COUNT_ACCESS

#define DMA_CH4_AL2_TRANS_COUNT_ACCESS "RW"

◆ DMA_CH4_AL2_TRANS_COUNT_BITS

#define DMA_CH4_AL2_TRANS_COUNT_BITS _u(0xffffffff)

◆ DMA_CH4_AL2_TRANS_COUNT_LSB

#define DMA_CH4_AL2_TRANS_COUNT_LSB _u(0)

◆ DMA_CH4_AL2_TRANS_COUNT_MSB

#define DMA_CH4_AL2_TRANS_COUNT_MSB _u(31)

◆ DMA_CH4_AL2_TRANS_COUNT_OFFSET

#define DMA_CH4_AL2_TRANS_COUNT_OFFSET _u(0x00000124)

◆ DMA_CH4_AL2_TRANS_COUNT_RESET

#define DMA_CH4_AL2_TRANS_COUNT_RESET "-"

◆ DMA_CH4_AL2_WRITE_ADDR_TRIG_ACCESS

#define DMA_CH4_AL2_WRITE_ADDR_TRIG_ACCESS "RW"

◆ DMA_CH4_AL2_WRITE_ADDR_TRIG_BITS

#define DMA_CH4_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff)

◆ DMA_CH4_AL2_WRITE_ADDR_TRIG_LSB

#define DMA_CH4_AL2_WRITE_ADDR_TRIG_LSB _u(0)

◆ DMA_CH4_AL2_WRITE_ADDR_TRIG_MSB

#define DMA_CH4_AL2_WRITE_ADDR_TRIG_MSB _u(31)

◆ DMA_CH4_AL2_WRITE_ADDR_TRIG_OFFSET

#define DMA_CH4_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x0000012c)

◆ DMA_CH4_AL2_WRITE_ADDR_TRIG_RESET

#define DMA_CH4_AL2_WRITE_ADDR_TRIG_RESET "-"

◆ DMA_CH4_AL3_CTRL_ACCESS

#define DMA_CH4_AL3_CTRL_ACCESS "RW"

◆ DMA_CH4_AL3_CTRL_BITS

#define DMA_CH4_AL3_CTRL_BITS _u(0xffffffff)

◆ DMA_CH4_AL3_CTRL_LSB

#define DMA_CH4_AL3_CTRL_LSB _u(0)

◆ DMA_CH4_AL3_CTRL_MSB

#define DMA_CH4_AL3_CTRL_MSB _u(31)

◆ DMA_CH4_AL3_CTRL_OFFSET

#define DMA_CH4_AL3_CTRL_OFFSET _u(0x00000130)

◆ DMA_CH4_AL3_CTRL_RESET

#define DMA_CH4_AL3_CTRL_RESET "-"

◆ DMA_CH4_AL3_READ_ADDR_TRIG_ACCESS

#define DMA_CH4_AL3_READ_ADDR_TRIG_ACCESS "RW"

◆ DMA_CH4_AL3_READ_ADDR_TRIG_BITS

#define DMA_CH4_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff)

◆ DMA_CH4_AL3_READ_ADDR_TRIG_LSB

#define DMA_CH4_AL3_READ_ADDR_TRIG_LSB _u(0)

◆ DMA_CH4_AL3_READ_ADDR_TRIG_MSB

#define DMA_CH4_AL3_READ_ADDR_TRIG_MSB _u(31)

◆ DMA_CH4_AL3_READ_ADDR_TRIG_OFFSET

#define DMA_CH4_AL3_READ_ADDR_TRIG_OFFSET _u(0x0000013c)

◆ DMA_CH4_AL3_READ_ADDR_TRIG_RESET

#define DMA_CH4_AL3_READ_ADDR_TRIG_RESET "-"

◆ DMA_CH4_AL3_TRANS_COUNT_ACCESS

#define DMA_CH4_AL3_TRANS_COUNT_ACCESS "RW"

◆ DMA_CH4_AL3_TRANS_COUNT_BITS

#define DMA_CH4_AL3_TRANS_COUNT_BITS _u(0xffffffff)

◆ DMA_CH4_AL3_TRANS_COUNT_LSB

#define DMA_CH4_AL3_TRANS_COUNT_LSB _u(0)

◆ DMA_CH4_AL3_TRANS_COUNT_MSB

#define DMA_CH4_AL3_TRANS_COUNT_MSB _u(31)

◆ DMA_CH4_AL3_TRANS_COUNT_OFFSET

#define DMA_CH4_AL3_TRANS_COUNT_OFFSET _u(0x00000138)

◆ DMA_CH4_AL3_TRANS_COUNT_RESET

#define DMA_CH4_AL3_TRANS_COUNT_RESET "-"

◆ DMA_CH4_AL3_WRITE_ADDR_ACCESS

#define DMA_CH4_AL3_WRITE_ADDR_ACCESS "RW"

◆ DMA_CH4_AL3_WRITE_ADDR_BITS

#define DMA_CH4_AL3_WRITE_ADDR_BITS _u(0xffffffff)

◆ DMA_CH4_AL3_WRITE_ADDR_LSB

#define DMA_CH4_AL3_WRITE_ADDR_LSB _u(0)

◆ DMA_CH4_AL3_WRITE_ADDR_MSB

#define DMA_CH4_AL3_WRITE_ADDR_MSB _u(31)

◆ DMA_CH4_AL3_WRITE_ADDR_OFFSET

#define DMA_CH4_AL3_WRITE_ADDR_OFFSET _u(0x00000134)

◆ DMA_CH4_AL3_WRITE_ADDR_RESET

#define DMA_CH4_AL3_WRITE_ADDR_RESET "-"

◆ DMA_CH4_CTRL_TRIG_AHB_ERROR_ACCESS

#define DMA_CH4_CTRL_TRIG_AHB_ERROR_ACCESS "RO"

◆ DMA_CH4_CTRL_TRIG_AHB_ERROR_BITS

#define DMA_CH4_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000)

◆ DMA_CH4_CTRL_TRIG_AHB_ERROR_LSB

#define DMA_CH4_CTRL_TRIG_AHB_ERROR_LSB _u(31)

◆ DMA_CH4_CTRL_TRIG_AHB_ERROR_MSB

#define DMA_CH4_CTRL_TRIG_AHB_ERROR_MSB _u(31)

◆ DMA_CH4_CTRL_TRIG_AHB_ERROR_RESET

#define DMA_CH4_CTRL_TRIG_AHB_ERROR_RESET _u(0x0)

◆ DMA_CH4_CTRL_TRIG_BITS

#define DMA_CH4_CTRL_TRIG_BITS _u(0xe7ffffff)

◆ DMA_CH4_CTRL_TRIG_BSWAP_ACCESS

#define DMA_CH4_CTRL_TRIG_BSWAP_ACCESS "RW"

◆ DMA_CH4_CTRL_TRIG_BSWAP_BITS

#define DMA_CH4_CTRL_TRIG_BSWAP_BITS _u(0x01000000)

◆ DMA_CH4_CTRL_TRIG_BSWAP_LSB

#define DMA_CH4_CTRL_TRIG_BSWAP_LSB _u(24)

◆ DMA_CH4_CTRL_TRIG_BSWAP_MSB

#define DMA_CH4_CTRL_TRIG_BSWAP_MSB _u(24)

◆ DMA_CH4_CTRL_TRIG_BSWAP_RESET

#define DMA_CH4_CTRL_TRIG_BSWAP_RESET _u(0x0)

◆ DMA_CH4_CTRL_TRIG_BUSY_ACCESS

#define DMA_CH4_CTRL_TRIG_BUSY_ACCESS "RO"

◆ DMA_CH4_CTRL_TRIG_BUSY_BITS

#define DMA_CH4_CTRL_TRIG_BUSY_BITS _u(0x04000000)

◆ DMA_CH4_CTRL_TRIG_BUSY_LSB

#define DMA_CH4_CTRL_TRIG_BUSY_LSB _u(26)

◆ DMA_CH4_CTRL_TRIG_BUSY_MSB

#define DMA_CH4_CTRL_TRIG_BUSY_MSB _u(26)

◆ DMA_CH4_CTRL_TRIG_BUSY_RESET

#define DMA_CH4_CTRL_TRIG_BUSY_RESET _u(0x0)

◆ DMA_CH4_CTRL_TRIG_CHAIN_TO_ACCESS

#define DMA_CH4_CTRL_TRIG_CHAIN_TO_ACCESS "RW"

◆ DMA_CH4_CTRL_TRIG_CHAIN_TO_BITS

#define DMA_CH4_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000)

◆ DMA_CH4_CTRL_TRIG_CHAIN_TO_LSB

#define DMA_CH4_CTRL_TRIG_CHAIN_TO_LSB _u(13)

◆ DMA_CH4_CTRL_TRIG_CHAIN_TO_MSB

#define DMA_CH4_CTRL_TRIG_CHAIN_TO_MSB _u(16)

◆ DMA_CH4_CTRL_TRIG_CHAIN_TO_RESET

#define DMA_CH4_CTRL_TRIG_CHAIN_TO_RESET _u(0x0)

◆ DMA_CH4_CTRL_TRIG_DATA_SIZE_ACCESS

#define DMA_CH4_CTRL_TRIG_DATA_SIZE_ACCESS "RW"

◆ DMA_CH4_CTRL_TRIG_DATA_SIZE_BITS

#define DMA_CH4_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c)

◆ DMA_CH4_CTRL_TRIG_DATA_SIZE_LSB

#define DMA_CH4_CTRL_TRIG_DATA_SIZE_LSB _u(2)

◆ DMA_CH4_CTRL_TRIG_DATA_SIZE_MSB

#define DMA_CH4_CTRL_TRIG_DATA_SIZE_MSB _u(3)

◆ DMA_CH4_CTRL_TRIG_DATA_SIZE_RESET

#define DMA_CH4_CTRL_TRIG_DATA_SIZE_RESET _u(0x0)

◆ DMA_CH4_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE

#define DMA_CH4_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0)

◆ DMA_CH4_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD

#define DMA_CH4_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1)

◆ DMA_CH4_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD

#define DMA_CH4_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2)

◆ DMA_CH4_CTRL_TRIG_EN_ACCESS

#define DMA_CH4_CTRL_TRIG_EN_ACCESS "RW"

◆ DMA_CH4_CTRL_TRIG_EN_BITS

#define DMA_CH4_CTRL_TRIG_EN_BITS _u(0x00000001)

◆ DMA_CH4_CTRL_TRIG_EN_LSB

#define DMA_CH4_CTRL_TRIG_EN_LSB _u(0)

◆ DMA_CH4_CTRL_TRIG_EN_MSB

#define DMA_CH4_CTRL_TRIG_EN_MSB _u(0)

◆ DMA_CH4_CTRL_TRIG_EN_RESET

#define DMA_CH4_CTRL_TRIG_EN_RESET _u(0x0)

◆ DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_ACCESS

#define DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW"

◆ DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_BITS

#define DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002)

◆ DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_LSB

#define DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1)

◆ DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_MSB

#define DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1)

◆ DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_RESET

#define DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0)

◆ DMA_CH4_CTRL_TRIG_INCR_READ_ACCESS

#define DMA_CH4_CTRL_TRIG_INCR_READ_ACCESS "RW"

◆ DMA_CH4_CTRL_TRIG_INCR_READ_BITS

#define DMA_CH4_CTRL_TRIG_INCR_READ_BITS _u(0x00000010)

◆ DMA_CH4_CTRL_TRIG_INCR_READ_LSB

#define DMA_CH4_CTRL_TRIG_INCR_READ_LSB _u(4)

◆ DMA_CH4_CTRL_TRIG_INCR_READ_MSB

#define DMA_CH4_CTRL_TRIG_INCR_READ_MSB _u(4)

◆ DMA_CH4_CTRL_TRIG_INCR_READ_RESET

#define DMA_CH4_CTRL_TRIG_INCR_READ_RESET _u(0x0)

◆ DMA_CH4_CTRL_TRIG_INCR_READ_REV_ACCESS

#define DMA_CH4_CTRL_TRIG_INCR_READ_REV_ACCESS "RW"

◆ DMA_CH4_CTRL_TRIG_INCR_READ_REV_BITS

#define DMA_CH4_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020)

◆ DMA_CH4_CTRL_TRIG_INCR_READ_REV_LSB

#define DMA_CH4_CTRL_TRIG_INCR_READ_REV_LSB _u(5)

◆ DMA_CH4_CTRL_TRIG_INCR_READ_REV_MSB

#define DMA_CH4_CTRL_TRIG_INCR_READ_REV_MSB _u(5)

◆ DMA_CH4_CTRL_TRIG_INCR_READ_REV_RESET

#define DMA_CH4_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0)

◆ DMA_CH4_CTRL_TRIG_INCR_WRITE_ACCESS

#define DMA_CH4_CTRL_TRIG_INCR_WRITE_ACCESS "RW"

◆ DMA_CH4_CTRL_TRIG_INCR_WRITE_BITS

#define DMA_CH4_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040)

◆ DMA_CH4_CTRL_TRIG_INCR_WRITE_LSB

#define DMA_CH4_CTRL_TRIG_INCR_WRITE_LSB _u(6)

◆ DMA_CH4_CTRL_TRIG_INCR_WRITE_MSB

#define DMA_CH4_CTRL_TRIG_INCR_WRITE_MSB _u(6)

◆ DMA_CH4_CTRL_TRIG_INCR_WRITE_RESET

#define DMA_CH4_CTRL_TRIG_INCR_WRITE_RESET _u(0x0)

◆ DMA_CH4_CTRL_TRIG_INCR_WRITE_REV_ACCESS

#define DMA_CH4_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW"

◆ DMA_CH4_CTRL_TRIG_INCR_WRITE_REV_BITS

#define DMA_CH4_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080)

◆ DMA_CH4_CTRL_TRIG_INCR_WRITE_REV_LSB

#define DMA_CH4_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7)

◆ DMA_CH4_CTRL_TRIG_INCR_WRITE_REV_MSB

#define DMA_CH4_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7)

◆ DMA_CH4_CTRL_TRIG_INCR_WRITE_REV_RESET

#define DMA_CH4_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0)

◆ DMA_CH4_CTRL_TRIG_IRQ_QUIET_ACCESS

#define DMA_CH4_CTRL_TRIG_IRQ_QUIET_ACCESS "RW"

◆ DMA_CH4_CTRL_TRIG_IRQ_QUIET_BITS

#define DMA_CH4_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000)

◆ DMA_CH4_CTRL_TRIG_IRQ_QUIET_LSB

#define DMA_CH4_CTRL_TRIG_IRQ_QUIET_LSB _u(23)

◆ DMA_CH4_CTRL_TRIG_IRQ_QUIET_MSB

#define DMA_CH4_CTRL_TRIG_IRQ_QUIET_MSB _u(23)

◆ DMA_CH4_CTRL_TRIG_IRQ_QUIET_RESET

#define DMA_CH4_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0)

◆ DMA_CH4_CTRL_TRIG_OFFSET

#define DMA_CH4_CTRL_TRIG_OFFSET _u(0x0000010c)

◆ DMA_CH4_CTRL_TRIG_READ_ERROR_ACCESS

#define DMA_CH4_CTRL_TRIG_READ_ERROR_ACCESS "WC"

◆ DMA_CH4_CTRL_TRIG_READ_ERROR_BITS

#define DMA_CH4_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000)

◆ DMA_CH4_CTRL_TRIG_READ_ERROR_LSB

#define DMA_CH4_CTRL_TRIG_READ_ERROR_LSB _u(30)

◆ DMA_CH4_CTRL_TRIG_READ_ERROR_MSB

#define DMA_CH4_CTRL_TRIG_READ_ERROR_MSB _u(30)

◆ DMA_CH4_CTRL_TRIG_READ_ERROR_RESET

#define DMA_CH4_CTRL_TRIG_READ_ERROR_RESET _u(0x0)

◆ DMA_CH4_CTRL_TRIG_RESET

#define DMA_CH4_CTRL_TRIG_RESET _u(0x00000000)

◆ DMA_CH4_CTRL_TRIG_RING_SEL_ACCESS

#define DMA_CH4_CTRL_TRIG_RING_SEL_ACCESS "RW"

◆ DMA_CH4_CTRL_TRIG_RING_SEL_BITS

#define DMA_CH4_CTRL_TRIG_RING_SEL_BITS _u(0x00001000)

◆ DMA_CH4_CTRL_TRIG_RING_SEL_LSB

#define DMA_CH4_CTRL_TRIG_RING_SEL_LSB _u(12)

◆ DMA_CH4_CTRL_TRIG_RING_SEL_MSB

#define DMA_CH4_CTRL_TRIG_RING_SEL_MSB _u(12)

◆ DMA_CH4_CTRL_TRIG_RING_SEL_RESET

#define DMA_CH4_CTRL_TRIG_RING_SEL_RESET _u(0x0)

◆ DMA_CH4_CTRL_TRIG_RING_SIZE_ACCESS

#define DMA_CH4_CTRL_TRIG_RING_SIZE_ACCESS "RW"

◆ DMA_CH4_CTRL_TRIG_RING_SIZE_BITS

#define DMA_CH4_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00)

◆ DMA_CH4_CTRL_TRIG_RING_SIZE_LSB

#define DMA_CH4_CTRL_TRIG_RING_SIZE_LSB _u(8)

◆ DMA_CH4_CTRL_TRIG_RING_SIZE_MSB

#define DMA_CH4_CTRL_TRIG_RING_SIZE_MSB _u(11)

◆ DMA_CH4_CTRL_TRIG_RING_SIZE_RESET

#define DMA_CH4_CTRL_TRIG_RING_SIZE_RESET _u(0x0)

◆ DMA_CH4_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE

#define DMA_CH4_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0)

◆ DMA_CH4_CTRL_TRIG_SNIFF_EN_ACCESS

#define DMA_CH4_CTRL_TRIG_SNIFF_EN_ACCESS "RW"

◆ DMA_CH4_CTRL_TRIG_SNIFF_EN_BITS

#define DMA_CH4_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000)

◆ DMA_CH4_CTRL_TRIG_SNIFF_EN_LSB

#define DMA_CH4_CTRL_TRIG_SNIFF_EN_LSB _u(25)

◆ DMA_CH4_CTRL_TRIG_SNIFF_EN_MSB

#define DMA_CH4_CTRL_TRIG_SNIFF_EN_MSB _u(25)

◆ DMA_CH4_CTRL_TRIG_SNIFF_EN_RESET

#define DMA_CH4_CTRL_TRIG_SNIFF_EN_RESET _u(0x0)

◆ DMA_CH4_CTRL_TRIG_TREQ_SEL_ACCESS

#define DMA_CH4_CTRL_TRIG_TREQ_SEL_ACCESS "RW"

◆ DMA_CH4_CTRL_TRIG_TREQ_SEL_BITS

#define DMA_CH4_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000)

◆ DMA_CH4_CTRL_TRIG_TREQ_SEL_LSB

#define DMA_CH4_CTRL_TRIG_TREQ_SEL_LSB _u(17)

◆ DMA_CH4_CTRL_TRIG_TREQ_SEL_MSB

#define DMA_CH4_CTRL_TRIG_TREQ_SEL_MSB _u(22)

◆ DMA_CH4_CTRL_TRIG_TREQ_SEL_RESET

#define DMA_CH4_CTRL_TRIG_TREQ_SEL_RESET _u(0x00)

◆ DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT

#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f)

◆ DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0

#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b)

◆ DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1

#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c)

◆ DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2

#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d)

◆ DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3

#define DMA_CH4_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e)

◆ DMA_CH4_CTRL_TRIG_WRITE_ERROR_ACCESS

#define DMA_CH4_CTRL_TRIG_WRITE_ERROR_ACCESS "WC"

◆ DMA_CH4_CTRL_TRIG_WRITE_ERROR_BITS

#define DMA_CH4_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000)

◆ DMA_CH4_CTRL_TRIG_WRITE_ERROR_LSB

#define DMA_CH4_CTRL_TRIG_WRITE_ERROR_LSB _u(29)

◆ DMA_CH4_CTRL_TRIG_WRITE_ERROR_MSB

#define DMA_CH4_CTRL_TRIG_WRITE_ERROR_MSB _u(29)

◆ DMA_CH4_CTRL_TRIG_WRITE_ERROR_RESET

#define DMA_CH4_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0)

◆ DMA_CH4_DBG_CTDREQ_ACCESS

#define DMA_CH4_DBG_CTDREQ_ACCESS "WC"

◆ DMA_CH4_DBG_CTDREQ_BITS

#define DMA_CH4_DBG_CTDREQ_BITS _u(0x0000003f)

◆ DMA_CH4_DBG_CTDREQ_LSB

#define DMA_CH4_DBG_CTDREQ_LSB _u(0)

◆ DMA_CH4_DBG_CTDREQ_MSB

#define DMA_CH4_DBG_CTDREQ_MSB _u(5)

◆ DMA_CH4_DBG_CTDREQ_OFFSET

#define DMA_CH4_DBG_CTDREQ_OFFSET _u(0x00000900)

◆ DMA_CH4_DBG_CTDREQ_RESET

#define DMA_CH4_DBG_CTDREQ_RESET _u(0x00000000)

◆ DMA_CH4_DBG_TCR_ACCESS

#define DMA_CH4_DBG_TCR_ACCESS "RO"

◆ DMA_CH4_DBG_TCR_BITS

#define DMA_CH4_DBG_TCR_BITS _u(0xffffffff)

◆ DMA_CH4_DBG_TCR_LSB

#define DMA_CH4_DBG_TCR_LSB _u(0)

◆ DMA_CH4_DBG_TCR_MSB

#define DMA_CH4_DBG_TCR_MSB _u(31)

◆ DMA_CH4_DBG_TCR_OFFSET

#define DMA_CH4_DBG_TCR_OFFSET _u(0x00000904)

◆ DMA_CH4_DBG_TCR_RESET

#define DMA_CH4_DBG_TCR_RESET _u(0x00000000)

◆ DMA_CH4_READ_ADDR_ACCESS

#define DMA_CH4_READ_ADDR_ACCESS "RW"

◆ DMA_CH4_READ_ADDR_BITS

#define DMA_CH4_READ_ADDR_BITS _u(0xffffffff)

◆ DMA_CH4_READ_ADDR_LSB

#define DMA_CH4_READ_ADDR_LSB _u(0)

◆ DMA_CH4_READ_ADDR_MSB

#define DMA_CH4_READ_ADDR_MSB _u(31)

◆ DMA_CH4_READ_ADDR_OFFSET

#define DMA_CH4_READ_ADDR_OFFSET _u(0x00000100)

◆ DMA_CH4_READ_ADDR_RESET

#define DMA_CH4_READ_ADDR_RESET _u(0x00000000)

◆ DMA_CH4_TRANS_COUNT_BITS

#define DMA_CH4_TRANS_COUNT_BITS _u(0xffffffff)

◆ DMA_CH4_TRANS_COUNT_COUNT_ACCESS

#define DMA_CH4_TRANS_COUNT_COUNT_ACCESS "RW"

◆ DMA_CH4_TRANS_COUNT_COUNT_BITS

#define DMA_CH4_TRANS_COUNT_COUNT_BITS _u(0x0fffffff)

◆ DMA_CH4_TRANS_COUNT_COUNT_LSB

#define DMA_CH4_TRANS_COUNT_COUNT_LSB _u(0)

◆ DMA_CH4_TRANS_COUNT_COUNT_MSB

#define DMA_CH4_TRANS_COUNT_COUNT_MSB _u(27)

◆ DMA_CH4_TRANS_COUNT_COUNT_RESET

#define DMA_CH4_TRANS_COUNT_COUNT_RESET _u(0x0000000)

◆ DMA_CH4_TRANS_COUNT_MODE_ACCESS

#define DMA_CH4_TRANS_COUNT_MODE_ACCESS "RW"

◆ DMA_CH4_TRANS_COUNT_MODE_BITS

#define DMA_CH4_TRANS_COUNT_MODE_BITS _u(0xf0000000)

◆ DMA_CH4_TRANS_COUNT_MODE_LSB

#define DMA_CH4_TRANS_COUNT_MODE_LSB _u(28)

◆ DMA_CH4_TRANS_COUNT_MODE_MSB

#define DMA_CH4_TRANS_COUNT_MODE_MSB _u(31)

◆ DMA_CH4_TRANS_COUNT_MODE_RESET

#define DMA_CH4_TRANS_COUNT_MODE_RESET _u(0x0)

◆ DMA_CH4_TRANS_COUNT_MODE_VALUE_ENDLESS

#define DMA_CH4_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf)

◆ DMA_CH4_TRANS_COUNT_MODE_VALUE_NORMAL

#define DMA_CH4_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0)

◆ DMA_CH4_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF

#define DMA_CH4_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1)

◆ DMA_CH4_TRANS_COUNT_OFFSET

#define DMA_CH4_TRANS_COUNT_OFFSET _u(0x00000108)

◆ DMA_CH4_TRANS_COUNT_RESET

#define DMA_CH4_TRANS_COUNT_RESET _u(0x00000000)

◆ DMA_CH4_WRITE_ADDR_ACCESS

#define DMA_CH4_WRITE_ADDR_ACCESS "RW"

◆ DMA_CH4_WRITE_ADDR_BITS

#define DMA_CH4_WRITE_ADDR_BITS _u(0xffffffff)

◆ DMA_CH4_WRITE_ADDR_LSB

#define DMA_CH4_WRITE_ADDR_LSB _u(0)

◆ DMA_CH4_WRITE_ADDR_MSB

#define DMA_CH4_WRITE_ADDR_MSB _u(31)

◆ DMA_CH4_WRITE_ADDR_OFFSET

#define DMA_CH4_WRITE_ADDR_OFFSET _u(0x00000104)

◆ DMA_CH4_WRITE_ADDR_RESET

#define DMA_CH4_WRITE_ADDR_RESET _u(0x00000000)

◆ DMA_CH5_AL1_CTRL_ACCESS

#define DMA_CH5_AL1_CTRL_ACCESS "RW"

◆ DMA_CH5_AL1_CTRL_BITS

#define DMA_CH5_AL1_CTRL_BITS _u(0xffffffff)

◆ DMA_CH5_AL1_CTRL_LSB

#define DMA_CH5_AL1_CTRL_LSB _u(0)

◆ DMA_CH5_AL1_CTRL_MSB

#define DMA_CH5_AL1_CTRL_MSB _u(31)

◆ DMA_CH5_AL1_CTRL_OFFSET

#define DMA_CH5_AL1_CTRL_OFFSET _u(0x00000150)

◆ DMA_CH5_AL1_CTRL_RESET

#define DMA_CH5_AL1_CTRL_RESET "-"

◆ DMA_CH5_AL1_READ_ADDR_ACCESS

#define DMA_CH5_AL1_READ_ADDR_ACCESS "RW"

◆ DMA_CH5_AL1_READ_ADDR_BITS

#define DMA_CH5_AL1_READ_ADDR_BITS _u(0xffffffff)

◆ DMA_CH5_AL1_READ_ADDR_LSB

#define DMA_CH5_AL1_READ_ADDR_LSB _u(0)

◆ DMA_CH5_AL1_READ_ADDR_MSB

#define DMA_CH5_AL1_READ_ADDR_MSB _u(31)

◆ DMA_CH5_AL1_READ_ADDR_OFFSET

#define DMA_CH5_AL1_READ_ADDR_OFFSET _u(0x00000154)

◆ DMA_CH5_AL1_READ_ADDR_RESET

#define DMA_CH5_AL1_READ_ADDR_RESET "-"

◆ DMA_CH5_AL1_TRANS_COUNT_TRIG_ACCESS

#define DMA_CH5_AL1_TRANS_COUNT_TRIG_ACCESS "RW"

◆ DMA_CH5_AL1_TRANS_COUNT_TRIG_BITS

#define DMA_CH5_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff)

◆ DMA_CH5_AL1_TRANS_COUNT_TRIG_LSB

#define DMA_CH5_AL1_TRANS_COUNT_TRIG_LSB _u(0)

◆ DMA_CH5_AL1_TRANS_COUNT_TRIG_MSB

#define DMA_CH5_AL1_TRANS_COUNT_TRIG_MSB _u(31)

◆ DMA_CH5_AL1_TRANS_COUNT_TRIG_OFFSET

#define DMA_CH5_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000015c)

◆ DMA_CH5_AL1_TRANS_COUNT_TRIG_RESET

#define DMA_CH5_AL1_TRANS_COUNT_TRIG_RESET "-"

◆ DMA_CH5_AL1_WRITE_ADDR_ACCESS

#define DMA_CH5_AL1_WRITE_ADDR_ACCESS "RW"

◆ DMA_CH5_AL1_WRITE_ADDR_BITS

#define DMA_CH5_AL1_WRITE_ADDR_BITS _u(0xffffffff)

◆ DMA_CH5_AL1_WRITE_ADDR_LSB

#define DMA_CH5_AL1_WRITE_ADDR_LSB _u(0)

◆ DMA_CH5_AL1_WRITE_ADDR_MSB

#define DMA_CH5_AL1_WRITE_ADDR_MSB _u(31)

◆ DMA_CH5_AL1_WRITE_ADDR_OFFSET

#define DMA_CH5_AL1_WRITE_ADDR_OFFSET _u(0x00000158)

◆ DMA_CH5_AL1_WRITE_ADDR_RESET

#define DMA_CH5_AL1_WRITE_ADDR_RESET "-"

◆ DMA_CH5_AL2_CTRL_ACCESS

#define DMA_CH5_AL2_CTRL_ACCESS "RW"

◆ DMA_CH5_AL2_CTRL_BITS

#define DMA_CH5_AL2_CTRL_BITS _u(0xffffffff)

◆ DMA_CH5_AL2_CTRL_LSB

#define DMA_CH5_AL2_CTRL_LSB _u(0)

◆ DMA_CH5_AL2_CTRL_MSB

#define DMA_CH5_AL2_CTRL_MSB _u(31)

◆ DMA_CH5_AL2_CTRL_OFFSET

#define DMA_CH5_AL2_CTRL_OFFSET _u(0x00000160)

◆ DMA_CH5_AL2_CTRL_RESET

#define DMA_CH5_AL2_CTRL_RESET "-"

◆ DMA_CH5_AL2_READ_ADDR_ACCESS

#define DMA_CH5_AL2_READ_ADDR_ACCESS "RW"

◆ DMA_CH5_AL2_READ_ADDR_BITS

#define DMA_CH5_AL2_READ_ADDR_BITS _u(0xffffffff)

◆ DMA_CH5_AL2_READ_ADDR_LSB

#define DMA_CH5_AL2_READ_ADDR_LSB _u(0)

◆ DMA_CH5_AL2_READ_ADDR_MSB

#define DMA_CH5_AL2_READ_ADDR_MSB _u(31)

◆ DMA_CH5_AL2_READ_ADDR_OFFSET

#define DMA_CH5_AL2_READ_ADDR_OFFSET _u(0x00000168)

◆ DMA_CH5_AL2_READ_ADDR_RESET

#define DMA_CH5_AL2_READ_ADDR_RESET "-"

◆ DMA_CH5_AL2_TRANS_COUNT_ACCESS

#define DMA_CH5_AL2_TRANS_COUNT_ACCESS "RW"

◆ DMA_CH5_AL2_TRANS_COUNT_BITS

#define DMA_CH5_AL2_TRANS_COUNT_BITS _u(0xffffffff)

◆ DMA_CH5_AL2_TRANS_COUNT_LSB

#define DMA_CH5_AL2_TRANS_COUNT_LSB _u(0)

◆ DMA_CH5_AL2_TRANS_COUNT_MSB

#define DMA_CH5_AL2_TRANS_COUNT_MSB _u(31)

◆ DMA_CH5_AL2_TRANS_COUNT_OFFSET

#define DMA_CH5_AL2_TRANS_COUNT_OFFSET _u(0x00000164)

◆ DMA_CH5_AL2_TRANS_COUNT_RESET

#define DMA_CH5_AL2_TRANS_COUNT_RESET "-"

◆ DMA_CH5_AL2_WRITE_ADDR_TRIG_ACCESS

#define DMA_CH5_AL2_WRITE_ADDR_TRIG_ACCESS "RW"

◆ DMA_CH5_AL2_WRITE_ADDR_TRIG_BITS

#define DMA_CH5_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff)

◆ DMA_CH5_AL2_WRITE_ADDR_TRIG_LSB

#define DMA_CH5_AL2_WRITE_ADDR_TRIG_LSB _u(0)

◆ DMA_CH5_AL2_WRITE_ADDR_TRIG_MSB

#define DMA_CH5_AL2_WRITE_ADDR_TRIG_MSB _u(31)

◆ DMA_CH5_AL2_WRITE_ADDR_TRIG_OFFSET

#define DMA_CH5_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x0000016c)

◆ DMA_CH5_AL2_WRITE_ADDR_TRIG_RESET

#define DMA_CH5_AL2_WRITE_ADDR_TRIG_RESET "-"

◆ DMA_CH5_AL3_CTRL_ACCESS

#define DMA_CH5_AL3_CTRL_ACCESS "RW"

◆ DMA_CH5_AL3_CTRL_BITS

#define DMA_CH5_AL3_CTRL_BITS _u(0xffffffff)

◆ DMA_CH5_AL3_CTRL_LSB

#define DMA_CH5_AL3_CTRL_LSB _u(0)

◆ DMA_CH5_AL3_CTRL_MSB

#define DMA_CH5_AL3_CTRL_MSB _u(31)

◆ DMA_CH5_AL3_CTRL_OFFSET

#define DMA_CH5_AL3_CTRL_OFFSET _u(0x00000170)

◆ DMA_CH5_AL3_CTRL_RESET

#define DMA_CH5_AL3_CTRL_RESET "-"

◆ DMA_CH5_AL3_READ_ADDR_TRIG_ACCESS

#define DMA_CH5_AL3_READ_ADDR_TRIG_ACCESS "RW"

◆ DMA_CH5_AL3_READ_ADDR_TRIG_BITS

#define DMA_CH5_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff)

◆ DMA_CH5_AL3_READ_ADDR_TRIG_LSB

#define DMA_CH5_AL3_READ_ADDR_TRIG_LSB _u(0)

◆ DMA_CH5_AL3_READ_ADDR_TRIG_MSB

#define DMA_CH5_AL3_READ_ADDR_TRIG_MSB _u(31)

◆ DMA_CH5_AL3_READ_ADDR_TRIG_OFFSET

#define DMA_CH5_AL3_READ_ADDR_TRIG_OFFSET _u(0x0000017c)

◆ DMA_CH5_AL3_READ_ADDR_TRIG_RESET

#define DMA_CH5_AL3_READ_ADDR_TRIG_RESET "-"

◆ DMA_CH5_AL3_TRANS_COUNT_ACCESS

#define DMA_CH5_AL3_TRANS_COUNT_ACCESS "RW"

◆ DMA_CH5_AL3_TRANS_COUNT_BITS

#define DMA_CH5_AL3_TRANS_COUNT_BITS _u(0xffffffff)

◆ DMA_CH5_AL3_TRANS_COUNT_LSB

#define DMA_CH5_AL3_TRANS_COUNT_LSB _u(0)

◆ DMA_CH5_AL3_TRANS_COUNT_MSB

#define DMA_CH5_AL3_TRANS_COUNT_MSB _u(31)

◆ DMA_CH5_AL3_TRANS_COUNT_OFFSET

#define DMA_CH5_AL3_TRANS_COUNT_OFFSET _u(0x00000178)

◆ DMA_CH5_AL3_TRANS_COUNT_RESET

#define DMA_CH5_AL3_TRANS_COUNT_RESET "-"

◆ DMA_CH5_AL3_WRITE_ADDR_ACCESS

#define DMA_CH5_AL3_WRITE_ADDR_ACCESS "RW"

◆ DMA_CH5_AL3_WRITE_ADDR_BITS

#define DMA_CH5_AL3_WRITE_ADDR_BITS _u(0xffffffff)

◆ DMA_CH5_AL3_WRITE_ADDR_LSB

#define DMA_CH5_AL3_WRITE_ADDR_LSB _u(0)

◆ DMA_CH5_AL3_WRITE_ADDR_MSB

#define DMA_CH5_AL3_WRITE_ADDR_MSB _u(31)

◆ DMA_CH5_AL3_WRITE_ADDR_OFFSET

#define DMA_CH5_AL3_WRITE_ADDR_OFFSET _u(0x00000174)

◆ DMA_CH5_AL3_WRITE_ADDR_RESET

#define DMA_CH5_AL3_WRITE_ADDR_RESET "-"

◆ DMA_CH5_CTRL_TRIG_AHB_ERROR_ACCESS

#define DMA_CH5_CTRL_TRIG_AHB_ERROR_ACCESS "RO"

◆ DMA_CH5_CTRL_TRIG_AHB_ERROR_BITS

#define DMA_CH5_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000)

◆ DMA_CH5_CTRL_TRIG_AHB_ERROR_LSB

#define DMA_CH5_CTRL_TRIG_AHB_ERROR_LSB _u(31)

◆ DMA_CH5_CTRL_TRIG_AHB_ERROR_MSB

#define DMA_CH5_CTRL_TRIG_AHB_ERROR_MSB _u(31)

◆ DMA_CH5_CTRL_TRIG_AHB_ERROR_RESET

#define DMA_CH5_CTRL_TRIG_AHB_ERROR_RESET _u(0x0)

◆ DMA_CH5_CTRL_TRIG_BITS

#define DMA_CH5_CTRL_TRIG_BITS _u(0xe7ffffff)

◆ DMA_CH5_CTRL_TRIG_BSWAP_ACCESS

#define DMA_CH5_CTRL_TRIG_BSWAP_ACCESS "RW"

◆ DMA_CH5_CTRL_TRIG_BSWAP_BITS

#define DMA_CH5_CTRL_TRIG_BSWAP_BITS _u(0x01000000)

◆ DMA_CH5_CTRL_TRIG_BSWAP_LSB

#define DMA_CH5_CTRL_TRIG_BSWAP_LSB _u(24)

◆ DMA_CH5_CTRL_TRIG_BSWAP_MSB

#define DMA_CH5_CTRL_TRIG_BSWAP_MSB _u(24)

◆ DMA_CH5_CTRL_TRIG_BSWAP_RESET

#define DMA_CH5_CTRL_TRIG_BSWAP_RESET _u(0x0)

◆ DMA_CH5_CTRL_TRIG_BUSY_ACCESS

#define DMA_CH5_CTRL_TRIG_BUSY_ACCESS "RO"

◆ DMA_CH5_CTRL_TRIG_BUSY_BITS

#define DMA_CH5_CTRL_TRIG_BUSY_BITS _u(0x04000000)

◆ DMA_CH5_CTRL_TRIG_BUSY_LSB

#define DMA_CH5_CTRL_TRIG_BUSY_LSB _u(26)

◆ DMA_CH5_CTRL_TRIG_BUSY_MSB

#define DMA_CH5_CTRL_TRIG_BUSY_MSB _u(26)

◆ DMA_CH5_CTRL_TRIG_BUSY_RESET

#define DMA_CH5_CTRL_TRIG_BUSY_RESET _u(0x0)

◆ DMA_CH5_CTRL_TRIG_CHAIN_TO_ACCESS

#define DMA_CH5_CTRL_TRIG_CHAIN_TO_ACCESS "RW"

◆ DMA_CH5_CTRL_TRIG_CHAIN_TO_BITS

#define DMA_CH5_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000)

◆ DMA_CH5_CTRL_TRIG_CHAIN_TO_LSB

#define DMA_CH5_CTRL_TRIG_CHAIN_TO_LSB _u(13)

◆ DMA_CH5_CTRL_TRIG_CHAIN_TO_MSB

#define DMA_CH5_CTRL_TRIG_CHAIN_TO_MSB _u(16)

◆ DMA_CH5_CTRL_TRIG_CHAIN_TO_RESET

#define DMA_CH5_CTRL_TRIG_CHAIN_TO_RESET _u(0x0)

◆ DMA_CH5_CTRL_TRIG_DATA_SIZE_ACCESS

#define DMA_CH5_CTRL_TRIG_DATA_SIZE_ACCESS "RW"

◆ DMA_CH5_CTRL_TRIG_DATA_SIZE_BITS

#define DMA_CH5_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c)

◆ DMA_CH5_CTRL_TRIG_DATA_SIZE_LSB

#define DMA_CH5_CTRL_TRIG_DATA_SIZE_LSB _u(2)

◆ DMA_CH5_CTRL_TRIG_DATA_SIZE_MSB

#define DMA_CH5_CTRL_TRIG_DATA_SIZE_MSB _u(3)

◆ DMA_CH5_CTRL_TRIG_DATA_SIZE_RESET

#define DMA_CH5_CTRL_TRIG_DATA_SIZE_RESET _u(0x0)

◆ DMA_CH5_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE

#define DMA_CH5_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0)

◆ DMA_CH5_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD

#define DMA_CH5_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1)

◆ DMA_CH5_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD

#define DMA_CH5_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2)

◆ DMA_CH5_CTRL_TRIG_EN_ACCESS

#define DMA_CH5_CTRL_TRIG_EN_ACCESS "RW"

◆ DMA_CH5_CTRL_TRIG_EN_BITS

#define DMA_CH5_CTRL_TRIG_EN_BITS _u(0x00000001)

◆ DMA_CH5_CTRL_TRIG_EN_LSB

#define DMA_CH5_CTRL_TRIG_EN_LSB _u(0)

◆ DMA_CH5_CTRL_TRIG_EN_MSB

#define DMA_CH5_CTRL_TRIG_EN_MSB _u(0)

◆ DMA_CH5_CTRL_TRIG_EN_RESET

#define DMA_CH5_CTRL_TRIG_EN_RESET _u(0x0)

◆ DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_ACCESS

#define DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW"

◆ DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_BITS

#define DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002)

◆ DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_LSB

#define DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1)

◆ DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_MSB

#define DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1)

◆ DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_RESET

#define DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0)

◆ DMA_CH5_CTRL_TRIG_INCR_READ_ACCESS

#define DMA_CH5_CTRL_TRIG_INCR_READ_ACCESS "RW"

◆ DMA_CH5_CTRL_TRIG_INCR_READ_BITS

#define DMA_CH5_CTRL_TRIG_INCR_READ_BITS _u(0x00000010)

◆ DMA_CH5_CTRL_TRIG_INCR_READ_LSB

#define DMA_CH5_CTRL_TRIG_INCR_READ_LSB _u(4)

◆ DMA_CH5_CTRL_TRIG_INCR_READ_MSB

#define DMA_CH5_CTRL_TRIG_INCR_READ_MSB _u(4)

◆ DMA_CH5_CTRL_TRIG_INCR_READ_RESET

#define DMA_CH5_CTRL_TRIG_INCR_READ_RESET _u(0x0)

◆ DMA_CH5_CTRL_TRIG_INCR_READ_REV_ACCESS

#define DMA_CH5_CTRL_TRIG_INCR_READ_REV_ACCESS "RW"

◆ DMA_CH5_CTRL_TRIG_INCR_READ_REV_BITS

#define DMA_CH5_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020)

◆ DMA_CH5_CTRL_TRIG_INCR_READ_REV_LSB

#define DMA_CH5_CTRL_TRIG_INCR_READ_REV_LSB _u(5)

◆ DMA_CH5_CTRL_TRIG_INCR_READ_REV_MSB

#define DMA_CH5_CTRL_TRIG_INCR_READ_REV_MSB _u(5)

◆ DMA_CH5_CTRL_TRIG_INCR_READ_REV_RESET

#define DMA_CH5_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0)

◆ DMA_CH5_CTRL_TRIG_INCR_WRITE_ACCESS

#define DMA_CH5_CTRL_TRIG_INCR_WRITE_ACCESS "RW"

◆ DMA_CH5_CTRL_TRIG_INCR_WRITE_BITS

#define DMA_CH5_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040)

◆ DMA_CH5_CTRL_TRIG_INCR_WRITE_LSB

#define DMA_CH5_CTRL_TRIG_INCR_WRITE_LSB _u(6)

◆ DMA_CH5_CTRL_TRIG_INCR_WRITE_MSB

#define DMA_CH5_CTRL_TRIG_INCR_WRITE_MSB _u(6)

◆ DMA_CH5_CTRL_TRIG_INCR_WRITE_RESET

#define DMA_CH5_CTRL_TRIG_INCR_WRITE_RESET _u(0x0)

◆ DMA_CH5_CTRL_TRIG_INCR_WRITE_REV_ACCESS

#define DMA_CH5_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW"

◆ DMA_CH5_CTRL_TRIG_INCR_WRITE_REV_BITS

#define DMA_CH5_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080)

◆ DMA_CH5_CTRL_TRIG_INCR_WRITE_REV_LSB

#define DMA_CH5_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7)

◆ DMA_CH5_CTRL_TRIG_INCR_WRITE_REV_MSB

#define DMA_CH5_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7)

◆ DMA_CH5_CTRL_TRIG_INCR_WRITE_REV_RESET

#define DMA_CH5_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0)

◆ DMA_CH5_CTRL_TRIG_IRQ_QUIET_ACCESS

#define DMA_CH5_CTRL_TRIG_IRQ_QUIET_ACCESS "RW"

◆ DMA_CH5_CTRL_TRIG_IRQ_QUIET_BITS

#define DMA_CH5_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000)

◆ DMA_CH5_CTRL_TRIG_IRQ_QUIET_LSB

#define DMA_CH5_CTRL_TRIG_IRQ_QUIET_LSB _u(23)

◆ DMA_CH5_CTRL_TRIG_IRQ_QUIET_MSB

#define DMA_CH5_CTRL_TRIG_IRQ_QUIET_MSB _u(23)

◆ DMA_CH5_CTRL_TRIG_IRQ_QUIET_RESET

#define DMA_CH5_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0)

◆ DMA_CH5_CTRL_TRIG_OFFSET

#define DMA_CH5_CTRL_TRIG_OFFSET _u(0x0000014c)

◆ DMA_CH5_CTRL_TRIG_READ_ERROR_ACCESS

#define DMA_CH5_CTRL_TRIG_READ_ERROR_ACCESS "WC"

◆ DMA_CH5_CTRL_TRIG_READ_ERROR_BITS

#define DMA_CH5_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000)

◆ DMA_CH5_CTRL_TRIG_READ_ERROR_LSB

#define DMA_CH5_CTRL_TRIG_READ_ERROR_LSB _u(30)

◆ DMA_CH5_CTRL_TRIG_READ_ERROR_MSB

#define DMA_CH5_CTRL_TRIG_READ_ERROR_MSB _u(30)

◆ DMA_CH5_CTRL_TRIG_READ_ERROR_RESET

#define DMA_CH5_CTRL_TRIG_READ_ERROR_RESET _u(0x0)

◆ DMA_CH5_CTRL_TRIG_RESET

#define DMA_CH5_CTRL_TRIG_RESET _u(0x00000000)

◆ DMA_CH5_CTRL_TRIG_RING_SEL_ACCESS

#define DMA_CH5_CTRL_TRIG_RING_SEL_ACCESS "RW"

◆ DMA_CH5_CTRL_TRIG_RING_SEL_BITS

#define DMA_CH5_CTRL_TRIG_RING_SEL_BITS _u(0x00001000)

◆ DMA_CH5_CTRL_TRIG_RING_SEL_LSB

#define DMA_CH5_CTRL_TRIG_RING_SEL_LSB _u(12)

◆ DMA_CH5_CTRL_TRIG_RING_SEL_MSB

#define DMA_CH5_CTRL_TRIG_RING_SEL_MSB _u(12)

◆ DMA_CH5_CTRL_TRIG_RING_SEL_RESET

#define DMA_CH5_CTRL_TRIG_RING_SEL_RESET _u(0x0)

◆ DMA_CH5_CTRL_TRIG_RING_SIZE_ACCESS

#define DMA_CH5_CTRL_TRIG_RING_SIZE_ACCESS "RW"

◆ DMA_CH5_CTRL_TRIG_RING_SIZE_BITS

#define DMA_CH5_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00)

◆ DMA_CH5_CTRL_TRIG_RING_SIZE_LSB

#define DMA_CH5_CTRL_TRIG_RING_SIZE_LSB _u(8)

◆ DMA_CH5_CTRL_TRIG_RING_SIZE_MSB

#define DMA_CH5_CTRL_TRIG_RING_SIZE_MSB _u(11)

◆ DMA_CH5_CTRL_TRIG_RING_SIZE_RESET

#define DMA_CH5_CTRL_TRIG_RING_SIZE_RESET _u(0x0)

◆ DMA_CH5_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE

#define DMA_CH5_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0)

◆ DMA_CH5_CTRL_TRIG_SNIFF_EN_ACCESS

#define DMA_CH5_CTRL_TRIG_SNIFF_EN_ACCESS "RW"

◆ DMA_CH5_CTRL_TRIG_SNIFF_EN_BITS

#define DMA_CH5_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000)

◆ DMA_CH5_CTRL_TRIG_SNIFF_EN_LSB

#define DMA_CH5_CTRL_TRIG_SNIFF_EN_LSB _u(25)

◆ DMA_CH5_CTRL_TRIG_SNIFF_EN_MSB

#define DMA_CH5_CTRL_TRIG_SNIFF_EN_MSB _u(25)

◆ DMA_CH5_CTRL_TRIG_SNIFF_EN_RESET

#define DMA_CH5_CTRL_TRIG_SNIFF_EN_RESET _u(0x0)

◆ DMA_CH5_CTRL_TRIG_TREQ_SEL_ACCESS

#define DMA_CH5_CTRL_TRIG_TREQ_SEL_ACCESS "RW"

◆ DMA_CH5_CTRL_TRIG_TREQ_SEL_BITS

#define DMA_CH5_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000)

◆ DMA_CH5_CTRL_TRIG_TREQ_SEL_LSB

#define DMA_CH5_CTRL_TRIG_TREQ_SEL_LSB _u(17)

◆ DMA_CH5_CTRL_TRIG_TREQ_SEL_MSB

#define DMA_CH5_CTRL_TRIG_TREQ_SEL_MSB _u(22)

◆ DMA_CH5_CTRL_TRIG_TREQ_SEL_RESET

#define DMA_CH5_CTRL_TRIG_TREQ_SEL_RESET _u(0x00)

◆ DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT

#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f)

◆ DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0

#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b)

◆ DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1

#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c)

◆ DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2

#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d)

◆ DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3

#define DMA_CH5_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e)

◆ DMA_CH5_CTRL_TRIG_WRITE_ERROR_ACCESS

#define DMA_CH5_CTRL_TRIG_WRITE_ERROR_ACCESS "WC"

◆ DMA_CH5_CTRL_TRIG_WRITE_ERROR_BITS

#define DMA_CH5_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000)

◆ DMA_CH5_CTRL_TRIG_WRITE_ERROR_LSB

#define DMA_CH5_CTRL_TRIG_WRITE_ERROR_LSB _u(29)

◆ DMA_CH5_CTRL_TRIG_WRITE_ERROR_MSB

#define DMA_CH5_CTRL_TRIG_WRITE_ERROR_MSB _u(29)

◆ DMA_CH5_CTRL_TRIG_WRITE_ERROR_RESET

#define DMA_CH5_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0)

◆ DMA_CH5_DBG_CTDREQ_ACCESS

#define DMA_CH5_DBG_CTDREQ_ACCESS "WC"

◆ DMA_CH5_DBG_CTDREQ_BITS

#define DMA_CH5_DBG_CTDREQ_BITS _u(0x0000003f)

◆ DMA_CH5_DBG_CTDREQ_LSB

#define DMA_CH5_DBG_CTDREQ_LSB _u(0)

◆ DMA_CH5_DBG_CTDREQ_MSB

#define DMA_CH5_DBG_CTDREQ_MSB _u(5)

◆ DMA_CH5_DBG_CTDREQ_OFFSET

#define DMA_CH5_DBG_CTDREQ_OFFSET _u(0x00000940)

◆ DMA_CH5_DBG_CTDREQ_RESET

#define DMA_CH5_DBG_CTDREQ_RESET _u(0x00000000)

◆ DMA_CH5_DBG_TCR_ACCESS

#define DMA_CH5_DBG_TCR_ACCESS "RO"

◆ DMA_CH5_DBG_TCR_BITS

#define DMA_CH5_DBG_TCR_BITS _u(0xffffffff)

◆ DMA_CH5_DBG_TCR_LSB

#define DMA_CH5_DBG_TCR_LSB _u(0)

◆ DMA_CH5_DBG_TCR_MSB

#define DMA_CH5_DBG_TCR_MSB _u(31)

◆ DMA_CH5_DBG_TCR_OFFSET

#define DMA_CH5_DBG_TCR_OFFSET _u(0x00000944)

◆ DMA_CH5_DBG_TCR_RESET

#define DMA_CH5_DBG_TCR_RESET _u(0x00000000)

◆ DMA_CH5_READ_ADDR_ACCESS

#define DMA_CH5_READ_ADDR_ACCESS "RW"

◆ DMA_CH5_READ_ADDR_BITS

#define DMA_CH5_READ_ADDR_BITS _u(0xffffffff)

◆ DMA_CH5_READ_ADDR_LSB

#define DMA_CH5_READ_ADDR_LSB _u(0)

◆ DMA_CH5_READ_ADDR_MSB

#define DMA_CH5_READ_ADDR_MSB _u(31)

◆ DMA_CH5_READ_ADDR_OFFSET

#define DMA_CH5_READ_ADDR_OFFSET _u(0x00000140)

◆ DMA_CH5_READ_ADDR_RESET

#define DMA_CH5_READ_ADDR_RESET _u(0x00000000)

◆ DMA_CH5_TRANS_COUNT_BITS

#define DMA_CH5_TRANS_COUNT_BITS _u(0xffffffff)

◆ DMA_CH5_TRANS_COUNT_COUNT_ACCESS

#define DMA_CH5_TRANS_COUNT_COUNT_ACCESS "RW"

◆ DMA_CH5_TRANS_COUNT_COUNT_BITS

#define DMA_CH5_TRANS_COUNT_COUNT_BITS _u(0x0fffffff)

◆ DMA_CH5_TRANS_COUNT_COUNT_LSB

#define DMA_CH5_TRANS_COUNT_COUNT_LSB _u(0)

◆ DMA_CH5_TRANS_COUNT_COUNT_MSB

#define DMA_CH5_TRANS_COUNT_COUNT_MSB _u(27)

◆ DMA_CH5_TRANS_COUNT_COUNT_RESET

#define DMA_CH5_TRANS_COUNT_COUNT_RESET _u(0x0000000)

◆ DMA_CH5_TRANS_COUNT_MODE_ACCESS

#define DMA_CH5_TRANS_COUNT_MODE_ACCESS "RW"

◆ DMA_CH5_TRANS_COUNT_MODE_BITS

#define DMA_CH5_TRANS_COUNT_MODE_BITS _u(0xf0000000)

◆ DMA_CH5_TRANS_COUNT_MODE_LSB

#define DMA_CH5_TRANS_COUNT_MODE_LSB _u(28)

◆ DMA_CH5_TRANS_COUNT_MODE_MSB

#define DMA_CH5_TRANS_COUNT_MODE_MSB _u(31)

◆ DMA_CH5_TRANS_COUNT_MODE_RESET

#define DMA_CH5_TRANS_COUNT_MODE_RESET _u(0x0)

◆ DMA_CH5_TRANS_COUNT_MODE_VALUE_ENDLESS

#define DMA_CH5_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf)

◆ DMA_CH5_TRANS_COUNT_MODE_VALUE_NORMAL

#define DMA_CH5_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0)

◆ DMA_CH5_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF

#define DMA_CH5_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1)

◆ DMA_CH5_TRANS_COUNT_OFFSET

#define DMA_CH5_TRANS_COUNT_OFFSET _u(0x00000148)

◆ DMA_CH5_TRANS_COUNT_RESET

#define DMA_CH5_TRANS_COUNT_RESET _u(0x00000000)

◆ DMA_CH5_WRITE_ADDR_ACCESS

#define DMA_CH5_WRITE_ADDR_ACCESS "RW"

◆ DMA_CH5_WRITE_ADDR_BITS

#define DMA_CH5_WRITE_ADDR_BITS _u(0xffffffff)

◆ DMA_CH5_WRITE_ADDR_LSB

#define DMA_CH5_WRITE_ADDR_LSB _u(0)

◆ DMA_CH5_WRITE_ADDR_MSB

#define DMA_CH5_WRITE_ADDR_MSB _u(31)

◆ DMA_CH5_WRITE_ADDR_OFFSET

#define DMA_CH5_WRITE_ADDR_OFFSET _u(0x00000144)

◆ DMA_CH5_WRITE_ADDR_RESET

#define DMA_CH5_WRITE_ADDR_RESET _u(0x00000000)

◆ DMA_CH6_AL1_CTRL_ACCESS

#define DMA_CH6_AL1_CTRL_ACCESS "RW"

◆ DMA_CH6_AL1_CTRL_BITS

#define DMA_CH6_AL1_CTRL_BITS _u(0xffffffff)

◆ DMA_CH6_AL1_CTRL_LSB

#define DMA_CH6_AL1_CTRL_LSB _u(0)

◆ DMA_CH6_AL1_CTRL_MSB

#define DMA_CH6_AL1_CTRL_MSB _u(31)

◆ DMA_CH6_AL1_CTRL_OFFSET

#define DMA_CH6_AL1_CTRL_OFFSET _u(0x00000190)

◆ DMA_CH6_AL1_CTRL_RESET

#define DMA_CH6_AL1_CTRL_RESET "-"

◆ DMA_CH6_AL1_READ_ADDR_ACCESS

#define DMA_CH6_AL1_READ_ADDR_ACCESS "RW"

◆ DMA_CH6_AL1_READ_ADDR_BITS

#define DMA_CH6_AL1_READ_ADDR_BITS _u(0xffffffff)

◆ DMA_CH6_AL1_READ_ADDR_LSB

#define DMA_CH6_AL1_READ_ADDR_LSB _u(0)

◆ DMA_CH6_AL1_READ_ADDR_MSB

#define DMA_CH6_AL1_READ_ADDR_MSB _u(31)

◆ DMA_CH6_AL1_READ_ADDR_OFFSET

#define DMA_CH6_AL1_READ_ADDR_OFFSET _u(0x00000194)

◆ DMA_CH6_AL1_READ_ADDR_RESET

#define DMA_CH6_AL1_READ_ADDR_RESET "-"

◆ DMA_CH6_AL1_TRANS_COUNT_TRIG_ACCESS

#define DMA_CH6_AL1_TRANS_COUNT_TRIG_ACCESS "RW"

◆ DMA_CH6_AL1_TRANS_COUNT_TRIG_BITS

#define DMA_CH6_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff)

◆ DMA_CH6_AL1_TRANS_COUNT_TRIG_LSB

#define DMA_CH6_AL1_TRANS_COUNT_TRIG_LSB _u(0)

◆ DMA_CH6_AL1_TRANS_COUNT_TRIG_MSB

#define DMA_CH6_AL1_TRANS_COUNT_TRIG_MSB _u(31)

◆ DMA_CH6_AL1_TRANS_COUNT_TRIG_OFFSET

#define DMA_CH6_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000019c)

◆ DMA_CH6_AL1_TRANS_COUNT_TRIG_RESET

#define DMA_CH6_AL1_TRANS_COUNT_TRIG_RESET "-"

◆ DMA_CH6_AL1_WRITE_ADDR_ACCESS

#define DMA_CH6_AL1_WRITE_ADDR_ACCESS "RW"

◆ DMA_CH6_AL1_WRITE_ADDR_BITS

#define DMA_CH6_AL1_WRITE_ADDR_BITS _u(0xffffffff)

◆ DMA_CH6_AL1_WRITE_ADDR_LSB

#define DMA_CH6_AL1_WRITE_ADDR_LSB _u(0)

◆ DMA_CH6_AL1_WRITE_ADDR_MSB

#define DMA_CH6_AL1_WRITE_ADDR_MSB _u(31)

◆ DMA_CH6_AL1_WRITE_ADDR_OFFSET

#define DMA_CH6_AL1_WRITE_ADDR_OFFSET _u(0x00000198)

◆ DMA_CH6_AL1_WRITE_ADDR_RESET

#define DMA_CH6_AL1_WRITE_ADDR_RESET "-"

◆ DMA_CH6_AL2_CTRL_ACCESS

#define DMA_CH6_AL2_CTRL_ACCESS "RW"

◆ DMA_CH6_AL2_CTRL_BITS

#define DMA_CH6_AL2_CTRL_BITS _u(0xffffffff)

◆ DMA_CH6_AL2_CTRL_LSB

#define DMA_CH6_AL2_CTRL_LSB _u(0)

◆ DMA_CH6_AL2_CTRL_MSB

#define DMA_CH6_AL2_CTRL_MSB _u(31)

◆ DMA_CH6_AL2_CTRL_OFFSET

#define DMA_CH6_AL2_CTRL_OFFSET _u(0x000001a0)

◆ DMA_CH6_AL2_CTRL_RESET

#define DMA_CH6_AL2_CTRL_RESET "-"

◆ DMA_CH6_AL2_READ_ADDR_ACCESS

#define DMA_CH6_AL2_READ_ADDR_ACCESS "RW"

◆ DMA_CH6_AL2_READ_ADDR_BITS

#define DMA_CH6_AL2_READ_ADDR_BITS _u(0xffffffff)

◆ DMA_CH6_AL2_READ_ADDR_LSB

#define DMA_CH6_AL2_READ_ADDR_LSB _u(0)

◆ DMA_CH6_AL2_READ_ADDR_MSB

#define DMA_CH6_AL2_READ_ADDR_MSB _u(31)

◆ DMA_CH6_AL2_READ_ADDR_OFFSET

#define DMA_CH6_AL2_READ_ADDR_OFFSET _u(0x000001a8)

◆ DMA_CH6_AL2_READ_ADDR_RESET

#define DMA_CH6_AL2_READ_ADDR_RESET "-"

◆ DMA_CH6_AL2_TRANS_COUNT_ACCESS

#define DMA_CH6_AL2_TRANS_COUNT_ACCESS "RW"

◆ DMA_CH6_AL2_TRANS_COUNT_BITS

#define DMA_CH6_AL2_TRANS_COUNT_BITS _u(0xffffffff)

◆ DMA_CH6_AL2_TRANS_COUNT_LSB

#define DMA_CH6_AL2_TRANS_COUNT_LSB _u(0)

◆ DMA_CH6_AL2_TRANS_COUNT_MSB

#define DMA_CH6_AL2_TRANS_COUNT_MSB _u(31)

◆ DMA_CH6_AL2_TRANS_COUNT_OFFSET

#define DMA_CH6_AL2_TRANS_COUNT_OFFSET _u(0x000001a4)

◆ DMA_CH6_AL2_TRANS_COUNT_RESET

#define DMA_CH6_AL2_TRANS_COUNT_RESET "-"

◆ DMA_CH6_AL2_WRITE_ADDR_TRIG_ACCESS

#define DMA_CH6_AL2_WRITE_ADDR_TRIG_ACCESS "RW"

◆ DMA_CH6_AL2_WRITE_ADDR_TRIG_BITS

#define DMA_CH6_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff)

◆ DMA_CH6_AL2_WRITE_ADDR_TRIG_LSB

#define DMA_CH6_AL2_WRITE_ADDR_TRIG_LSB _u(0)

◆ DMA_CH6_AL2_WRITE_ADDR_TRIG_MSB

#define DMA_CH6_AL2_WRITE_ADDR_TRIG_MSB _u(31)

◆ DMA_CH6_AL2_WRITE_ADDR_TRIG_OFFSET

#define DMA_CH6_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x000001ac)

◆ DMA_CH6_AL2_WRITE_ADDR_TRIG_RESET

#define DMA_CH6_AL2_WRITE_ADDR_TRIG_RESET "-"

◆ DMA_CH6_AL3_CTRL_ACCESS

#define DMA_CH6_AL3_CTRL_ACCESS "RW"

◆ DMA_CH6_AL3_CTRL_BITS

#define DMA_CH6_AL3_CTRL_BITS _u(0xffffffff)

◆ DMA_CH6_AL3_CTRL_LSB

#define DMA_CH6_AL3_CTRL_LSB _u(0)

◆ DMA_CH6_AL3_CTRL_MSB

#define DMA_CH6_AL3_CTRL_MSB _u(31)

◆ DMA_CH6_AL3_CTRL_OFFSET

#define DMA_CH6_AL3_CTRL_OFFSET _u(0x000001b0)

◆ DMA_CH6_AL3_CTRL_RESET

#define DMA_CH6_AL3_CTRL_RESET "-"

◆ DMA_CH6_AL3_READ_ADDR_TRIG_ACCESS

#define DMA_CH6_AL3_READ_ADDR_TRIG_ACCESS "RW"

◆ DMA_CH6_AL3_READ_ADDR_TRIG_BITS

#define DMA_CH6_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff)

◆ DMA_CH6_AL3_READ_ADDR_TRIG_LSB

#define DMA_CH6_AL3_READ_ADDR_TRIG_LSB _u(0)

◆ DMA_CH6_AL3_READ_ADDR_TRIG_MSB

#define DMA_CH6_AL3_READ_ADDR_TRIG_MSB _u(31)

◆ DMA_CH6_AL3_READ_ADDR_TRIG_OFFSET

#define DMA_CH6_AL3_READ_ADDR_TRIG_OFFSET _u(0x000001bc)

◆ DMA_CH6_AL3_READ_ADDR_TRIG_RESET

#define DMA_CH6_AL3_READ_ADDR_TRIG_RESET "-"

◆ DMA_CH6_AL3_TRANS_COUNT_ACCESS

#define DMA_CH6_AL3_TRANS_COUNT_ACCESS "RW"

◆ DMA_CH6_AL3_TRANS_COUNT_BITS

#define DMA_CH6_AL3_TRANS_COUNT_BITS _u(0xffffffff)

◆ DMA_CH6_AL3_TRANS_COUNT_LSB

#define DMA_CH6_AL3_TRANS_COUNT_LSB _u(0)

◆ DMA_CH6_AL3_TRANS_COUNT_MSB

#define DMA_CH6_AL3_TRANS_COUNT_MSB _u(31)

◆ DMA_CH6_AL3_TRANS_COUNT_OFFSET

#define DMA_CH6_AL3_TRANS_COUNT_OFFSET _u(0x000001b8)

◆ DMA_CH6_AL3_TRANS_COUNT_RESET

#define DMA_CH6_AL3_TRANS_COUNT_RESET "-"

◆ DMA_CH6_AL3_WRITE_ADDR_ACCESS

#define DMA_CH6_AL3_WRITE_ADDR_ACCESS "RW"

◆ DMA_CH6_AL3_WRITE_ADDR_BITS

#define DMA_CH6_AL3_WRITE_ADDR_BITS _u(0xffffffff)

◆ DMA_CH6_AL3_WRITE_ADDR_LSB

#define DMA_CH6_AL3_WRITE_ADDR_LSB _u(0)

◆ DMA_CH6_AL3_WRITE_ADDR_MSB

#define DMA_CH6_AL3_WRITE_ADDR_MSB _u(31)

◆ DMA_CH6_AL3_WRITE_ADDR_OFFSET

#define DMA_CH6_AL3_WRITE_ADDR_OFFSET _u(0x000001b4)

◆ DMA_CH6_AL3_WRITE_ADDR_RESET

#define DMA_CH6_AL3_WRITE_ADDR_RESET "-"

◆ DMA_CH6_CTRL_TRIG_AHB_ERROR_ACCESS

#define DMA_CH6_CTRL_TRIG_AHB_ERROR_ACCESS "RO"

◆ DMA_CH6_CTRL_TRIG_AHB_ERROR_BITS

#define DMA_CH6_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000)

◆ DMA_CH6_CTRL_TRIG_AHB_ERROR_LSB

#define DMA_CH6_CTRL_TRIG_AHB_ERROR_LSB _u(31)

◆ DMA_CH6_CTRL_TRIG_AHB_ERROR_MSB

#define DMA_CH6_CTRL_TRIG_AHB_ERROR_MSB _u(31)

◆ DMA_CH6_CTRL_TRIG_AHB_ERROR_RESET

#define DMA_CH6_CTRL_TRIG_AHB_ERROR_RESET _u(0x0)

◆ DMA_CH6_CTRL_TRIG_BITS

#define DMA_CH6_CTRL_TRIG_BITS _u(0xe7ffffff)

◆ DMA_CH6_CTRL_TRIG_BSWAP_ACCESS

#define DMA_CH6_CTRL_TRIG_BSWAP_ACCESS "RW"

◆ DMA_CH6_CTRL_TRIG_BSWAP_BITS

#define DMA_CH6_CTRL_TRIG_BSWAP_BITS _u(0x01000000)

◆ DMA_CH6_CTRL_TRIG_BSWAP_LSB

#define DMA_CH6_CTRL_TRIG_BSWAP_LSB _u(24)

◆ DMA_CH6_CTRL_TRIG_BSWAP_MSB

#define DMA_CH6_CTRL_TRIG_BSWAP_MSB _u(24)

◆ DMA_CH6_CTRL_TRIG_BSWAP_RESET

#define DMA_CH6_CTRL_TRIG_BSWAP_RESET _u(0x0)

◆ DMA_CH6_CTRL_TRIG_BUSY_ACCESS

#define DMA_CH6_CTRL_TRIG_BUSY_ACCESS "RO"

◆ DMA_CH6_CTRL_TRIG_BUSY_BITS

#define DMA_CH6_CTRL_TRIG_BUSY_BITS _u(0x04000000)

◆ DMA_CH6_CTRL_TRIG_BUSY_LSB

#define DMA_CH6_CTRL_TRIG_BUSY_LSB _u(26)

◆ DMA_CH6_CTRL_TRIG_BUSY_MSB

#define DMA_CH6_CTRL_TRIG_BUSY_MSB _u(26)

◆ DMA_CH6_CTRL_TRIG_BUSY_RESET

#define DMA_CH6_CTRL_TRIG_BUSY_RESET _u(0x0)

◆ DMA_CH6_CTRL_TRIG_CHAIN_TO_ACCESS

#define DMA_CH6_CTRL_TRIG_CHAIN_TO_ACCESS "RW"

◆ DMA_CH6_CTRL_TRIG_CHAIN_TO_BITS

#define DMA_CH6_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000)

◆ DMA_CH6_CTRL_TRIG_CHAIN_TO_LSB

#define DMA_CH6_CTRL_TRIG_CHAIN_TO_LSB _u(13)

◆ DMA_CH6_CTRL_TRIG_CHAIN_TO_MSB

#define DMA_CH6_CTRL_TRIG_CHAIN_TO_MSB _u(16)

◆ DMA_CH6_CTRL_TRIG_CHAIN_TO_RESET

#define DMA_CH6_CTRL_TRIG_CHAIN_TO_RESET _u(0x0)

◆ DMA_CH6_CTRL_TRIG_DATA_SIZE_ACCESS

#define DMA_CH6_CTRL_TRIG_DATA_SIZE_ACCESS "RW"

◆ DMA_CH6_CTRL_TRIG_DATA_SIZE_BITS

#define DMA_CH6_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c)

◆ DMA_CH6_CTRL_TRIG_DATA_SIZE_LSB

#define DMA_CH6_CTRL_TRIG_DATA_SIZE_LSB _u(2)

◆ DMA_CH6_CTRL_TRIG_DATA_SIZE_MSB

#define DMA_CH6_CTRL_TRIG_DATA_SIZE_MSB _u(3)

◆ DMA_CH6_CTRL_TRIG_DATA_SIZE_RESET

#define DMA_CH6_CTRL_TRIG_DATA_SIZE_RESET _u(0x0)

◆ DMA_CH6_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE

#define DMA_CH6_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0)

◆ DMA_CH6_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD

#define DMA_CH6_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1)

◆ DMA_CH6_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD

#define DMA_CH6_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2)

◆ DMA_CH6_CTRL_TRIG_EN_ACCESS

#define DMA_CH6_CTRL_TRIG_EN_ACCESS "RW"

◆ DMA_CH6_CTRL_TRIG_EN_BITS

#define DMA_CH6_CTRL_TRIG_EN_BITS _u(0x00000001)

◆ DMA_CH6_CTRL_TRIG_EN_LSB

#define DMA_CH6_CTRL_TRIG_EN_LSB _u(0)

◆ DMA_CH6_CTRL_TRIG_EN_MSB

#define DMA_CH6_CTRL_TRIG_EN_MSB _u(0)

◆ DMA_CH6_CTRL_TRIG_EN_RESET

#define DMA_CH6_CTRL_TRIG_EN_RESET _u(0x0)

◆ DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_ACCESS

#define DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW"

◆ DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_BITS

#define DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002)

◆ DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_LSB

#define DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1)

◆ DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_MSB

#define DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1)

◆ DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_RESET

#define DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0)

◆ DMA_CH6_CTRL_TRIG_INCR_READ_ACCESS

#define DMA_CH6_CTRL_TRIG_INCR_READ_ACCESS "RW"

◆ DMA_CH6_CTRL_TRIG_INCR_READ_BITS

#define DMA_CH6_CTRL_TRIG_INCR_READ_BITS _u(0x00000010)

◆ DMA_CH6_CTRL_TRIG_INCR_READ_LSB

#define DMA_CH6_CTRL_TRIG_INCR_READ_LSB _u(4)

◆ DMA_CH6_CTRL_TRIG_INCR_READ_MSB

#define DMA_CH6_CTRL_TRIG_INCR_READ_MSB _u(4)

◆ DMA_CH6_CTRL_TRIG_INCR_READ_RESET

#define DMA_CH6_CTRL_TRIG_INCR_READ_RESET _u(0x0)

◆ DMA_CH6_CTRL_TRIG_INCR_READ_REV_ACCESS

#define DMA_CH6_CTRL_TRIG_INCR_READ_REV_ACCESS "RW"

◆ DMA_CH6_CTRL_TRIG_INCR_READ_REV_BITS

#define DMA_CH6_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020)

◆ DMA_CH6_CTRL_TRIG_INCR_READ_REV_LSB

#define DMA_CH6_CTRL_TRIG_INCR_READ_REV_LSB _u(5)

◆ DMA_CH6_CTRL_TRIG_INCR_READ_REV_MSB

#define DMA_CH6_CTRL_TRIG_INCR_READ_REV_MSB _u(5)

◆ DMA_CH6_CTRL_TRIG_INCR_READ_REV_RESET

#define DMA_CH6_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0)

◆ DMA_CH6_CTRL_TRIG_INCR_WRITE_ACCESS

#define DMA_CH6_CTRL_TRIG_INCR_WRITE_ACCESS "RW"

◆ DMA_CH6_CTRL_TRIG_INCR_WRITE_BITS

#define DMA_CH6_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040)

◆ DMA_CH6_CTRL_TRIG_INCR_WRITE_LSB

#define DMA_CH6_CTRL_TRIG_INCR_WRITE_LSB _u(6)

◆ DMA_CH6_CTRL_TRIG_INCR_WRITE_MSB

#define DMA_CH6_CTRL_TRIG_INCR_WRITE_MSB _u(6)

◆ DMA_CH6_CTRL_TRIG_INCR_WRITE_RESET

#define DMA_CH6_CTRL_TRIG_INCR_WRITE_RESET _u(0x0)

◆ DMA_CH6_CTRL_TRIG_INCR_WRITE_REV_ACCESS

#define DMA_CH6_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW"

◆ DMA_CH6_CTRL_TRIG_INCR_WRITE_REV_BITS

#define DMA_CH6_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080)

◆ DMA_CH6_CTRL_TRIG_INCR_WRITE_REV_LSB

#define DMA_CH6_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7)

◆ DMA_CH6_CTRL_TRIG_INCR_WRITE_REV_MSB

#define DMA_CH6_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7)

◆ DMA_CH6_CTRL_TRIG_INCR_WRITE_REV_RESET

#define DMA_CH6_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0)

◆ DMA_CH6_CTRL_TRIG_IRQ_QUIET_ACCESS

#define DMA_CH6_CTRL_TRIG_IRQ_QUIET_ACCESS "RW"

◆ DMA_CH6_CTRL_TRIG_IRQ_QUIET_BITS

#define DMA_CH6_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000)

◆ DMA_CH6_CTRL_TRIG_IRQ_QUIET_LSB

#define DMA_CH6_CTRL_TRIG_IRQ_QUIET_LSB _u(23)

◆ DMA_CH6_CTRL_TRIG_IRQ_QUIET_MSB

#define DMA_CH6_CTRL_TRIG_IRQ_QUIET_MSB _u(23)

◆ DMA_CH6_CTRL_TRIG_IRQ_QUIET_RESET

#define DMA_CH6_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0)

◆ DMA_CH6_CTRL_TRIG_OFFSET

#define DMA_CH6_CTRL_TRIG_OFFSET _u(0x0000018c)

◆ DMA_CH6_CTRL_TRIG_READ_ERROR_ACCESS

#define DMA_CH6_CTRL_TRIG_READ_ERROR_ACCESS "WC"

◆ DMA_CH6_CTRL_TRIG_READ_ERROR_BITS

#define DMA_CH6_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000)

◆ DMA_CH6_CTRL_TRIG_READ_ERROR_LSB

#define DMA_CH6_CTRL_TRIG_READ_ERROR_LSB _u(30)

◆ DMA_CH6_CTRL_TRIG_READ_ERROR_MSB

#define DMA_CH6_CTRL_TRIG_READ_ERROR_MSB _u(30)

◆ DMA_CH6_CTRL_TRIG_READ_ERROR_RESET

#define DMA_CH6_CTRL_TRIG_READ_ERROR_RESET _u(0x0)

◆ DMA_CH6_CTRL_TRIG_RESET

#define DMA_CH6_CTRL_TRIG_RESET _u(0x00000000)

◆ DMA_CH6_CTRL_TRIG_RING_SEL_ACCESS

#define DMA_CH6_CTRL_TRIG_RING_SEL_ACCESS "RW"

◆ DMA_CH6_CTRL_TRIG_RING_SEL_BITS

#define DMA_CH6_CTRL_TRIG_RING_SEL_BITS _u(0x00001000)

◆ DMA_CH6_CTRL_TRIG_RING_SEL_LSB

#define DMA_CH6_CTRL_TRIG_RING_SEL_LSB _u(12)

◆ DMA_CH6_CTRL_TRIG_RING_SEL_MSB

#define DMA_CH6_CTRL_TRIG_RING_SEL_MSB _u(12)

◆ DMA_CH6_CTRL_TRIG_RING_SEL_RESET

#define DMA_CH6_CTRL_TRIG_RING_SEL_RESET _u(0x0)

◆ DMA_CH6_CTRL_TRIG_RING_SIZE_ACCESS

#define DMA_CH6_CTRL_TRIG_RING_SIZE_ACCESS "RW"

◆ DMA_CH6_CTRL_TRIG_RING_SIZE_BITS

#define DMA_CH6_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00)

◆ DMA_CH6_CTRL_TRIG_RING_SIZE_LSB

#define DMA_CH6_CTRL_TRIG_RING_SIZE_LSB _u(8)

◆ DMA_CH6_CTRL_TRIG_RING_SIZE_MSB

#define DMA_CH6_CTRL_TRIG_RING_SIZE_MSB _u(11)

◆ DMA_CH6_CTRL_TRIG_RING_SIZE_RESET

#define DMA_CH6_CTRL_TRIG_RING_SIZE_RESET _u(0x0)

◆ DMA_CH6_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE

#define DMA_CH6_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0)

◆ DMA_CH6_CTRL_TRIG_SNIFF_EN_ACCESS

#define DMA_CH6_CTRL_TRIG_SNIFF_EN_ACCESS "RW"

◆ DMA_CH6_CTRL_TRIG_SNIFF_EN_BITS

#define DMA_CH6_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000)

◆ DMA_CH6_CTRL_TRIG_SNIFF_EN_LSB

#define DMA_CH6_CTRL_TRIG_SNIFF_EN_LSB _u(25)

◆ DMA_CH6_CTRL_TRIG_SNIFF_EN_MSB

#define DMA_CH6_CTRL_TRIG_SNIFF_EN_MSB _u(25)

◆ DMA_CH6_CTRL_TRIG_SNIFF_EN_RESET

#define DMA_CH6_CTRL_TRIG_SNIFF_EN_RESET _u(0x0)

◆ DMA_CH6_CTRL_TRIG_TREQ_SEL_ACCESS

#define DMA_CH6_CTRL_TRIG_TREQ_SEL_ACCESS "RW"

◆ DMA_CH6_CTRL_TRIG_TREQ_SEL_BITS

#define DMA_CH6_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000)

◆ DMA_CH6_CTRL_TRIG_TREQ_SEL_LSB

#define DMA_CH6_CTRL_TRIG_TREQ_SEL_LSB _u(17)

◆ DMA_CH6_CTRL_TRIG_TREQ_SEL_MSB

#define DMA_CH6_CTRL_TRIG_TREQ_SEL_MSB _u(22)

◆ DMA_CH6_CTRL_TRIG_TREQ_SEL_RESET

#define DMA_CH6_CTRL_TRIG_TREQ_SEL_RESET _u(0x00)

◆ DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT

#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f)

◆ DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0

#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b)

◆ DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1

#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c)

◆ DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2

#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d)

◆ DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3

#define DMA_CH6_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e)

◆ DMA_CH6_CTRL_TRIG_WRITE_ERROR_ACCESS

#define DMA_CH6_CTRL_TRIG_WRITE_ERROR_ACCESS "WC"

◆ DMA_CH6_CTRL_TRIG_WRITE_ERROR_BITS

#define DMA_CH6_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000)

◆ DMA_CH6_CTRL_TRIG_WRITE_ERROR_LSB

#define DMA_CH6_CTRL_TRIG_WRITE_ERROR_LSB _u(29)

◆ DMA_CH6_CTRL_TRIG_WRITE_ERROR_MSB

#define DMA_CH6_CTRL_TRIG_WRITE_ERROR_MSB _u(29)

◆ DMA_CH6_CTRL_TRIG_WRITE_ERROR_RESET

#define DMA_CH6_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0)

◆ DMA_CH6_DBG_CTDREQ_ACCESS

#define DMA_CH6_DBG_CTDREQ_ACCESS "WC"

◆ DMA_CH6_DBG_CTDREQ_BITS

#define DMA_CH6_DBG_CTDREQ_BITS _u(0x0000003f)

◆ DMA_CH6_DBG_CTDREQ_LSB

#define DMA_CH6_DBG_CTDREQ_LSB _u(0)

◆ DMA_CH6_DBG_CTDREQ_MSB

#define DMA_CH6_DBG_CTDREQ_MSB _u(5)

◆ DMA_CH6_DBG_CTDREQ_OFFSET

#define DMA_CH6_DBG_CTDREQ_OFFSET _u(0x00000980)

◆ DMA_CH6_DBG_CTDREQ_RESET

#define DMA_CH6_DBG_CTDREQ_RESET _u(0x00000000)

◆ DMA_CH6_DBG_TCR_ACCESS

#define DMA_CH6_DBG_TCR_ACCESS "RO"

◆ DMA_CH6_DBG_TCR_BITS

#define DMA_CH6_DBG_TCR_BITS _u(0xffffffff)

◆ DMA_CH6_DBG_TCR_LSB

#define DMA_CH6_DBG_TCR_LSB _u(0)

◆ DMA_CH6_DBG_TCR_MSB

#define DMA_CH6_DBG_TCR_MSB _u(31)

◆ DMA_CH6_DBG_TCR_OFFSET

#define DMA_CH6_DBG_TCR_OFFSET _u(0x00000984)

◆ DMA_CH6_DBG_TCR_RESET

#define DMA_CH6_DBG_TCR_RESET _u(0x00000000)

◆ DMA_CH6_READ_ADDR_ACCESS

#define DMA_CH6_READ_ADDR_ACCESS "RW"

◆ DMA_CH6_READ_ADDR_BITS

#define DMA_CH6_READ_ADDR_BITS _u(0xffffffff)

◆ DMA_CH6_READ_ADDR_LSB

#define DMA_CH6_READ_ADDR_LSB _u(0)

◆ DMA_CH6_READ_ADDR_MSB

#define DMA_CH6_READ_ADDR_MSB _u(31)

◆ DMA_CH6_READ_ADDR_OFFSET

#define DMA_CH6_READ_ADDR_OFFSET _u(0x00000180)

◆ DMA_CH6_READ_ADDR_RESET

#define DMA_CH6_READ_ADDR_RESET _u(0x00000000)

◆ DMA_CH6_TRANS_COUNT_BITS

#define DMA_CH6_TRANS_COUNT_BITS _u(0xffffffff)

◆ DMA_CH6_TRANS_COUNT_COUNT_ACCESS

#define DMA_CH6_TRANS_COUNT_COUNT_ACCESS "RW"

◆ DMA_CH6_TRANS_COUNT_COUNT_BITS

#define DMA_CH6_TRANS_COUNT_COUNT_BITS _u(0x0fffffff)

◆ DMA_CH6_TRANS_COUNT_COUNT_LSB

#define DMA_CH6_TRANS_COUNT_COUNT_LSB _u(0)

◆ DMA_CH6_TRANS_COUNT_COUNT_MSB

#define DMA_CH6_TRANS_COUNT_COUNT_MSB _u(27)

◆ DMA_CH6_TRANS_COUNT_COUNT_RESET

#define DMA_CH6_TRANS_COUNT_COUNT_RESET _u(0x0000000)

◆ DMA_CH6_TRANS_COUNT_MODE_ACCESS

#define DMA_CH6_TRANS_COUNT_MODE_ACCESS "RW"

◆ DMA_CH6_TRANS_COUNT_MODE_BITS

#define DMA_CH6_TRANS_COUNT_MODE_BITS _u(0xf0000000)

◆ DMA_CH6_TRANS_COUNT_MODE_LSB

#define DMA_CH6_TRANS_COUNT_MODE_LSB _u(28)

◆ DMA_CH6_TRANS_COUNT_MODE_MSB

#define DMA_CH6_TRANS_COUNT_MODE_MSB _u(31)

◆ DMA_CH6_TRANS_COUNT_MODE_RESET

#define DMA_CH6_TRANS_COUNT_MODE_RESET _u(0x0)

◆ DMA_CH6_TRANS_COUNT_MODE_VALUE_ENDLESS

#define DMA_CH6_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf)

◆ DMA_CH6_TRANS_COUNT_MODE_VALUE_NORMAL

#define DMA_CH6_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0)

◆ DMA_CH6_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF

#define DMA_CH6_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1)

◆ DMA_CH6_TRANS_COUNT_OFFSET

#define DMA_CH6_TRANS_COUNT_OFFSET _u(0x00000188)

◆ DMA_CH6_TRANS_COUNT_RESET

#define DMA_CH6_TRANS_COUNT_RESET _u(0x00000000)

◆ DMA_CH6_WRITE_ADDR_ACCESS

#define DMA_CH6_WRITE_ADDR_ACCESS "RW"

◆ DMA_CH6_WRITE_ADDR_BITS

#define DMA_CH6_WRITE_ADDR_BITS _u(0xffffffff)

◆ DMA_CH6_WRITE_ADDR_LSB

#define DMA_CH6_WRITE_ADDR_LSB _u(0)

◆ DMA_CH6_WRITE_ADDR_MSB

#define DMA_CH6_WRITE_ADDR_MSB _u(31)

◆ DMA_CH6_WRITE_ADDR_OFFSET

#define DMA_CH6_WRITE_ADDR_OFFSET _u(0x00000184)

◆ DMA_CH6_WRITE_ADDR_RESET

#define DMA_CH6_WRITE_ADDR_RESET _u(0x00000000)

◆ DMA_CH7_AL1_CTRL_ACCESS

#define DMA_CH7_AL1_CTRL_ACCESS "RW"

◆ DMA_CH7_AL1_CTRL_BITS

#define DMA_CH7_AL1_CTRL_BITS _u(0xffffffff)

◆ DMA_CH7_AL1_CTRL_LSB

#define DMA_CH7_AL1_CTRL_LSB _u(0)

◆ DMA_CH7_AL1_CTRL_MSB

#define DMA_CH7_AL1_CTRL_MSB _u(31)

◆ DMA_CH7_AL1_CTRL_OFFSET

#define DMA_CH7_AL1_CTRL_OFFSET _u(0x000001d0)

◆ DMA_CH7_AL1_CTRL_RESET

#define DMA_CH7_AL1_CTRL_RESET "-"

◆ DMA_CH7_AL1_READ_ADDR_ACCESS

#define DMA_CH7_AL1_READ_ADDR_ACCESS "RW"

◆ DMA_CH7_AL1_READ_ADDR_BITS

#define DMA_CH7_AL1_READ_ADDR_BITS _u(0xffffffff)

◆ DMA_CH7_AL1_READ_ADDR_LSB

#define DMA_CH7_AL1_READ_ADDR_LSB _u(0)

◆ DMA_CH7_AL1_READ_ADDR_MSB

#define DMA_CH7_AL1_READ_ADDR_MSB _u(31)

◆ DMA_CH7_AL1_READ_ADDR_OFFSET

#define DMA_CH7_AL1_READ_ADDR_OFFSET _u(0x000001d4)

◆ DMA_CH7_AL1_READ_ADDR_RESET

#define DMA_CH7_AL1_READ_ADDR_RESET "-"

◆ DMA_CH7_AL1_TRANS_COUNT_TRIG_ACCESS

#define DMA_CH7_AL1_TRANS_COUNT_TRIG_ACCESS "RW"

◆ DMA_CH7_AL1_TRANS_COUNT_TRIG_BITS

#define DMA_CH7_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff)

◆ DMA_CH7_AL1_TRANS_COUNT_TRIG_LSB

#define DMA_CH7_AL1_TRANS_COUNT_TRIG_LSB _u(0)

◆ DMA_CH7_AL1_TRANS_COUNT_TRIG_MSB

#define DMA_CH7_AL1_TRANS_COUNT_TRIG_MSB _u(31)

◆ DMA_CH7_AL1_TRANS_COUNT_TRIG_OFFSET

#define DMA_CH7_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x000001dc)

◆ DMA_CH7_AL1_TRANS_COUNT_TRIG_RESET

#define DMA_CH7_AL1_TRANS_COUNT_TRIG_RESET "-"

◆ DMA_CH7_AL1_WRITE_ADDR_ACCESS

#define DMA_CH7_AL1_WRITE_ADDR_ACCESS "RW"

◆ DMA_CH7_AL1_WRITE_ADDR_BITS

#define DMA_CH7_AL1_WRITE_ADDR_BITS _u(0xffffffff)

◆ DMA_CH7_AL1_WRITE_ADDR_LSB

#define DMA_CH7_AL1_WRITE_ADDR_LSB _u(0)

◆ DMA_CH7_AL1_WRITE_ADDR_MSB

#define DMA_CH7_AL1_WRITE_ADDR_MSB _u(31)

◆ DMA_CH7_AL1_WRITE_ADDR_OFFSET

#define DMA_CH7_AL1_WRITE_ADDR_OFFSET _u(0x000001d8)

◆ DMA_CH7_AL1_WRITE_ADDR_RESET

#define DMA_CH7_AL1_WRITE_ADDR_RESET "-"

◆ DMA_CH7_AL2_CTRL_ACCESS

#define DMA_CH7_AL2_CTRL_ACCESS "RW"

◆ DMA_CH7_AL2_CTRL_BITS

#define DMA_CH7_AL2_CTRL_BITS _u(0xffffffff)

◆ DMA_CH7_AL2_CTRL_LSB

#define DMA_CH7_AL2_CTRL_LSB _u(0)

◆ DMA_CH7_AL2_CTRL_MSB

#define DMA_CH7_AL2_CTRL_MSB _u(31)

◆ DMA_CH7_AL2_CTRL_OFFSET

#define DMA_CH7_AL2_CTRL_OFFSET _u(0x000001e0)

◆ DMA_CH7_AL2_CTRL_RESET

#define DMA_CH7_AL2_CTRL_RESET "-"

◆ DMA_CH7_AL2_READ_ADDR_ACCESS

#define DMA_CH7_AL2_READ_ADDR_ACCESS "RW"

◆ DMA_CH7_AL2_READ_ADDR_BITS

#define DMA_CH7_AL2_READ_ADDR_BITS _u(0xffffffff)

◆ DMA_CH7_AL2_READ_ADDR_LSB

#define DMA_CH7_AL2_READ_ADDR_LSB _u(0)

◆ DMA_CH7_AL2_READ_ADDR_MSB

#define DMA_CH7_AL2_READ_ADDR_MSB _u(31)

◆ DMA_CH7_AL2_READ_ADDR_OFFSET

#define DMA_CH7_AL2_READ_ADDR_OFFSET _u(0x000001e8)

◆ DMA_CH7_AL2_READ_ADDR_RESET

#define DMA_CH7_AL2_READ_ADDR_RESET "-"

◆ DMA_CH7_AL2_TRANS_COUNT_ACCESS

#define DMA_CH7_AL2_TRANS_COUNT_ACCESS "RW"

◆ DMA_CH7_AL2_TRANS_COUNT_BITS

#define DMA_CH7_AL2_TRANS_COUNT_BITS _u(0xffffffff)

◆ DMA_CH7_AL2_TRANS_COUNT_LSB

#define DMA_CH7_AL2_TRANS_COUNT_LSB _u(0)

◆ DMA_CH7_AL2_TRANS_COUNT_MSB

#define DMA_CH7_AL2_TRANS_COUNT_MSB _u(31)

◆ DMA_CH7_AL2_TRANS_COUNT_OFFSET

#define DMA_CH7_AL2_TRANS_COUNT_OFFSET _u(0x000001e4)

◆ DMA_CH7_AL2_TRANS_COUNT_RESET

#define DMA_CH7_AL2_TRANS_COUNT_RESET "-"

◆ DMA_CH7_AL2_WRITE_ADDR_TRIG_ACCESS

#define DMA_CH7_AL2_WRITE_ADDR_TRIG_ACCESS "RW"

◆ DMA_CH7_AL2_WRITE_ADDR_TRIG_BITS

#define DMA_CH7_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff)

◆ DMA_CH7_AL2_WRITE_ADDR_TRIG_LSB

#define DMA_CH7_AL2_WRITE_ADDR_TRIG_LSB _u(0)

◆ DMA_CH7_AL2_WRITE_ADDR_TRIG_MSB

#define DMA_CH7_AL2_WRITE_ADDR_TRIG_MSB _u(31)

◆ DMA_CH7_AL2_WRITE_ADDR_TRIG_OFFSET

#define DMA_CH7_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x000001ec)

◆ DMA_CH7_AL2_WRITE_ADDR_TRIG_RESET

#define DMA_CH7_AL2_WRITE_ADDR_TRIG_RESET "-"

◆ DMA_CH7_AL3_CTRL_ACCESS

#define DMA_CH7_AL3_CTRL_ACCESS "RW"

◆ DMA_CH7_AL3_CTRL_BITS

#define DMA_CH7_AL3_CTRL_BITS _u(0xffffffff)

◆ DMA_CH7_AL3_CTRL_LSB

#define DMA_CH7_AL3_CTRL_LSB _u(0)

◆ DMA_CH7_AL3_CTRL_MSB

#define DMA_CH7_AL3_CTRL_MSB _u(31)

◆ DMA_CH7_AL3_CTRL_OFFSET

#define DMA_CH7_AL3_CTRL_OFFSET _u(0x000001f0)

◆ DMA_CH7_AL3_CTRL_RESET

#define DMA_CH7_AL3_CTRL_RESET "-"

◆ DMA_CH7_AL3_READ_ADDR_TRIG_ACCESS

#define DMA_CH7_AL3_READ_ADDR_TRIG_ACCESS "RW"

◆ DMA_CH7_AL3_READ_ADDR_TRIG_BITS

#define DMA_CH7_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff)

◆ DMA_CH7_AL3_READ_ADDR_TRIG_LSB

#define DMA_CH7_AL3_READ_ADDR_TRIG_LSB _u(0)

◆ DMA_CH7_AL3_READ_ADDR_TRIG_MSB

#define DMA_CH7_AL3_READ_ADDR_TRIG_MSB _u(31)

◆ DMA_CH7_AL3_READ_ADDR_TRIG_OFFSET

#define DMA_CH7_AL3_READ_ADDR_TRIG_OFFSET _u(0x000001fc)

◆ DMA_CH7_AL3_READ_ADDR_TRIG_RESET

#define DMA_CH7_AL3_READ_ADDR_TRIG_RESET "-"

◆ DMA_CH7_AL3_TRANS_COUNT_ACCESS

#define DMA_CH7_AL3_TRANS_COUNT_ACCESS "RW"

◆ DMA_CH7_AL3_TRANS_COUNT_BITS

#define DMA_CH7_AL3_TRANS_COUNT_BITS _u(0xffffffff)

◆ DMA_CH7_AL3_TRANS_COUNT_LSB

#define DMA_CH7_AL3_TRANS_COUNT_LSB _u(0)

◆ DMA_CH7_AL3_TRANS_COUNT_MSB

#define DMA_CH7_AL3_TRANS_COUNT_MSB _u(31)

◆ DMA_CH7_AL3_TRANS_COUNT_OFFSET

#define DMA_CH7_AL3_TRANS_COUNT_OFFSET _u(0x000001f8)

◆ DMA_CH7_AL3_TRANS_COUNT_RESET

#define DMA_CH7_AL3_TRANS_COUNT_RESET "-"

◆ DMA_CH7_AL3_WRITE_ADDR_ACCESS

#define DMA_CH7_AL3_WRITE_ADDR_ACCESS "RW"

◆ DMA_CH7_AL3_WRITE_ADDR_BITS

#define DMA_CH7_AL3_WRITE_ADDR_BITS _u(0xffffffff)

◆ DMA_CH7_AL3_WRITE_ADDR_LSB

#define DMA_CH7_AL3_WRITE_ADDR_LSB _u(0)

◆ DMA_CH7_AL3_WRITE_ADDR_MSB

#define DMA_CH7_AL3_WRITE_ADDR_MSB _u(31)

◆ DMA_CH7_AL3_WRITE_ADDR_OFFSET

#define DMA_CH7_AL3_WRITE_ADDR_OFFSET _u(0x000001f4)

◆ DMA_CH7_AL3_WRITE_ADDR_RESET

#define DMA_CH7_AL3_WRITE_ADDR_RESET "-"

◆ DMA_CH7_CTRL_TRIG_AHB_ERROR_ACCESS

#define DMA_CH7_CTRL_TRIG_AHB_ERROR_ACCESS "RO"

◆ DMA_CH7_CTRL_TRIG_AHB_ERROR_BITS

#define DMA_CH7_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000)

◆ DMA_CH7_CTRL_TRIG_AHB_ERROR_LSB

#define DMA_CH7_CTRL_TRIG_AHB_ERROR_LSB _u(31)

◆ DMA_CH7_CTRL_TRIG_AHB_ERROR_MSB

#define DMA_CH7_CTRL_TRIG_AHB_ERROR_MSB _u(31)

◆ DMA_CH7_CTRL_TRIG_AHB_ERROR_RESET

#define DMA_CH7_CTRL_TRIG_AHB_ERROR_RESET _u(0x0)

◆ DMA_CH7_CTRL_TRIG_BITS

#define DMA_CH7_CTRL_TRIG_BITS _u(0xe7ffffff)

◆ DMA_CH7_CTRL_TRIG_BSWAP_ACCESS

#define DMA_CH7_CTRL_TRIG_BSWAP_ACCESS "RW"

◆ DMA_CH7_CTRL_TRIG_BSWAP_BITS

#define DMA_CH7_CTRL_TRIG_BSWAP_BITS _u(0x01000000)

◆ DMA_CH7_CTRL_TRIG_BSWAP_LSB

#define DMA_CH7_CTRL_TRIG_BSWAP_LSB _u(24)

◆ DMA_CH7_CTRL_TRIG_BSWAP_MSB

#define DMA_CH7_CTRL_TRIG_BSWAP_MSB _u(24)

◆ DMA_CH7_CTRL_TRIG_BSWAP_RESET

#define DMA_CH7_CTRL_TRIG_BSWAP_RESET _u(0x0)

◆ DMA_CH7_CTRL_TRIG_BUSY_ACCESS

#define DMA_CH7_CTRL_TRIG_BUSY_ACCESS "RO"

◆ DMA_CH7_CTRL_TRIG_BUSY_BITS

#define DMA_CH7_CTRL_TRIG_BUSY_BITS _u(0x04000000)

◆ DMA_CH7_CTRL_TRIG_BUSY_LSB

#define DMA_CH7_CTRL_TRIG_BUSY_LSB _u(26)

◆ DMA_CH7_CTRL_TRIG_BUSY_MSB

#define DMA_CH7_CTRL_TRIG_BUSY_MSB _u(26)

◆ DMA_CH7_CTRL_TRIG_BUSY_RESET

#define DMA_CH7_CTRL_TRIG_BUSY_RESET _u(0x0)

◆ DMA_CH7_CTRL_TRIG_CHAIN_TO_ACCESS

#define DMA_CH7_CTRL_TRIG_CHAIN_TO_ACCESS "RW"

◆ DMA_CH7_CTRL_TRIG_CHAIN_TO_BITS

#define DMA_CH7_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000)

◆ DMA_CH7_CTRL_TRIG_CHAIN_TO_LSB

#define DMA_CH7_CTRL_TRIG_CHAIN_TO_LSB _u(13)

◆ DMA_CH7_CTRL_TRIG_CHAIN_TO_MSB

#define DMA_CH7_CTRL_TRIG_CHAIN_TO_MSB _u(16)

◆ DMA_CH7_CTRL_TRIG_CHAIN_TO_RESET

#define DMA_CH7_CTRL_TRIG_CHAIN_TO_RESET _u(0x0)

◆ DMA_CH7_CTRL_TRIG_DATA_SIZE_ACCESS

#define DMA_CH7_CTRL_TRIG_DATA_SIZE_ACCESS "RW"

◆ DMA_CH7_CTRL_TRIG_DATA_SIZE_BITS

#define DMA_CH7_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c)

◆ DMA_CH7_CTRL_TRIG_DATA_SIZE_LSB

#define DMA_CH7_CTRL_TRIG_DATA_SIZE_LSB _u(2)

◆ DMA_CH7_CTRL_TRIG_DATA_SIZE_MSB

#define DMA_CH7_CTRL_TRIG_DATA_SIZE_MSB _u(3)

◆ DMA_CH7_CTRL_TRIG_DATA_SIZE_RESET

#define DMA_CH7_CTRL_TRIG_DATA_SIZE_RESET _u(0x0)

◆ DMA_CH7_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE

#define DMA_CH7_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0)

◆ DMA_CH7_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD

#define DMA_CH7_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1)

◆ DMA_CH7_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD

#define DMA_CH7_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2)

◆ DMA_CH7_CTRL_TRIG_EN_ACCESS

#define DMA_CH7_CTRL_TRIG_EN_ACCESS "RW"

◆ DMA_CH7_CTRL_TRIG_EN_BITS

#define DMA_CH7_CTRL_TRIG_EN_BITS _u(0x00000001)

◆ DMA_CH7_CTRL_TRIG_EN_LSB

#define DMA_CH7_CTRL_TRIG_EN_LSB _u(0)

◆ DMA_CH7_CTRL_TRIG_EN_MSB

#define DMA_CH7_CTRL_TRIG_EN_MSB _u(0)

◆ DMA_CH7_CTRL_TRIG_EN_RESET

#define DMA_CH7_CTRL_TRIG_EN_RESET _u(0x0)

◆ DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_ACCESS

#define DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW"

◆ DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_BITS

#define DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002)

◆ DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_LSB

#define DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1)

◆ DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_MSB

#define DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1)

◆ DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_RESET

#define DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0)

◆ DMA_CH7_CTRL_TRIG_INCR_READ_ACCESS

#define DMA_CH7_CTRL_TRIG_INCR_READ_ACCESS "RW"

◆ DMA_CH7_CTRL_TRIG_INCR_READ_BITS

#define DMA_CH7_CTRL_TRIG_INCR_READ_BITS _u(0x00000010)

◆ DMA_CH7_CTRL_TRIG_INCR_READ_LSB

#define DMA_CH7_CTRL_TRIG_INCR_READ_LSB _u(4)

◆ DMA_CH7_CTRL_TRIG_INCR_READ_MSB

#define DMA_CH7_CTRL_TRIG_INCR_READ_MSB _u(4)

◆ DMA_CH7_CTRL_TRIG_INCR_READ_RESET

#define DMA_CH7_CTRL_TRIG_INCR_READ_RESET _u(0x0)

◆ DMA_CH7_CTRL_TRIG_INCR_READ_REV_ACCESS

#define DMA_CH7_CTRL_TRIG_INCR_READ_REV_ACCESS "RW"

◆ DMA_CH7_CTRL_TRIG_INCR_READ_REV_BITS

#define DMA_CH7_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020)

◆ DMA_CH7_CTRL_TRIG_INCR_READ_REV_LSB

#define DMA_CH7_CTRL_TRIG_INCR_READ_REV_LSB _u(5)

◆ DMA_CH7_CTRL_TRIG_INCR_READ_REV_MSB

#define DMA_CH7_CTRL_TRIG_INCR_READ_REV_MSB _u(5)

◆ DMA_CH7_CTRL_TRIG_INCR_READ_REV_RESET

#define DMA_CH7_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0)

◆ DMA_CH7_CTRL_TRIG_INCR_WRITE_ACCESS

#define DMA_CH7_CTRL_TRIG_INCR_WRITE_ACCESS "RW"

◆ DMA_CH7_CTRL_TRIG_INCR_WRITE_BITS

#define DMA_CH7_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040)

◆ DMA_CH7_CTRL_TRIG_INCR_WRITE_LSB

#define DMA_CH7_CTRL_TRIG_INCR_WRITE_LSB _u(6)

◆ DMA_CH7_CTRL_TRIG_INCR_WRITE_MSB

#define DMA_CH7_CTRL_TRIG_INCR_WRITE_MSB _u(6)

◆ DMA_CH7_CTRL_TRIG_INCR_WRITE_RESET

#define DMA_CH7_CTRL_TRIG_INCR_WRITE_RESET _u(0x0)

◆ DMA_CH7_CTRL_TRIG_INCR_WRITE_REV_ACCESS

#define DMA_CH7_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW"

◆ DMA_CH7_CTRL_TRIG_INCR_WRITE_REV_BITS

#define DMA_CH7_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080)

◆ DMA_CH7_CTRL_TRIG_INCR_WRITE_REV_LSB

#define DMA_CH7_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7)

◆ DMA_CH7_CTRL_TRIG_INCR_WRITE_REV_MSB

#define DMA_CH7_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7)

◆ DMA_CH7_CTRL_TRIG_INCR_WRITE_REV_RESET

#define DMA_CH7_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0)

◆ DMA_CH7_CTRL_TRIG_IRQ_QUIET_ACCESS

#define DMA_CH7_CTRL_TRIG_IRQ_QUIET_ACCESS "RW"

◆ DMA_CH7_CTRL_TRIG_IRQ_QUIET_BITS

#define DMA_CH7_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000)

◆ DMA_CH7_CTRL_TRIG_IRQ_QUIET_LSB

#define DMA_CH7_CTRL_TRIG_IRQ_QUIET_LSB _u(23)

◆ DMA_CH7_CTRL_TRIG_IRQ_QUIET_MSB

#define DMA_CH7_CTRL_TRIG_IRQ_QUIET_MSB _u(23)

◆ DMA_CH7_CTRL_TRIG_IRQ_QUIET_RESET

#define DMA_CH7_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0)

◆ DMA_CH7_CTRL_TRIG_OFFSET

#define DMA_CH7_CTRL_TRIG_OFFSET _u(0x000001cc)

◆ DMA_CH7_CTRL_TRIG_READ_ERROR_ACCESS

#define DMA_CH7_CTRL_TRIG_READ_ERROR_ACCESS "WC"

◆ DMA_CH7_CTRL_TRIG_READ_ERROR_BITS

#define DMA_CH7_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000)

◆ DMA_CH7_CTRL_TRIG_READ_ERROR_LSB

#define DMA_CH7_CTRL_TRIG_READ_ERROR_LSB _u(30)

◆ DMA_CH7_CTRL_TRIG_READ_ERROR_MSB

#define DMA_CH7_CTRL_TRIG_READ_ERROR_MSB _u(30)

◆ DMA_CH7_CTRL_TRIG_READ_ERROR_RESET

#define DMA_CH7_CTRL_TRIG_READ_ERROR_RESET _u(0x0)

◆ DMA_CH7_CTRL_TRIG_RESET

#define DMA_CH7_CTRL_TRIG_RESET _u(0x00000000)

◆ DMA_CH7_CTRL_TRIG_RING_SEL_ACCESS

#define DMA_CH7_CTRL_TRIG_RING_SEL_ACCESS "RW"

◆ DMA_CH7_CTRL_TRIG_RING_SEL_BITS

#define DMA_CH7_CTRL_TRIG_RING_SEL_BITS _u(0x00001000)

◆ DMA_CH7_CTRL_TRIG_RING_SEL_LSB

#define DMA_CH7_CTRL_TRIG_RING_SEL_LSB _u(12)

◆ DMA_CH7_CTRL_TRIG_RING_SEL_MSB

#define DMA_CH7_CTRL_TRIG_RING_SEL_MSB _u(12)

◆ DMA_CH7_CTRL_TRIG_RING_SEL_RESET

#define DMA_CH7_CTRL_TRIG_RING_SEL_RESET _u(0x0)

◆ DMA_CH7_CTRL_TRIG_RING_SIZE_ACCESS

#define DMA_CH7_CTRL_TRIG_RING_SIZE_ACCESS "RW"

◆ DMA_CH7_CTRL_TRIG_RING_SIZE_BITS

#define DMA_CH7_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00)

◆ DMA_CH7_CTRL_TRIG_RING_SIZE_LSB

#define DMA_CH7_CTRL_TRIG_RING_SIZE_LSB _u(8)

◆ DMA_CH7_CTRL_TRIG_RING_SIZE_MSB

#define DMA_CH7_CTRL_TRIG_RING_SIZE_MSB _u(11)

◆ DMA_CH7_CTRL_TRIG_RING_SIZE_RESET

#define DMA_CH7_CTRL_TRIG_RING_SIZE_RESET _u(0x0)

◆ DMA_CH7_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE

#define DMA_CH7_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0)

◆ DMA_CH7_CTRL_TRIG_SNIFF_EN_ACCESS

#define DMA_CH7_CTRL_TRIG_SNIFF_EN_ACCESS "RW"

◆ DMA_CH7_CTRL_TRIG_SNIFF_EN_BITS

#define DMA_CH7_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000)

◆ DMA_CH7_CTRL_TRIG_SNIFF_EN_LSB

#define DMA_CH7_CTRL_TRIG_SNIFF_EN_LSB _u(25)

◆ DMA_CH7_CTRL_TRIG_SNIFF_EN_MSB

#define DMA_CH7_CTRL_TRIG_SNIFF_EN_MSB _u(25)

◆ DMA_CH7_CTRL_TRIG_SNIFF_EN_RESET

#define DMA_CH7_CTRL_TRIG_SNIFF_EN_RESET _u(0x0)

◆ DMA_CH7_CTRL_TRIG_TREQ_SEL_ACCESS

#define DMA_CH7_CTRL_TRIG_TREQ_SEL_ACCESS "RW"

◆ DMA_CH7_CTRL_TRIG_TREQ_SEL_BITS

#define DMA_CH7_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000)

◆ DMA_CH7_CTRL_TRIG_TREQ_SEL_LSB

#define DMA_CH7_CTRL_TRIG_TREQ_SEL_LSB _u(17)

◆ DMA_CH7_CTRL_TRIG_TREQ_SEL_MSB

#define DMA_CH7_CTRL_TRIG_TREQ_SEL_MSB _u(22)

◆ DMA_CH7_CTRL_TRIG_TREQ_SEL_RESET

#define DMA_CH7_CTRL_TRIG_TREQ_SEL_RESET _u(0x00)

◆ DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT

#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f)

◆ DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0

#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b)

◆ DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1

#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c)

◆ DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2

#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d)

◆ DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3

#define DMA_CH7_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e)

◆ DMA_CH7_CTRL_TRIG_WRITE_ERROR_ACCESS

#define DMA_CH7_CTRL_TRIG_WRITE_ERROR_ACCESS "WC"

◆ DMA_CH7_CTRL_TRIG_WRITE_ERROR_BITS

#define DMA_CH7_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000)

◆ DMA_CH7_CTRL_TRIG_WRITE_ERROR_LSB

#define DMA_CH7_CTRL_TRIG_WRITE_ERROR_LSB _u(29)

◆ DMA_CH7_CTRL_TRIG_WRITE_ERROR_MSB

#define DMA_CH7_CTRL_TRIG_WRITE_ERROR_MSB _u(29)

◆ DMA_CH7_CTRL_TRIG_WRITE_ERROR_RESET

#define DMA_CH7_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0)

◆ DMA_CH7_DBG_CTDREQ_ACCESS

#define DMA_CH7_DBG_CTDREQ_ACCESS "WC"

◆ DMA_CH7_DBG_CTDREQ_BITS

#define DMA_CH7_DBG_CTDREQ_BITS _u(0x0000003f)

◆ DMA_CH7_DBG_CTDREQ_LSB

#define DMA_CH7_DBG_CTDREQ_LSB _u(0)

◆ DMA_CH7_DBG_CTDREQ_MSB

#define DMA_CH7_DBG_CTDREQ_MSB _u(5)

◆ DMA_CH7_DBG_CTDREQ_OFFSET

#define DMA_CH7_DBG_CTDREQ_OFFSET _u(0x000009c0)

◆ DMA_CH7_DBG_CTDREQ_RESET

#define DMA_CH7_DBG_CTDREQ_RESET _u(0x00000000)

◆ DMA_CH7_DBG_TCR_ACCESS

#define DMA_CH7_DBG_TCR_ACCESS "RO"

◆ DMA_CH7_DBG_TCR_BITS

#define DMA_CH7_DBG_TCR_BITS _u(0xffffffff)

◆ DMA_CH7_DBG_TCR_LSB

#define DMA_CH7_DBG_TCR_LSB _u(0)

◆ DMA_CH7_DBG_TCR_MSB

#define DMA_CH7_DBG_TCR_MSB _u(31)

◆ DMA_CH7_DBG_TCR_OFFSET

#define DMA_CH7_DBG_TCR_OFFSET _u(0x000009c4)

◆ DMA_CH7_DBG_TCR_RESET

#define DMA_CH7_DBG_TCR_RESET _u(0x00000000)

◆ DMA_CH7_READ_ADDR_ACCESS

#define DMA_CH7_READ_ADDR_ACCESS "RW"

◆ DMA_CH7_READ_ADDR_BITS

#define DMA_CH7_READ_ADDR_BITS _u(0xffffffff)

◆ DMA_CH7_READ_ADDR_LSB

#define DMA_CH7_READ_ADDR_LSB _u(0)

◆ DMA_CH7_READ_ADDR_MSB

#define DMA_CH7_READ_ADDR_MSB _u(31)

◆ DMA_CH7_READ_ADDR_OFFSET

#define DMA_CH7_READ_ADDR_OFFSET _u(0x000001c0)

◆ DMA_CH7_READ_ADDR_RESET

#define DMA_CH7_READ_ADDR_RESET _u(0x00000000)

◆ DMA_CH7_TRANS_COUNT_BITS

#define DMA_CH7_TRANS_COUNT_BITS _u(0xffffffff)

◆ DMA_CH7_TRANS_COUNT_COUNT_ACCESS

#define DMA_CH7_TRANS_COUNT_COUNT_ACCESS "RW"

◆ DMA_CH7_TRANS_COUNT_COUNT_BITS

#define DMA_CH7_TRANS_COUNT_COUNT_BITS _u(0x0fffffff)

◆ DMA_CH7_TRANS_COUNT_COUNT_LSB

#define DMA_CH7_TRANS_COUNT_COUNT_LSB _u(0)

◆ DMA_CH7_TRANS_COUNT_COUNT_MSB

#define DMA_CH7_TRANS_COUNT_COUNT_MSB _u(27)

◆ DMA_CH7_TRANS_COUNT_COUNT_RESET

#define DMA_CH7_TRANS_COUNT_COUNT_RESET _u(0x0000000)

◆ DMA_CH7_TRANS_COUNT_MODE_ACCESS

#define DMA_CH7_TRANS_COUNT_MODE_ACCESS "RW"

◆ DMA_CH7_TRANS_COUNT_MODE_BITS

#define DMA_CH7_TRANS_COUNT_MODE_BITS _u(0xf0000000)

◆ DMA_CH7_TRANS_COUNT_MODE_LSB

#define DMA_CH7_TRANS_COUNT_MODE_LSB _u(28)

◆ DMA_CH7_TRANS_COUNT_MODE_MSB

#define DMA_CH7_TRANS_COUNT_MODE_MSB _u(31)

◆ DMA_CH7_TRANS_COUNT_MODE_RESET

#define DMA_CH7_TRANS_COUNT_MODE_RESET _u(0x0)

◆ DMA_CH7_TRANS_COUNT_MODE_VALUE_ENDLESS

#define DMA_CH7_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf)

◆ DMA_CH7_TRANS_COUNT_MODE_VALUE_NORMAL

#define DMA_CH7_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0)

◆ DMA_CH7_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF

#define DMA_CH7_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1)

◆ DMA_CH7_TRANS_COUNT_OFFSET

#define DMA_CH7_TRANS_COUNT_OFFSET _u(0x000001c8)

◆ DMA_CH7_TRANS_COUNT_RESET

#define DMA_CH7_TRANS_COUNT_RESET _u(0x00000000)

◆ DMA_CH7_WRITE_ADDR_ACCESS

#define DMA_CH7_WRITE_ADDR_ACCESS "RW"

◆ DMA_CH7_WRITE_ADDR_BITS

#define DMA_CH7_WRITE_ADDR_BITS _u(0xffffffff)

◆ DMA_CH7_WRITE_ADDR_LSB

#define DMA_CH7_WRITE_ADDR_LSB _u(0)

◆ DMA_CH7_WRITE_ADDR_MSB

#define DMA_CH7_WRITE_ADDR_MSB _u(31)

◆ DMA_CH7_WRITE_ADDR_OFFSET

#define DMA_CH7_WRITE_ADDR_OFFSET _u(0x000001c4)

◆ DMA_CH7_WRITE_ADDR_RESET

#define DMA_CH7_WRITE_ADDR_RESET _u(0x00000000)

◆ DMA_CH8_AL1_CTRL_ACCESS

#define DMA_CH8_AL1_CTRL_ACCESS "RW"

◆ DMA_CH8_AL1_CTRL_BITS

#define DMA_CH8_AL1_CTRL_BITS _u(0xffffffff)

◆ DMA_CH8_AL1_CTRL_LSB

#define DMA_CH8_AL1_CTRL_LSB _u(0)

◆ DMA_CH8_AL1_CTRL_MSB

#define DMA_CH8_AL1_CTRL_MSB _u(31)

◆ DMA_CH8_AL1_CTRL_OFFSET

#define DMA_CH8_AL1_CTRL_OFFSET _u(0x00000210)

◆ DMA_CH8_AL1_CTRL_RESET

#define DMA_CH8_AL1_CTRL_RESET "-"

◆ DMA_CH8_AL1_READ_ADDR_ACCESS

#define DMA_CH8_AL1_READ_ADDR_ACCESS "RW"

◆ DMA_CH8_AL1_READ_ADDR_BITS

#define DMA_CH8_AL1_READ_ADDR_BITS _u(0xffffffff)

◆ DMA_CH8_AL1_READ_ADDR_LSB

#define DMA_CH8_AL1_READ_ADDR_LSB _u(0)

◆ DMA_CH8_AL1_READ_ADDR_MSB

#define DMA_CH8_AL1_READ_ADDR_MSB _u(31)

◆ DMA_CH8_AL1_READ_ADDR_OFFSET

#define DMA_CH8_AL1_READ_ADDR_OFFSET _u(0x00000214)

◆ DMA_CH8_AL1_READ_ADDR_RESET

#define DMA_CH8_AL1_READ_ADDR_RESET "-"

◆ DMA_CH8_AL1_TRANS_COUNT_TRIG_ACCESS

#define DMA_CH8_AL1_TRANS_COUNT_TRIG_ACCESS "RW"

◆ DMA_CH8_AL1_TRANS_COUNT_TRIG_BITS

#define DMA_CH8_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff)

◆ DMA_CH8_AL1_TRANS_COUNT_TRIG_LSB

#define DMA_CH8_AL1_TRANS_COUNT_TRIG_LSB _u(0)

◆ DMA_CH8_AL1_TRANS_COUNT_TRIG_MSB

#define DMA_CH8_AL1_TRANS_COUNT_TRIG_MSB _u(31)

◆ DMA_CH8_AL1_TRANS_COUNT_TRIG_OFFSET

#define DMA_CH8_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000021c)

◆ DMA_CH8_AL1_TRANS_COUNT_TRIG_RESET

#define DMA_CH8_AL1_TRANS_COUNT_TRIG_RESET "-"

◆ DMA_CH8_AL1_WRITE_ADDR_ACCESS

#define DMA_CH8_AL1_WRITE_ADDR_ACCESS "RW"

◆ DMA_CH8_AL1_WRITE_ADDR_BITS

#define DMA_CH8_AL1_WRITE_ADDR_BITS _u(0xffffffff)

◆ DMA_CH8_AL1_WRITE_ADDR_LSB

#define DMA_CH8_AL1_WRITE_ADDR_LSB _u(0)

◆ DMA_CH8_AL1_WRITE_ADDR_MSB

#define DMA_CH8_AL1_WRITE_ADDR_MSB _u(31)

◆ DMA_CH8_AL1_WRITE_ADDR_OFFSET

#define DMA_CH8_AL1_WRITE_ADDR_OFFSET _u(0x00000218)

◆ DMA_CH8_AL1_WRITE_ADDR_RESET

#define DMA_CH8_AL1_WRITE_ADDR_RESET "-"

◆ DMA_CH8_AL2_CTRL_ACCESS

#define DMA_CH8_AL2_CTRL_ACCESS "RW"

◆ DMA_CH8_AL2_CTRL_BITS

#define DMA_CH8_AL2_CTRL_BITS _u(0xffffffff)

◆ DMA_CH8_AL2_CTRL_LSB

#define DMA_CH8_AL2_CTRL_LSB _u(0)

◆ DMA_CH8_AL2_CTRL_MSB

#define DMA_CH8_AL2_CTRL_MSB _u(31)

◆ DMA_CH8_AL2_CTRL_OFFSET

#define DMA_CH8_AL2_CTRL_OFFSET _u(0x00000220)

◆ DMA_CH8_AL2_CTRL_RESET

#define DMA_CH8_AL2_CTRL_RESET "-"

◆ DMA_CH8_AL2_READ_ADDR_ACCESS

#define DMA_CH8_AL2_READ_ADDR_ACCESS "RW"

◆ DMA_CH8_AL2_READ_ADDR_BITS

#define DMA_CH8_AL2_READ_ADDR_BITS _u(0xffffffff)

◆ DMA_CH8_AL2_READ_ADDR_LSB

#define DMA_CH8_AL2_READ_ADDR_LSB _u(0)

◆ DMA_CH8_AL2_READ_ADDR_MSB

#define DMA_CH8_AL2_READ_ADDR_MSB _u(31)

◆ DMA_CH8_AL2_READ_ADDR_OFFSET

#define DMA_CH8_AL2_READ_ADDR_OFFSET _u(0x00000228)

◆ DMA_CH8_AL2_READ_ADDR_RESET

#define DMA_CH8_AL2_READ_ADDR_RESET "-"

◆ DMA_CH8_AL2_TRANS_COUNT_ACCESS

#define DMA_CH8_AL2_TRANS_COUNT_ACCESS "RW"

◆ DMA_CH8_AL2_TRANS_COUNT_BITS

#define DMA_CH8_AL2_TRANS_COUNT_BITS _u(0xffffffff)

◆ DMA_CH8_AL2_TRANS_COUNT_LSB

#define DMA_CH8_AL2_TRANS_COUNT_LSB _u(0)

◆ DMA_CH8_AL2_TRANS_COUNT_MSB

#define DMA_CH8_AL2_TRANS_COUNT_MSB _u(31)

◆ DMA_CH8_AL2_TRANS_COUNT_OFFSET

#define DMA_CH8_AL2_TRANS_COUNT_OFFSET _u(0x00000224)

◆ DMA_CH8_AL2_TRANS_COUNT_RESET

#define DMA_CH8_AL2_TRANS_COUNT_RESET "-"

◆ DMA_CH8_AL2_WRITE_ADDR_TRIG_ACCESS

#define DMA_CH8_AL2_WRITE_ADDR_TRIG_ACCESS "RW"

◆ DMA_CH8_AL2_WRITE_ADDR_TRIG_BITS

#define DMA_CH8_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff)

◆ DMA_CH8_AL2_WRITE_ADDR_TRIG_LSB

#define DMA_CH8_AL2_WRITE_ADDR_TRIG_LSB _u(0)

◆ DMA_CH8_AL2_WRITE_ADDR_TRIG_MSB

#define DMA_CH8_AL2_WRITE_ADDR_TRIG_MSB _u(31)

◆ DMA_CH8_AL2_WRITE_ADDR_TRIG_OFFSET

#define DMA_CH8_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x0000022c)

◆ DMA_CH8_AL2_WRITE_ADDR_TRIG_RESET

#define DMA_CH8_AL2_WRITE_ADDR_TRIG_RESET "-"

◆ DMA_CH8_AL3_CTRL_ACCESS

#define DMA_CH8_AL3_CTRL_ACCESS "RW"

◆ DMA_CH8_AL3_CTRL_BITS

#define DMA_CH8_AL3_CTRL_BITS _u(0xffffffff)

◆ DMA_CH8_AL3_CTRL_LSB

#define DMA_CH8_AL3_CTRL_LSB _u(0)

◆ DMA_CH8_AL3_CTRL_MSB

#define DMA_CH8_AL3_CTRL_MSB _u(31)

◆ DMA_CH8_AL3_CTRL_OFFSET

#define DMA_CH8_AL3_CTRL_OFFSET _u(0x00000230)

◆ DMA_CH8_AL3_CTRL_RESET

#define DMA_CH8_AL3_CTRL_RESET "-"

◆ DMA_CH8_AL3_READ_ADDR_TRIG_ACCESS

#define DMA_CH8_AL3_READ_ADDR_TRIG_ACCESS "RW"

◆ DMA_CH8_AL3_READ_ADDR_TRIG_BITS

#define DMA_CH8_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff)

◆ DMA_CH8_AL3_READ_ADDR_TRIG_LSB

#define DMA_CH8_AL3_READ_ADDR_TRIG_LSB _u(0)

◆ DMA_CH8_AL3_READ_ADDR_TRIG_MSB

#define DMA_CH8_AL3_READ_ADDR_TRIG_MSB _u(31)

◆ DMA_CH8_AL3_READ_ADDR_TRIG_OFFSET

#define DMA_CH8_AL3_READ_ADDR_TRIG_OFFSET _u(0x0000023c)

◆ DMA_CH8_AL3_READ_ADDR_TRIG_RESET

#define DMA_CH8_AL3_READ_ADDR_TRIG_RESET "-"

◆ DMA_CH8_AL3_TRANS_COUNT_ACCESS

#define DMA_CH8_AL3_TRANS_COUNT_ACCESS "RW"

◆ DMA_CH8_AL3_TRANS_COUNT_BITS

#define DMA_CH8_AL3_TRANS_COUNT_BITS _u(0xffffffff)

◆ DMA_CH8_AL3_TRANS_COUNT_LSB

#define DMA_CH8_AL3_TRANS_COUNT_LSB _u(0)

◆ DMA_CH8_AL3_TRANS_COUNT_MSB

#define DMA_CH8_AL3_TRANS_COUNT_MSB _u(31)

◆ DMA_CH8_AL3_TRANS_COUNT_OFFSET

#define DMA_CH8_AL3_TRANS_COUNT_OFFSET _u(0x00000238)

◆ DMA_CH8_AL3_TRANS_COUNT_RESET

#define DMA_CH8_AL3_TRANS_COUNT_RESET "-"

◆ DMA_CH8_AL3_WRITE_ADDR_ACCESS

#define DMA_CH8_AL3_WRITE_ADDR_ACCESS "RW"

◆ DMA_CH8_AL3_WRITE_ADDR_BITS

#define DMA_CH8_AL3_WRITE_ADDR_BITS _u(0xffffffff)

◆ DMA_CH8_AL3_WRITE_ADDR_LSB

#define DMA_CH8_AL3_WRITE_ADDR_LSB _u(0)

◆ DMA_CH8_AL3_WRITE_ADDR_MSB

#define DMA_CH8_AL3_WRITE_ADDR_MSB _u(31)

◆ DMA_CH8_AL3_WRITE_ADDR_OFFSET

#define DMA_CH8_AL3_WRITE_ADDR_OFFSET _u(0x00000234)

◆ DMA_CH8_AL3_WRITE_ADDR_RESET

#define DMA_CH8_AL3_WRITE_ADDR_RESET "-"

◆ DMA_CH8_CTRL_TRIG_AHB_ERROR_ACCESS

#define DMA_CH8_CTRL_TRIG_AHB_ERROR_ACCESS "RO"

◆ DMA_CH8_CTRL_TRIG_AHB_ERROR_BITS

#define DMA_CH8_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000)

◆ DMA_CH8_CTRL_TRIG_AHB_ERROR_LSB

#define DMA_CH8_CTRL_TRIG_AHB_ERROR_LSB _u(31)

◆ DMA_CH8_CTRL_TRIG_AHB_ERROR_MSB

#define DMA_CH8_CTRL_TRIG_AHB_ERROR_MSB _u(31)

◆ DMA_CH8_CTRL_TRIG_AHB_ERROR_RESET

#define DMA_CH8_CTRL_TRIG_AHB_ERROR_RESET _u(0x0)

◆ DMA_CH8_CTRL_TRIG_BITS

#define DMA_CH8_CTRL_TRIG_BITS _u(0xe7ffffff)

◆ DMA_CH8_CTRL_TRIG_BSWAP_ACCESS

#define DMA_CH8_CTRL_TRIG_BSWAP_ACCESS "RW"

◆ DMA_CH8_CTRL_TRIG_BSWAP_BITS

#define DMA_CH8_CTRL_TRIG_BSWAP_BITS _u(0x01000000)

◆ DMA_CH8_CTRL_TRIG_BSWAP_LSB

#define DMA_CH8_CTRL_TRIG_BSWAP_LSB _u(24)

◆ DMA_CH8_CTRL_TRIG_BSWAP_MSB

#define DMA_CH8_CTRL_TRIG_BSWAP_MSB _u(24)

◆ DMA_CH8_CTRL_TRIG_BSWAP_RESET

#define DMA_CH8_CTRL_TRIG_BSWAP_RESET _u(0x0)

◆ DMA_CH8_CTRL_TRIG_BUSY_ACCESS

#define DMA_CH8_CTRL_TRIG_BUSY_ACCESS "RO"

◆ DMA_CH8_CTRL_TRIG_BUSY_BITS

#define DMA_CH8_CTRL_TRIG_BUSY_BITS _u(0x04000000)

◆ DMA_CH8_CTRL_TRIG_BUSY_LSB

#define DMA_CH8_CTRL_TRIG_BUSY_LSB _u(26)

◆ DMA_CH8_CTRL_TRIG_BUSY_MSB

#define DMA_CH8_CTRL_TRIG_BUSY_MSB _u(26)

◆ DMA_CH8_CTRL_TRIG_BUSY_RESET

#define DMA_CH8_CTRL_TRIG_BUSY_RESET _u(0x0)

◆ DMA_CH8_CTRL_TRIG_CHAIN_TO_ACCESS

#define DMA_CH8_CTRL_TRIG_CHAIN_TO_ACCESS "RW"

◆ DMA_CH8_CTRL_TRIG_CHAIN_TO_BITS

#define DMA_CH8_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000)

◆ DMA_CH8_CTRL_TRIG_CHAIN_TO_LSB

#define DMA_CH8_CTRL_TRIG_CHAIN_TO_LSB _u(13)

◆ DMA_CH8_CTRL_TRIG_CHAIN_TO_MSB

#define DMA_CH8_CTRL_TRIG_CHAIN_TO_MSB _u(16)

◆ DMA_CH8_CTRL_TRIG_CHAIN_TO_RESET

#define DMA_CH8_CTRL_TRIG_CHAIN_TO_RESET _u(0x0)

◆ DMA_CH8_CTRL_TRIG_DATA_SIZE_ACCESS

#define DMA_CH8_CTRL_TRIG_DATA_SIZE_ACCESS "RW"

◆ DMA_CH8_CTRL_TRIG_DATA_SIZE_BITS

#define DMA_CH8_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c)

◆ DMA_CH8_CTRL_TRIG_DATA_SIZE_LSB

#define DMA_CH8_CTRL_TRIG_DATA_SIZE_LSB _u(2)

◆ DMA_CH8_CTRL_TRIG_DATA_SIZE_MSB

#define DMA_CH8_CTRL_TRIG_DATA_SIZE_MSB _u(3)

◆ DMA_CH8_CTRL_TRIG_DATA_SIZE_RESET

#define DMA_CH8_CTRL_TRIG_DATA_SIZE_RESET _u(0x0)

◆ DMA_CH8_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE

#define DMA_CH8_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0)

◆ DMA_CH8_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD

#define DMA_CH8_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1)

◆ DMA_CH8_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD

#define DMA_CH8_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2)

◆ DMA_CH8_CTRL_TRIG_EN_ACCESS

#define DMA_CH8_CTRL_TRIG_EN_ACCESS "RW"

◆ DMA_CH8_CTRL_TRIG_EN_BITS

#define DMA_CH8_CTRL_TRIG_EN_BITS _u(0x00000001)

◆ DMA_CH8_CTRL_TRIG_EN_LSB

#define DMA_CH8_CTRL_TRIG_EN_LSB _u(0)

◆ DMA_CH8_CTRL_TRIG_EN_MSB

#define DMA_CH8_CTRL_TRIG_EN_MSB _u(0)

◆ DMA_CH8_CTRL_TRIG_EN_RESET

#define DMA_CH8_CTRL_TRIG_EN_RESET _u(0x0)

◆ DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_ACCESS

#define DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW"

◆ DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_BITS

#define DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002)

◆ DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_LSB

#define DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1)

◆ DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_MSB

#define DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1)

◆ DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_RESET

#define DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0)

◆ DMA_CH8_CTRL_TRIG_INCR_READ_ACCESS

#define DMA_CH8_CTRL_TRIG_INCR_READ_ACCESS "RW"

◆ DMA_CH8_CTRL_TRIG_INCR_READ_BITS

#define DMA_CH8_CTRL_TRIG_INCR_READ_BITS _u(0x00000010)

◆ DMA_CH8_CTRL_TRIG_INCR_READ_LSB

#define DMA_CH8_CTRL_TRIG_INCR_READ_LSB _u(4)

◆ DMA_CH8_CTRL_TRIG_INCR_READ_MSB

#define DMA_CH8_CTRL_TRIG_INCR_READ_MSB _u(4)

◆ DMA_CH8_CTRL_TRIG_INCR_READ_RESET

#define DMA_CH8_CTRL_TRIG_INCR_READ_RESET _u(0x0)

◆ DMA_CH8_CTRL_TRIG_INCR_READ_REV_ACCESS

#define DMA_CH8_CTRL_TRIG_INCR_READ_REV_ACCESS "RW"

◆ DMA_CH8_CTRL_TRIG_INCR_READ_REV_BITS

#define DMA_CH8_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020)

◆ DMA_CH8_CTRL_TRIG_INCR_READ_REV_LSB

#define DMA_CH8_CTRL_TRIG_INCR_READ_REV_LSB _u(5)

◆ DMA_CH8_CTRL_TRIG_INCR_READ_REV_MSB

#define DMA_CH8_CTRL_TRIG_INCR_READ_REV_MSB _u(5)

◆ DMA_CH8_CTRL_TRIG_INCR_READ_REV_RESET

#define DMA_CH8_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0)

◆ DMA_CH8_CTRL_TRIG_INCR_WRITE_ACCESS

#define DMA_CH8_CTRL_TRIG_INCR_WRITE_ACCESS "RW"

◆ DMA_CH8_CTRL_TRIG_INCR_WRITE_BITS

#define DMA_CH8_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040)

◆ DMA_CH8_CTRL_TRIG_INCR_WRITE_LSB

#define DMA_CH8_CTRL_TRIG_INCR_WRITE_LSB _u(6)

◆ DMA_CH8_CTRL_TRIG_INCR_WRITE_MSB

#define DMA_CH8_CTRL_TRIG_INCR_WRITE_MSB _u(6)

◆ DMA_CH8_CTRL_TRIG_INCR_WRITE_RESET

#define DMA_CH8_CTRL_TRIG_INCR_WRITE_RESET _u(0x0)

◆ DMA_CH8_CTRL_TRIG_INCR_WRITE_REV_ACCESS

#define DMA_CH8_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW"

◆ DMA_CH8_CTRL_TRIG_INCR_WRITE_REV_BITS

#define DMA_CH8_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080)

◆ DMA_CH8_CTRL_TRIG_INCR_WRITE_REV_LSB

#define DMA_CH8_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7)

◆ DMA_CH8_CTRL_TRIG_INCR_WRITE_REV_MSB

#define DMA_CH8_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7)

◆ DMA_CH8_CTRL_TRIG_INCR_WRITE_REV_RESET

#define DMA_CH8_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0)

◆ DMA_CH8_CTRL_TRIG_IRQ_QUIET_ACCESS

#define DMA_CH8_CTRL_TRIG_IRQ_QUIET_ACCESS "RW"

◆ DMA_CH8_CTRL_TRIG_IRQ_QUIET_BITS

#define DMA_CH8_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000)

◆ DMA_CH8_CTRL_TRIG_IRQ_QUIET_LSB

#define DMA_CH8_CTRL_TRIG_IRQ_QUIET_LSB _u(23)

◆ DMA_CH8_CTRL_TRIG_IRQ_QUIET_MSB

#define DMA_CH8_CTRL_TRIG_IRQ_QUIET_MSB _u(23)

◆ DMA_CH8_CTRL_TRIG_IRQ_QUIET_RESET

#define DMA_CH8_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0)

◆ DMA_CH8_CTRL_TRIG_OFFSET

#define DMA_CH8_CTRL_TRIG_OFFSET _u(0x0000020c)

◆ DMA_CH8_CTRL_TRIG_READ_ERROR_ACCESS

#define DMA_CH8_CTRL_TRIG_READ_ERROR_ACCESS "WC"

◆ DMA_CH8_CTRL_TRIG_READ_ERROR_BITS

#define DMA_CH8_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000)

◆ DMA_CH8_CTRL_TRIG_READ_ERROR_LSB

#define DMA_CH8_CTRL_TRIG_READ_ERROR_LSB _u(30)

◆ DMA_CH8_CTRL_TRIG_READ_ERROR_MSB

#define DMA_CH8_CTRL_TRIG_READ_ERROR_MSB _u(30)

◆ DMA_CH8_CTRL_TRIG_READ_ERROR_RESET

#define DMA_CH8_CTRL_TRIG_READ_ERROR_RESET _u(0x0)

◆ DMA_CH8_CTRL_TRIG_RESET

#define DMA_CH8_CTRL_TRIG_RESET _u(0x00000000)

◆ DMA_CH8_CTRL_TRIG_RING_SEL_ACCESS

#define DMA_CH8_CTRL_TRIG_RING_SEL_ACCESS "RW"

◆ DMA_CH8_CTRL_TRIG_RING_SEL_BITS

#define DMA_CH8_CTRL_TRIG_RING_SEL_BITS _u(0x00001000)

◆ DMA_CH8_CTRL_TRIG_RING_SEL_LSB

#define DMA_CH8_CTRL_TRIG_RING_SEL_LSB _u(12)

◆ DMA_CH8_CTRL_TRIG_RING_SEL_MSB

#define DMA_CH8_CTRL_TRIG_RING_SEL_MSB _u(12)

◆ DMA_CH8_CTRL_TRIG_RING_SEL_RESET

#define DMA_CH8_CTRL_TRIG_RING_SEL_RESET _u(0x0)

◆ DMA_CH8_CTRL_TRIG_RING_SIZE_ACCESS

#define DMA_CH8_CTRL_TRIG_RING_SIZE_ACCESS "RW"

◆ DMA_CH8_CTRL_TRIG_RING_SIZE_BITS

#define DMA_CH8_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00)

◆ DMA_CH8_CTRL_TRIG_RING_SIZE_LSB

#define DMA_CH8_CTRL_TRIG_RING_SIZE_LSB _u(8)

◆ DMA_CH8_CTRL_TRIG_RING_SIZE_MSB

#define DMA_CH8_CTRL_TRIG_RING_SIZE_MSB _u(11)

◆ DMA_CH8_CTRL_TRIG_RING_SIZE_RESET

#define DMA_CH8_CTRL_TRIG_RING_SIZE_RESET _u(0x0)

◆ DMA_CH8_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE

#define DMA_CH8_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0)

◆ DMA_CH8_CTRL_TRIG_SNIFF_EN_ACCESS

#define DMA_CH8_CTRL_TRIG_SNIFF_EN_ACCESS "RW"

◆ DMA_CH8_CTRL_TRIG_SNIFF_EN_BITS

#define DMA_CH8_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000)

◆ DMA_CH8_CTRL_TRIG_SNIFF_EN_LSB

#define DMA_CH8_CTRL_TRIG_SNIFF_EN_LSB _u(25)

◆ DMA_CH8_CTRL_TRIG_SNIFF_EN_MSB

#define DMA_CH8_CTRL_TRIG_SNIFF_EN_MSB _u(25)

◆ DMA_CH8_CTRL_TRIG_SNIFF_EN_RESET

#define DMA_CH8_CTRL_TRIG_SNIFF_EN_RESET _u(0x0)

◆ DMA_CH8_CTRL_TRIG_TREQ_SEL_ACCESS

#define DMA_CH8_CTRL_TRIG_TREQ_SEL_ACCESS "RW"

◆ DMA_CH8_CTRL_TRIG_TREQ_SEL_BITS

#define DMA_CH8_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000)

◆ DMA_CH8_CTRL_TRIG_TREQ_SEL_LSB

#define DMA_CH8_CTRL_TRIG_TREQ_SEL_LSB _u(17)

◆ DMA_CH8_CTRL_TRIG_TREQ_SEL_MSB

#define DMA_CH8_CTRL_TRIG_TREQ_SEL_MSB _u(22)

◆ DMA_CH8_CTRL_TRIG_TREQ_SEL_RESET

#define DMA_CH8_CTRL_TRIG_TREQ_SEL_RESET _u(0x00)

◆ DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT

#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f)

◆ DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0

#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b)

◆ DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1

#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c)

◆ DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2

#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d)

◆ DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3

#define DMA_CH8_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e)

◆ DMA_CH8_CTRL_TRIG_WRITE_ERROR_ACCESS

#define DMA_CH8_CTRL_TRIG_WRITE_ERROR_ACCESS "WC"

◆ DMA_CH8_CTRL_TRIG_WRITE_ERROR_BITS

#define DMA_CH8_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000)

◆ DMA_CH8_CTRL_TRIG_WRITE_ERROR_LSB

#define DMA_CH8_CTRL_TRIG_WRITE_ERROR_LSB _u(29)

◆ DMA_CH8_CTRL_TRIG_WRITE_ERROR_MSB

#define DMA_CH8_CTRL_TRIG_WRITE_ERROR_MSB _u(29)

◆ DMA_CH8_CTRL_TRIG_WRITE_ERROR_RESET

#define DMA_CH8_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0)

◆ DMA_CH8_DBG_CTDREQ_ACCESS

#define DMA_CH8_DBG_CTDREQ_ACCESS "WC"

◆ DMA_CH8_DBG_CTDREQ_BITS

#define DMA_CH8_DBG_CTDREQ_BITS _u(0x0000003f)

◆ DMA_CH8_DBG_CTDREQ_LSB

#define DMA_CH8_DBG_CTDREQ_LSB _u(0)

◆ DMA_CH8_DBG_CTDREQ_MSB

#define DMA_CH8_DBG_CTDREQ_MSB _u(5)

◆ DMA_CH8_DBG_CTDREQ_OFFSET

#define DMA_CH8_DBG_CTDREQ_OFFSET _u(0x00000a00)

◆ DMA_CH8_DBG_CTDREQ_RESET

#define DMA_CH8_DBG_CTDREQ_RESET _u(0x00000000)

◆ DMA_CH8_DBG_TCR_ACCESS

#define DMA_CH8_DBG_TCR_ACCESS "RO"

◆ DMA_CH8_DBG_TCR_BITS

#define DMA_CH8_DBG_TCR_BITS _u(0xffffffff)

◆ DMA_CH8_DBG_TCR_LSB

#define DMA_CH8_DBG_TCR_LSB _u(0)

◆ DMA_CH8_DBG_TCR_MSB

#define DMA_CH8_DBG_TCR_MSB _u(31)

◆ DMA_CH8_DBG_TCR_OFFSET

#define DMA_CH8_DBG_TCR_OFFSET _u(0x00000a04)

◆ DMA_CH8_DBG_TCR_RESET

#define DMA_CH8_DBG_TCR_RESET _u(0x00000000)

◆ DMA_CH8_READ_ADDR_ACCESS

#define DMA_CH8_READ_ADDR_ACCESS "RW"

◆ DMA_CH8_READ_ADDR_BITS

#define DMA_CH8_READ_ADDR_BITS _u(0xffffffff)

◆ DMA_CH8_READ_ADDR_LSB

#define DMA_CH8_READ_ADDR_LSB _u(0)

◆ DMA_CH8_READ_ADDR_MSB

#define DMA_CH8_READ_ADDR_MSB _u(31)

◆ DMA_CH8_READ_ADDR_OFFSET

#define DMA_CH8_READ_ADDR_OFFSET _u(0x00000200)

◆ DMA_CH8_READ_ADDR_RESET

#define DMA_CH8_READ_ADDR_RESET _u(0x00000000)

◆ DMA_CH8_TRANS_COUNT_BITS

#define DMA_CH8_TRANS_COUNT_BITS _u(0xffffffff)

◆ DMA_CH8_TRANS_COUNT_COUNT_ACCESS

#define DMA_CH8_TRANS_COUNT_COUNT_ACCESS "RW"

◆ DMA_CH8_TRANS_COUNT_COUNT_BITS

#define DMA_CH8_TRANS_COUNT_COUNT_BITS _u(0x0fffffff)

◆ DMA_CH8_TRANS_COUNT_COUNT_LSB

#define DMA_CH8_TRANS_COUNT_COUNT_LSB _u(0)

◆ DMA_CH8_TRANS_COUNT_COUNT_MSB

#define DMA_CH8_TRANS_COUNT_COUNT_MSB _u(27)

◆ DMA_CH8_TRANS_COUNT_COUNT_RESET

#define DMA_CH8_TRANS_COUNT_COUNT_RESET _u(0x0000000)

◆ DMA_CH8_TRANS_COUNT_MODE_ACCESS

#define DMA_CH8_TRANS_COUNT_MODE_ACCESS "RW"

◆ DMA_CH8_TRANS_COUNT_MODE_BITS

#define DMA_CH8_TRANS_COUNT_MODE_BITS _u(0xf0000000)

◆ DMA_CH8_TRANS_COUNT_MODE_LSB

#define DMA_CH8_TRANS_COUNT_MODE_LSB _u(28)

◆ DMA_CH8_TRANS_COUNT_MODE_MSB

#define DMA_CH8_TRANS_COUNT_MODE_MSB _u(31)

◆ DMA_CH8_TRANS_COUNT_MODE_RESET

#define DMA_CH8_TRANS_COUNT_MODE_RESET _u(0x0)

◆ DMA_CH8_TRANS_COUNT_MODE_VALUE_ENDLESS

#define DMA_CH8_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf)

◆ DMA_CH8_TRANS_COUNT_MODE_VALUE_NORMAL

#define DMA_CH8_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0)

◆ DMA_CH8_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF

#define DMA_CH8_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1)

◆ DMA_CH8_TRANS_COUNT_OFFSET

#define DMA_CH8_TRANS_COUNT_OFFSET _u(0x00000208)

◆ DMA_CH8_TRANS_COUNT_RESET

#define DMA_CH8_TRANS_COUNT_RESET _u(0x00000000)

◆ DMA_CH8_WRITE_ADDR_ACCESS

#define DMA_CH8_WRITE_ADDR_ACCESS "RW"

◆ DMA_CH8_WRITE_ADDR_BITS

#define DMA_CH8_WRITE_ADDR_BITS _u(0xffffffff)

◆ DMA_CH8_WRITE_ADDR_LSB

#define DMA_CH8_WRITE_ADDR_LSB _u(0)

◆ DMA_CH8_WRITE_ADDR_MSB

#define DMA_CH8_WRITE_ADDR_MSB _u(31)

◆ DMA_CH8_WRITE_ADDR_OFFSET

#define DMA_CH8_WRITE_ADDR_OFFSET _u(0x00000204)

◆ DMA_CH8_WRITE_ADDR_RESET

#define DMA_CH8_WRITE_ADDR_RESET _u(0x00000000)

◆ DMA_CH9_AL1_CTRL_ACCESS

#define DMA_CH9_AL1_CTRL_ACCESS "RW"

◆ DMA_CH9_AL1_CTRL_BITS

#define DMA_CH9_AL1_CTRL_BITS _u(0xffffffff)

◆ DMA_CH9_AL1_CTRL_LSB

#define DMA_CH9_AL1_CTRL_LSB _u(0)

◆ DMA_CH9_AL1_CTRL_MSB

#define DMA_CH9_AL1_CTRL_MSB _u(31)

◆ DMA_CH9_AL1_CTRL_OFFSET

#define DMA_CH9_AL1_CTRL_OFFSET _u(0x00000250)

◆ DMA_CH9_AL1_CTRL_RESET

#define DMA_CH9_AL1_CTRL_RESET "-"

◆ DMA_CH9_AL1_READ_ADDR_ACCESS

#define DMA_CH9_AL1_READ_ADDR_ACCESS "RW"

◆ DMA_CH9_AL1_READ_ADDR_BITS

#define DMA_CH9_AL1_READ_ADDR_BITS _u(0xffffffff)

◆ DMA_CH9_AL1_READ_ADDR_LSB

#define DMA_CH9_AL1_READ_ADDR_LSB _u(0)

◆ DMA_CH9_AL1_READ_ADDR_MSB

#define DMA_CH9_AL1_READ_ADDR_MSB _u(31)

◆ DMA_CH9_AL1_READ_ADDR_OFFSET

#define DMA_CH9_AL1_READ_ADDR_OFFSET _u(0x00000254)

◆ DMA_CH9_AL1_READ_ADDR_RESET

#define DMA_CH9_AL1_READ_ADDR_RESET "-"

◆ DMA_CH9_AL1_TRANS_COUNT_TRIG_ACCESS

#define DMA_CH9_AL1_TRANS_COUNT_TRIG_ACCESS "RW"

◆ DMA_CH9_AL1_TRANS_COUNT_TRIG_BITS

#define DMA_CH9_AL1_TRANS_COUNT_TRIG_BITS _u(0xffffffff)

◆ DMA_CH9_AL1_TRANS_COUNT_TRIG_LSB

#define DMA_CH9_AL1_TRANS_COUNT_TRIG_LSB _u(0)

◆ DMA_CH9_AL1_TRANS_COUNT_TRIG_MSB

#define DMA_CH9_AL1_TRANS_COUNT_TRIG_MSB _u(31)

◆ DMA_CH9_AL1_TRANS_COUNT_TRIG_OFFSET

#define DMA_CH9_AL1_TRANS_COUNT_TRIG_OFFSET _u(0x0000025c)

◆ DMA_CH9_AL1_TRANS_COUNT_TRIG_RESET

#define DMA_CH9_AL1_TRANS_COUNT_TRIG_RESET "-"

◆ DMA_CH9_AL1_WRITE_ADDR_ACCESS

#define DMA_CH9_AL1_WRITE_ADDR_ACCESS "RW"

◆ DMA_CH9_AL1_WRITE_ADDR_BITS

#define DMA_CH9_AL1_WRITE_ADDR_BITS _u(0xffffffff)

◆ DMA_CH9_AL1_WRITE_ADDR_LSB

#define DMA_CH9_AL1_WRITE_ADDR_LSB _u(0)

◆ DMA_CH9_AL1_WRITE_ADDR_MSB

#define DMA_CH9_AL1_WRITE_ADDR_MSB _u(31)

◆ DMA_CH9_AL1_WRITE_ADDR_OFFSET

#define DMA_CH9_AL1_WRITE_ADDR_OFFSET _u(0x00000258)

◆ DMA_CH9_AL1_WRITE_ADDR_RESET

#define DMA_CH9_AL1_WRITE_ADDR_RESET "-"

◆ DMA_CH9_AL2_CTRL_ACCESS

#define DMA_CH9_AL2_CTRL_ACCESS "RW"

◆ DMA_CH9_AL2_CTRL_BITS

#define DMA_CH9_AL2_CTRL_BITS _u(0xffffffff)

◆ DMA_CH9_AL2_CTRL_LSB

#define DMA_CH9_AL2_CTRL_LSB _u(0)

◆ DMA_CH9_AL2_CTRL_MSB

#define DMA_CH9_AL2_CTRL_MSB _u(31)

◆ DMA_CH9_AL2_CTRL_OFFSET

#define DMA_CH9_AL2_CTRL_OFFSET _u(0x00000260)

◆ DMA_CH9_AL2_CTRL_RESET

#define DMA_CH9_AL2_CTRL_RESET "-"

◆ DMA_CH9_AL2_READ_ADDR_ACCESS

#define DMA_CH9_AL2_READ_ADDR_ACCESS "RW"

◆ DMA_CH9_AL2_READ_ADDR_BITS

#define DMA_CH9_AL2_READ_ADDR_BITS _u(0xffffffff)

◆ DMA_CH9_AL2_READ_ADDR_LSB

#define DMA_CH9_AL2_READ_ADDR_LSB _u(0)

◆ DMA_CH9_AL2_READ_ADDR_MSB

#define DMA_CH9_AL2_READ_ADDR_MSB _u(31)

◆ DMA_CH9_AL2_READ_ADDR_OFFSET

#define DMA_CH9_AL2_READ_ADDR_OFFSET _u(0x00000268)

◆ DMA_CH9_AL2_READ_ADDR_RESET

#define DMA_CH9_AL2_READ_ADDR_RESET "-"

◆ DMA_CH9_AL2_TRANS_COUNT_ACCESS

#define DMA_CH9_AL2_TRANS_COUNT_ACCESS "RW"

◆ DMA_CH9_AL2_TRANS_COUNT_BITS

#define DMA_CH9_AL2_TRANS_COUNT_BITS _u(0xffffffff)

◆ DMA_CH9_AL2_TRANS_COUNT_LSB

#define DMA_CH9_AL2_TRANS_COUNT_LSB _u(0)

◆ DMA_CH9_AL2_TRANS_COUNT_MSB

#define DMA_CH9_AL2_TRANS_COUNT_MSB _u(31)

◆ DMA_CH9_AL2_TRANS_COUNT_OFFSET

#define DMA_CH9_AL2_TRANS_COUNT_OFFSET _u(0x00000264)

◆ DMA_CH9_AL2_TRANS_COUNT_RESET

#define DMA_CH9_AL2_TRANS_COUNT_RESET "-"

◆ DMA_CH9_AL2_WRITE_ADDR_TRIG_ACCESS

#define DMA_CH9_AL2_WRITE_ADDR_TRIG_ACCESS "RW"

◆ DMA_CH9_AL2_WRITE_ADDR_TRIG_BITS

#define DMA_CH9_AL2_WRITE_ADDR_TRIG_BITS _u(0xffffffff)

◆ DMA_CH9_AL2_WRITE_ADDR_TRIG_LSB

#define DMA_CH9_AL2_WRITE_ADDR_TRIG_LSB _u(0)

◆ DMA_CH9_AL2_WRITE_ADDR_TRIG_MSB

#define DMA_CH9_AL2_WRITE_ADDR_TRIG_MSB _u(31)

◆ DMA_CH9_AL2_WRITE_ADDR_TRIG_OFFSET

#define DMA_CH9_AL2_WRITE_ADDR_TRIG_OFFSET _u(0x0000026c)

◆ DMA_CH9_AL2_WRITE_ADDR_TRIG_RESET

#define DMA_CH9_AL2_WRITE_ADDR_TRIG_RESET "-"

◆ DMA_CH9_AL3_CTRL_ACCESS

#define DMA_CH9_AL3_CTRL_ACCESS "RW"

◆ DMA_CH9_AL3_CTRL_BITS

#define DMA_CH9_AL3_CTRL_BITS _u(0xffffffff)

◆ DMA_CH9_AL3_CTRL_LSB

#define DMA_CH9_AL3_CTRL_LSB _u(0)

◆ DMA_CH9_AL3_CTRL_MSB

#define DMA_CH9_AL3_CTRL_MSB _u(31)

◆ DMA_CH9_AL3_CTRL_OFFSET

#define DMA_CH9_AL3_CTRL_OFFSET _u(0x00000270)

◆ DMA_CH9_AL3_CTRL_RESET

#define DMA_CH9_AL3_CTRL_RESET "-"

◆ DMA_CH9_AL3_READ_ADDR_TRIG_ACCESS

#define DMA_CH9_AL3_READ_ADDR_TRIG_ACCESS "RW"

◆ DMA_CH9_AL3_READ_ADDR_TRIG_BITS

#define DMA_CH9_AL3_READ_ADDR_TRIG_BITS _u(0xffffffff)

◆ DMA_CH9_AL3_READ_ADDR_TRIG_LSB

#define DMA_CH9_AL3_READ_ADDR_TRIG_LSB _u(0)

◆ DMA_CH9_AL3_READ_ADDR_TRIG_MSB

#define DMA_CH9_AL3_READ_ADDR_TRIG_MSB _u(31)

◆ DMA_CH9_AL3_READ_ADDR_TRIG_OFFSET

#define DMA_CH9_AL3_READ_ADDR_TRIG_OFFSET _u(0x0000027c)

◆ DMA_CH9_AL3_READ_ADDR_TRIG_RESET

#define DMA_CH9_AL3_READ_ADDR_TRIG_RESET "-"

◆ DMA_CH9_AL3_TRANS_COUNT_ACCESS

#define DMA_CH9_AL3_TRANS_COUNT_ACCESS "RW"

◆ DMA_CH9_AL3_TRANS_COUNT_BITS

#define DMA_CH9_AL3_TRANS_COUNT_BITS _u(0xffffffff)

◆ DMA_CH9_AL3_TRANS_COUNT_LSB

#define DMA_CH9_AL3_TRANS_COUNT_LSB _u(0)

◆ DMA_CH9_AL3_TRANS_COUNT_MSB

#define DMA_CH9_AL3_TRANS_COUNT_MSB _u(31)

◆ DMA_CH9_AL3_TRANS_COUNT_OFFSET

#define DMA_CH9_AL3_TRANS_COUNT_OFFSET _u(0x00000278)

◆ DMA_CH9_AL3_TRANS_COUNT_RESET

#define DMA_CH9_AL3_TRANS_COUNT_RESET "-"

◆ DMA_CH9_AL3_WRITE_ADDR_ACCESS

#define DMA_CH9_AL3_WRITE_ADDR_ACCESS "RW"

◆ DMA_CH9_AL3_WRITE_ADDR_BITS

#define DMA_CH9_AL3_WRITE_ADDR_BITS _u(0xffffffff)

◆ DMA_CH9_AL3_WRITE_ADDR_LSB

#define DMA_CH9_AL3_WRITE_ADDR_LSB _u(0)

◆ DMA_CH9_AL3_WRITE_ADDR_MSB

#define DMA_CH9_AL3_WRITE_ADDR_MSB _u(31)

◆ DMA_CH9_AL3_WRITE_ADDR_OFFSET

#define DMA_CH9_AL3_WRITE_ADDR_OFFSET _u(0x00000274)

◆ DMA_CH9_AL3_WRITE_ADDR_RESET

#define DMA_CH9_AL3_WRITE_ADDR_RESET "-"

◆ DMA_CH9_CTRL_TRIG_AHB_ERROR_ACCESS

#define DMA_CH9_CTRL_TRIG_AHB_ERROR_ACCESS "RO"

◆ DMA_CH9_CTRL_TRIG_AHB_ERROR_BITS

#define DMA_CH9_CTRL_TRIG_AHB_ERROR_BITS _u(0x80000000)

◆ DMA_CH9_CTRL_TRIG_AHB_ERROR_LSB

#define DMA_CH9_CTRL_TRIG_AHB_ERROR_LSB _u(31)

◆ DMA_CH9_CTRL_TRIG_AHB_ERROR_MSB

#define DMA_CH9_CTRL_TRIG_AHB_ERROR_MSB _u(31)

◆ DMA_CH9_CTRL_TRIG_AHB_ERROR_RESET

#define DMA_CH9_CTRL_TRIG_AHB_ERROR_RESET _u(0x0)

◆ DMA_CH9_CTRL_TRIG_BITS

#define DMA_CH9_CTRL_TRIG_BITS _u(0xe7ffffff)

◆ DMA_CH9_CTRL_TRIG_BSWAP_ACCESS

#define DMA_CH9_CTRL_TRIG_BSWAP_ACCESS "RW"

◆ DMA_CH9_CTRL_TRIG_BSWAP_BITS

#define DMA_CH9_CTRL_TRIG_BSWAP_BITS _u(0x01000000)

◆ DMA_CH9_CTRL_TRIG_BSWAP_LSB

#define DMA_CH9_CTRL_TRIG_BSWAP_LSB _u(24)

◆ DMA_CH9_CTRL_TRIG_BSWAP_MSB

#define DMA_CH9_CTRL_TRIG_BSWAP_MSB _u(24)

◆ DMA_CH9_CTRL_TRIG_BSWAP_RESET

#define DMA_CH9_CTRL_TRIG_BSWAP_RESET _u(0x0)

◆ DMA_CH9_CTRL_TRIG_BUSY_ACCESS

#define DMA_CH9_CTRL_TRIG_BUSY_ACCESS "RO"

◆ DMA_CH9_CTRL_TRIG_BUSY_BITS

#define DMA_CH9_CTRL_TRIG_BUSY_BITS _u(0x04000000)

◆ DMA_CH9_CTRL_TRIG_BUSY_LSB

#define DMA_CH9_CTRL_TRIG_BUSY_LSB _u(26)

◆ DMA_CH9_CTRL_TRIG_BUSY_MSB

#define DMA_CH9_CTRL_TRIG_BUSY_MSB _u(26)

◆ DMA_CH9_CTRL_TRIG_BUSY_RESET

#define DMA_CH9_CTRL_TRIG_BUSY_RESET _u(0x0)

◆ DMA_CH9_CTRL_TRIG_CHAIN_TO_ACCESS

#define DMA_CH9_CTRL_TRIG_CHAIN_TO_ACCESS "RW"

◆ DMA_CH9_CTRL_TRIG_CHAIN_TO_BITS

#define DMA_CH9_CTRL_TRIG_CHAIN_TO_BITS _u(0x0001e000)

◆ DMA_CH9_CTRL_TRIG_CHAIN_TO_LSB

#define DMA_CH9_CTRL_TRIG_CHAIN_TO_LSB _u(13)

◆ DMA_CH9_CTRL_TRIG_CHAIN_TO_MSB

#define DMA_CH9_CTRL_TRIG_CHAIN_TO_MSB _u(16)

◆ DMA_CH9_CTRL_TRIG_CHAIN_TO_RESET

#define DMA_CH9_CTRL_TRIG_CHAIN_TO_RESET _u(0x0)

◆ DMA_CH9_CTRL_TRIG_DATA_SIZE_ACCESS

#define DMA_CH9_CTRL_TRIG_DATA_SIZE_ACCESS "RW"

◆ DMA_CH9_CTRL_TRIG_DATA_SIZE_BITS

#define DMA_CH9_CTRL_TRIG_DATA_SIZE_BITS _u(0x0000000c)

◆ DMA_CH9_CTRL_TRIG_DATA_SIZE_LSB

#define DMA_CH9_CTRL_TRIG_DATA_SIZE_LSB _u(2)

◆ DMA_CH9_CTRL_TRIG_DATA_SIZE_MSB

#define DMA_CH9_CTRL_TRIG_DATA_SIZE_MSB _u(3)

◆ DMA_CH9_CTRL_TRIG_DATA_SIZE_RESET

#define DMA_CH9_CTRL_TRIG_DATA_SIZE_RESET _u(0x0)

◆ DMA_CH9_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE

#define DMA_CH9_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE _u(0x0)

◆ DMA_CH9_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD

#define DMA_CH9_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD _u(0x1)

◆ DMA_CH9_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD

#define DMA_CH9_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_WORD _u(0x2)

◆ DMA_CH9_CTRL_TRIG_EN_ACCESS

#define DMA_CH9_CTRL_TRIG_EN_ACCESS "RW"

◆ DMA_CH9_CTRL_TRIG_EN_BITS

#define DMA_CH9_CTRL_TRIG_EN_BITS _u(0x00000001)

◆ DMA_CH9_CTRL_TRIG_EN_LSB

#define DMA_CH9_CTRL_TRIG_EN_LSB _u(0)

◆ DMA_CH9_CTRL_TRIG_EN_MSB

#define DMA_CH9_CTRL_TRIG_EN_MSB _u(0)

◆ DMA_CH9_CTRL_TRIG_EN_RESET

#define DMA_CH9_CTRL_TRIG_EN_RESET _u(0x0)

◆ DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_ACCESS

#define DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW"

◆ DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_BITS

#define DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_BITS _u(0x00000002)

◆ DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_LSB

#define DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_LSB _u(1)

◆ DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_MSB

#define DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_MSB _u(1)

◆ DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_RESET

#define DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_RESET _u(0x0)

◆ DMA_CH9_CTRL_TRIG_INCR_READ_ACCESS

#define DMA_CH9_CTRL_TRIG_INCR_READ_ACCESS "RW"

◆ DMA_CH9_CTRL_TRIG_INCR_READ_BITS

#define DMA_CH9_CTRL_TRIG_INCR_READ_BITS _u(0x00000010)

◆ DMA_CH9_CTRL_TRIG_INCR_READ_LSB

#define DMA_CH9_CTRL_TRIG_INCR_READ_LSB _u(4)

◆ DMA_CH9_CTRL_TRIG_INCR_READ_MSB

#define DMA_CH9_CTRL_TRIG_INCR_READ_MSB _u(4)

◆ DMA_CH9_CTRL_TRIG_INCR_READ_RESET

#define DMA_CH9_CTRL_TRIG_INCR_READ_RESET _u(0x0)

◆ DMA_CH9_CTRL_TRIG_INCR_READ_REV_ACCESS

#define DMA_CH9_CTRL_TRIG_INCR_READ_REV_ACCESS "RW"

◆ DMA_CH9_CTRL_TRIG_INCR_READ_REV_BITS

#define DMA_CH9_CTRL_TRIG_INCR_READ_REV_BITS _u(0x00000020)

◆ DMA_CH9_CTRL_TRIG_INCR_READ_REV_LSB

#define DMA_CH9_CTRL_TRIG_INCR_READ_REV_LSB _u(5)

◆ DMA_CH9_CTRL_TRIG_INCR_READ_REV_MSB

#define DMA_CH9_CTRL_TRIG_INCR_READ_REV_MSB _u(5)

◆ DMA_CH9_CTRL_TRIG_INCR_READ_REV_RESET

#define DMA_CH9_CTRL_TRIG_INCR_READ_REV_RESET _u(0x0)

◆ DMA_CH9_CTRL_TRIG_INCR_WRITE_ACCESS

#define DMA_CH9_CTRL_TRIG_INCR_WRITE_ACCESS "RW"

◆ DMA_CH9_CTRL_TRIG_INCR_WRITE_BITS

#define DMA_CH9_CTRL_TRIG_INCR_WRITE_BITS _u(0x00000040)

◆ DMA_CH9_CTRL_TRIG_INCR_WRITE_LSB

#define DMA_CH9_CTRL_TRIG_INCR_WRITE_LSB _u(6)

◆ DMA_CH9_CTRL_TRIG_INCR_WRITE_MSB

#define DMA_CH9_CTRL_TRIG_INCR_WRITE_MSB _u(6)

◆ DMA_CH9_CTRL_TRIG_INCR_WRITE_RESET

#define DMA_CH9_CTRL_TRIG_INCR_WRITE_RESET _u(0x0)

◆ DMA_CH9_CTRL_TRIG_INCR_WRITE_REV_ACCESS

#define DMA_CH9_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW"

◆ DMA_CH9_CTRL_TRIG_INCR_WRITE_REV_BITS

#define DMA_CH9_CTRL_TRIG_INCR_WRITE_REV_BITS _u(0x00000080)

◆ DMA_CH9_CTRL_TRIG_INCR_WRITE_REV_LSB

#define DMA_CH9_CTRL_TRIG_INCR_WRITE_REV_LSB _u(7)

◆ DMA_CH9_CTRL_TRIG_INCR_WRITE_REV_MSB

#define DMA_CH9_CTRL_TRIG_INCR_WRITE_REV_MSB _u(7)

◆ DMA_CH9_CTRL_TRIG_INCR_WRITE_REV_RESET

#define DMA_CH9_CTRL_TRIG_INCR_WRITE_REV_RESET _u(0x0)

◆ DMA_CH9_CTRL_TRIG_IRQ_QUIET_ACCESS

#define DMA_CH9_CTRL_TRIG_IRQ_QUIET_ACCESS "RW"

◆ DMA_CH9_CTRL_TRIG_IRQ_QUIET_BITS

#define DMA_CH9_CTRL_TRIG_IRQ_QUIET_BITS _u(0x00800000)

◆ DMA_CH9_CTRL_TRIG_IRQ_QUIET_LSB

#define DMA_CH9_CTRL_TRIG_IRQ_QUIET_LSB _u(23)

◆ DMA_CH9_CTRL_TRIG_IRQ_QUIET_MSB

#define DMA_CH9_CTRL_TRIG_IRQ_QUIET_MSB _u(23)

◆ DMA_CH9_CTRL_TRIG_IRQ_QUIET_RESET

#define DMA_CH9_CTRL_TRIG_IRQ_QUIET_RESET _u(0x0)

◆ DMA_CH9_CTRL_TRIG_OFFSET

#define DMA_CH9_CTRL_TRIG_OFFSET _u(0x0000024c)

◆ DMA_CH9_CTRL_TRIG_READ_ERROR_ACCESS

#define DMA_CH9_CTRL_TRIG_READ_ERROR_ACCESS "WC"

◆ DMA_CH9_CTRL_TRIG_READ_ERROR_BITS

#define DMA_CH9_CTRL_TRIG_READ_ERROR_BITS _u(0x40000000)

◆ DMA_CH9_CTRL_TRIG_READ_ERROR_LSB

#define DMA_CH9_CTRL_TRIG_READ_ERROR_LSB _u(30)

◆ DMA_CH9_CTRL_TRIG_READ_ERROR_MSB

#define DMA_CH9_CTRL_TRIG_READ_ERROR_MSB _u(30)

◆ DMA_CH9_CTRL_TRIG_READ_ERROR_RESET

#define DMA_CH9_CTRL_TRIG_READ_ERROR_RESET _u(0x0)

◆ DMA_CH9_CTRL_TRIG_RESET

#define DMA_CH9_CTRL_TRIG_RESET _u(0x00000000)

◆ DMA_CH9_CTRL_TRIG_RING_SEL_ACCESS

#define DMA_CH9_CTRL_TRIG_RING_SEL_ACCESS "RW"

◆ DMA_CH9_CTRL_TRIG_RING_SEL_BITS

#define DMA_CH9_CTRL_TRIG_RING_SEL_BITS _u(0x00001000)

◆ DMA_CH9_CTRL_TRIG_RING_SEL_LSB

#define DMA_CH9_CTRL_TRIG_RING_SEL_LSB _u(12)

◆ DMA_CH9_CTRL_TRIG_RING_SEL_MSB

#define DMA_CH9_CTRL_TRIG_RING_SEL_MSB _u(12)

◆ DMA_CH9_CTRL_TRIG_RING_SEL_RESET

#define DMA_CH9_CTRL_TRIG_RING_SEL_RESET _u(0x0)

◆ DMA_CH9_CTRL_TRIG_RING_SIZE_ACCESS

#define DMA_CH9_CTRL_TRIG_RING_SIZE_ACCESS "RW"

◆ DMA_CH9_CTRL_TRIG_RING_SIZE_BITS

#define DMA_CH9_CTRL_TRIG_RING_SIZE_BITS _u(0x00000f00)

◆ DMA_CH9_CTRL_TRIG_RING_SIZE_LSB

#define DMA_CH9_CTRL_TRIG_RING_SIZE_LSB _u(8)

◆ DMA_CH9_CTRL_TRIG_RING_SIZE_MSB

#define DMA_CH9_CTRL_TRIG_RING_SIZE_MSB _u(11)

◆ DMA_CH9_CTRL_TRIG_RING_SIZE_RESET

#define DMA_CH9_CTRL_TRIG_RING_SIZE_RESET _u(0x0)

◆ DMA_CH9_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE

#define DMA_CH9_CTRL_TRIG_RING_SIZE_VALUE_RING_NONE _u(0x0)

◆ DMA_CH9_CTRL_TRIG_SNIFF_EN_ACCESS

#define DMA_CH9_CTRL_TRIG_SNIFF_EN_ACCESS "RW"

◆ DMA_CH9_CTRL_TRIG_SNIFF_EN_BITS

#define DMA_CH9_CTRL_TRIG_SNIFF_EN_BITS _u(0x02000000)

◆ DMA_CH9_CTRL_TRIG_SNIFF_EN_LSB

#define DMA_CH9_CTRL_TRIG_SNIFF_EN_LSB _u(25)

◆ DMA_CH9_CTRL_TRIG_SNIFF_EN_MSB

#define DMA_CH9_CTRL_TRIG_SNIFF_EN_MSB _u(25)

◆ DMA_CH9_CTRL_TRIG_SNIFF_EN_RESET

#define DMA_CH9_CTRL_TRIG_SNIFF_EN_RESET _u(0x0)

◆ DMA_CH9_CTRL_TRIG_TREQ_SEL_ACCESS

#define DMA_CH9_CTRL_TRIG_TREQ_SEL_ACCESS "RW"

◆ DMA_CH9_CTRL_TRIG_TREQ_SEL_BITS

#define DMA_CH9_CTRL_TRIG_TREQ_SEL_BITS _u(0x007e0000)

◆ DMA_CH9_CTRL_TRIG_TREQ_SEL_LSB

#define DMA_CH9_CTRL_TRIG_TREQ_SEL_LSB _u(17)

◆ DMA_CH9_CTRL_TRIG_TREQ_SEL_MSB

#define DMA_CH9_CTRL_TRIG_TREQ_SEL_MSB _u(22)

◆ DMA_CH9_CTRL_TRIG_TREQ_SEL_RESET

#define DMA_CH9_CTRL_TRIG_TREQ_SEL_RESET _u(0x00)

◆ DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT

#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_PERMANENT _u(0x3f)

◆ DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0

#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER0 _u(0x3b)

◆ DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1

#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER1 _u(0x3c)

◆ DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2

#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER2 _u(0x3d)

◆ DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3

#define DMA_CH9_CTRL_TRIG_TREQ_SEL_VALUE_TIMER3 _u(0x3e)

◆ DMA_CH9_CTRL_TRIG_WRITE_ERROR_ACCESS

#define DMA_CH9_CTRL_TRIG_WRITE_ERROR_ACCESS "WC"

◆ DMA_CH9_CTRL_TRIG_WRITE_ERROR_BITS

#define DMA_CH9_CTRL_TRIG_WRITE_ERROR_BITS _u(0x20000000)

◆ DMA_CH9_CTRL_TRIG_WRITE_ERROR_LSB

#define DMA_CH9_CTRL_TRIG_WRITE_ERROR_LSB _u(29)

◆ DMA_CH9_CTRL_TRIG_WRITE_ERROR_MSB

#define DMA_CH9_CTRL_TRIG_WRITE_ERROR_MSB _u(29)

◆ DMA_CH9_CTRL_TRIG_WRITE_ERROR_RESET

#define DMA_CH9_CTRL_TRIG_WRITE_ERROR_RESET _u(0x0)

◆ DMA_CH9_DBG_CTDREQ_ACCESS

#define DMA_CH9_DBG_CTDREQ_ACCESS "WC"

◆ DMA_CH9_DBG_CTDREQ_BITS

#define DMA_CH9_DBG_CTDREQ_BITS _u(0x0000003f)

◆ DMA_CH9_DBG_CTDREQ_LSB

#define DMA_CH9_DBG_CTDREQ_LSB _u(0)

◆ DMA_CH9_DBG_CTDREQ_MSB

#define DMA_CH9_DBG_CTDREQ_MSB _u(5)

◆ DMA_CH9_DBG_CTDREQ_OFFSET

#define DMA_CH9_DBG_CTDREQ_OFFSET _u(0x00000a40)

◆ DMA_CH9_DBG_CTDREQ_RESET

#define DMA_CH9_DBG_CTDREQ_RESET _u(0x00000000)

◆ DMA_CH9_DBG_TCR_ACCESS

#define DMA_CH9_DBG_TCR_ACCESS "RO"

◆ DMA_CH9_DBG_TCR_BITS

#define DMA_CH9_DBG_TCR_BITS _u(0xffffffff)

◆ DMA_CH9_DBG_TCR_LSB

#define DMA_CH9_DBG_TCR_LSB _u(0)

◆ DMA_CH9_DBG_TCR_MSB

#define DMA_CH9_DBG_TCR_MSB _u(31)

◆ DMA_CH9_DBG_TCR_OFFSET

#define DMA_CH9_DBG_TCR_OFFSET _u(0x00000a44)

◆ DMA_CH9_DBG_TCR_RESET

#define DMA_CH9_DBG_TCR_RESET _u(0x00000000)

◆ DMA_CH9_READ_ADDR_ACCESS

#define DMA_CH9_READ_ADDR_ACCESS "RW"

◆ DMA_CH9_READ_ADDR_BITS

#define DMA_CH9_READ_ADDR_BITS _u(0xffffffff)

◆ DMA_CH9_READ_ADDR_LSB

#define DMA_CH9_READ_ADDR_LSB _u(0)

◆ DMA_CH9_READ_ADDR_MSB

#define DMA_CH9_READ_ADDR_MSB _u(31)

◆ DMA_CH9_READ_ADDR_OFFSET

#define DMA_CH9_READ_ADDR_OFFSET _u(0x00000240)

◆ DMA_CH9_READ_ADDR_RESET

#define DMA_CH9_READ_ADDR_RESET _u(0x00000000)

◆ DMA_CH9_TRANS_COUNT_BITS

#define DMA_CH9_TRANS_COUNT_BITS _u(0xffffffff)

◆ DMA_CH9_TRANS_COUNT_COUNT_ACCESS

#define DMA_CH9_TRANS_COUNT_COUNT_ACCESS "RW"

◆ DMA_CH9_TRANS_COUNT_COUNT_BITS

#define DMA_CH9_TRANS_COUNT_COUNT_BITS _u(0x0fffffff)

◆ DMA_CH9_TRANS_COUNT_COUNT_LSB

#define DMA_CH9_TRANS_COUNT_COUNT_LSB _u(0)

◆ DMA_CH9_TRANS_COUNT_COUNT_MSB

#define DMA_CH9_TRANS_COUNT_COUNT_MSB _u(27)

◆ DMA_CH9_TRANS_COUNT_COUNT_RESET

#define DMA_CH9_TRANS_COUNT_COUNT_RESET _u(0x0000000)

◆ DMA_CH9_TRANS_COUNT_MODE_ACCESS

#define DMA_CH9_TRANS_COUNT_MODE_ACCESS "RW"

◆ DMA_CH9_TRANS_COUNT_MODE_BITS

#define DMA_CH9_TRANS_COUNT_MODE_BITS _u(0xf0000000)

◆ DMA_CH9_TRANS_COUNT_MODE_LSB

#define DMA_CH9_TRANS_COUNT_MODE_LSB _u(28)

◆ DMA_CH9_TRANS_COUNT_MODE_MSB

#define DMA_CH9_TRANS_COUNT_MODE_MSB _u(31)

◆ DMA_CH9_TRANS_COUNT_MODE_RESET

#define DMA_CH9_TRANS_COUNT_MODE_RESET _u(0x0)

◆ DMA_CH9_TRANS_COUNT_MODE_VALUE_ENDLESS

#define DMA_CH9_TRANS_COUNT_MODE_VALUE_ENDLESS _u(0xf)

◆ DMA_CH9_TRANS_COUNT_MODE_VALUE_NORMAL

#define DMA_CH9_TRANS_COUNT_MODE_VALUE_NORMAL _u(0x0)

◆ DMA_CH9_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF

#define DMA_CH9_TRANS_COUNT_MODE_VALUE_TRIGGER_SELF _u(0x1)

◆ DMA_CH9_TRANS_COUNT_OFFSET

#define DMA_CH9_TRANS_COUNT_OFFSET _u(0x00000248)

◆ DMA_CH9_TRANS_COUNT_RESET

#define DMA_CH9_TRANS_COUNT_RESET _u(0x00000000)

◆ DMA_CH9_WRITE_ADDR_ACCESS

#define DMA_CH9_WRITE_ADDR_ACCESS "RW"

◆ DMA_CH9_WRITE_ADDR_BITS

#define DMA_CH9_WRITE_ADDR_BITS _u(0xffffffff)

◆ DMA_CH9_WRITE_ADDR_LSB

#define DMA_CH9_WRITE_ADDR_LSB _u(0)

◆ DMA_CH9_WRITE_ADDR_MSB

#define DMA_CH9_WRITE_ADDR_MSB _u(31)

◆ DMA_CH9_WRITE_ADDR_OFFSET

#define DMA_CH9_WRITE_ADDR_OFFSET _u(0x00000244)

◆ DMA_CH9_WRITE_ADDR_RESET

#define DMA_CH9_WRITE_ADDR_RESET _u(0x00000000)

◆ DMA_CHAN_ABORT_ACCESS

#define DMA_CHAN_ABORT_ACCESS "SC"

◆ DMA_CHAN_ABORT_BITS

#define DMA_CHAN_ABORT_BITS _u(0x0000ffff)

◆ DMA_CHAN_ABORT_LSB

#define DMA_CHAN_ABORT_LSB _u(0)

◆ DMA_CHAN_ABORT_MSB

#define DMA_CHAN_ABORT_MSB _u(15)

◆ DMA_CHAN_ABORT_OFFSET

#define DMA_CHAN_ABORT_OFFSET _u(0x00000464)

◆ DMA_CHAN_ABORT_RESET

#define DMA_CHAN_ABORT_RESET _u(0x00000000)

◆ DMA_FIFO_LEVELS_BITS

#define DMA_FIFO_LEVELS_BITS _u(0x00ffffff)

◆ DMA_FIFO_LEVELS_OFFSET

#define DMA_FIFO_LEVELS_OFFSET _u(0x00000460)

◆ DMA_FIFO_LEVELS_RAF_LVL_ACCESS

#define DMA_FIFO_LEVELS_RAF_LVL_ACCESS "RO"

◆ DMA_FIFO_LEVELS_RAF_LVL_BITS

#define DMA_FIFO_LEVELS_RAF_LVL_BITS _u(0x00ff0000)

◆ DMA_FIFO_LEVELS_RAF_LVL_LSB

#define DMA_FIFO_LEVELS_RAF_LVL_LSB _u(16)

◆ DMA_FIFO_LEVELS_RAF_LVL_MSB

#define DMA_FIFO_LEVELS_RAF_LVL_MSB _u(23)

◆ DMA_FIFO_LEVELS_RAF_LVL_RESET

#define DMA_FIFO_LEVELS_RAF_LVL_RESET _u(0x00)

◆ DMA_FIFO_LEVELS_RESET

#define DMA_FIFO_LEVELS_RESET _u(0x00000000)

◆ DMA_FIFO_LEVELS_TDF_LVL_ACCESS

#define DMA_FIFO_LEVELS_TDF_LVL_ACCESS "RO"

◆ DMA_FIFO_LEVELS_TDF_LVL_BITS

#define DMA_FIFO_LEVELS_TDF_LVL_BITS _u(0x000000ff)

◆ DMA_FIFO_LEVELS_TDF_LVL_LSB

#define DMA_FIFO_LEVELS_TDF_LVL_LSB _u(0)

◆ DMA_FIFO_LEVELS_TDF_LVL_MSB

#define DMA_FIFO_LEVELS_TDF_LVL_MSB _u(7)

◆ DMA_FIFO_LEVELS_TDF_LVL_RESET

#define DMA_FIFO_LEVELS_TDF_LVL_RESET _u(0x00)

◆ DMA_FIFO_LEVELS_WAF_LVL_ACCESS

#define DMA_FIFO_LEVELS_WAF_LVL_ACCESS "RO"

◆ DMA_FIFO_LEVELS_WAF_LVL_BITS

#define DMA_FIFO_LEVELS_WAF_LVL_BITS _u(0x0000ff00)

◆ DMA_FIFO_LEVELS_WAF_LVL_LSB

#define DMA_FIFO_LEVELS_WAF_LVL_LSB _u(8)

◆ DMA_FIFO_LEVELS_WAF_LVL_MSB

#define DMA_FIFO_LEVELS_WAF_LVL_MSB _u(15)

◆ DMA_FIFO_LEVELS_WAF_LVL_RESET

#define DMA_FIFO_LEVELS_WAF_LVL_RESET _u(0x00)

◆ DMA_INTE0_ACCESS

#define DMA_INTE0_ACCESS "RW"

◆ DMA_INTE0_BITS

#define DMA_INTE0_BITS _u(0x0000ffff)

◆ DMA_INTE0_LSB

#define DMA_INTE0_LSB _u(0)

◆ DMA_INTE0_MSB

#define DMA_INTE0_MSB _u(15)

◆ DMA_INTE0_OFFSET

#define DMA_INTE0_OFFSET _u(0x00000404)

◆ DMA_INTE0_RESET

#define DMA_INTE0_RESET _u(0x00000000)

◆ DMA_INTE1_ACCESS

#define DMA_INTE1_ACCESS "RW"

◆ DMA_INTE1_BITS

#define DMA_INTE1_BITS _u(0x0000ffff)

◆ DMA_INTE1_LSB

#define DMA_INTE1_LSB _u(0)

◆ DMA_INTE1_MSB

#define DMA_INTE1_MSB _u(15)

◆ DMA_INTE1_OFFSET

#define DMA_INTE1_OFFSET _u(0x00000414)

◆ DMA_INTE1_RESET

#define DMA_INTE1_RESET _u(0x00000000)

◆ DMA_INTE2_ACCESS

#define DMA_INTE2_ACCESS "RW"

◆ DMA_INTE2_BITS

#define DMA_INTE2_BITS _u(0x0000ffff)

◆ DMA_INTE2_LSB

#define DMA_INTE2_LSB _u(0)

◆ DMA_INTE2_MSB

#define DMA_INTE2_MSB _u(15)

◆ DMA_INTE2_OFFSET

#define DMA_INTE2_OFFSET _u(0x00000424)

◆ DMA_INTE2_RESET

#define DMA_INTE2_RESET _u(0x00000000)

◆ DMA_INTE3_ACCESS

#define DMA_INTE3_ACCESS "RW"

◆ DMA_INTE3_BITS

#define DMA_INTE3_BITS _u(0x0000ffff)

◆ DMA_INTE3_LSB

#define DMA_INTE3_LSB _u(0)

◆ DMA_INTE3_MSB

#define DMA_INTE3_MSB _u(15)

◆ DMA_INTE3_OFFSET

#define DMA_INTE3_OFFSET _u(0x00000434)

◆ DMA_INTE3_RESET

#define DMA_INTE3_RESET _u(0x00000000)

◆ DMA_INTF0_ACCESS

#define DMA_INTF0_ACCESS "RW"

◆ DMA_INTF0_BITS

#define DMA_INTF0_BITS _u(0x0000ffff)

◆ DMA_INTF0_LSB

#define DMA_INTF0_LSB _u(0)

◆ DMA_INTF0_MSB

#define DMA_INTF0_MSB _u(15)

◆ DMA_INTF0_OFFSET

#define DMA_INTF0_OFFSET _u(0x00000408)

◆ DMA_INTF0_RESET

#define DMA_INTF0_RESET _u(0x00000000)

◆ DMA_INTF1_ACCESS

#define DMA_INTF1_ACCESS "RW"

◆ DMA_INTF1_BITS

#define DMA_INTF1_BITS _u(0x0000ffff)

◆ DMA_INTF1_LSB

#define DMA_INTF1_LSB _u(0)

◆ DMA_INTF1_MSB

#define DMA_INTF1_MSB _u(15)

◆ DMA_INTF1_OFFSET

#define DMA_INTF1_OFFSET _u(0x00000418)

◆ DMA_INTF1_RESET

#define DMA_INTF1_RESET _u(0x00000000)

◆ DMA_INTF2_ACCESS

#define DMA_INTF2_ACCESS "RW"

◆ DMA_INTF2_BITS

#define DMA_INTF2_BITS _u(0x0000ffff)

◆ DMA_INTF2_LSB

#define DMA_INTF2_LSB _u(0)

◆ DMA_INTF2_MSB

#define DMA_INTF2_MSB _u(15)

◆ DMA_INTF2_OFFSET

#define DMA_INTF2_OFFSET _u(0x00000428)

◆ DMA_INTF2_RESET

#define DMA_INTF2_RESET _u(0x00000000)

◆ DMA_INTF3_ACCESS

#define DMA_INTF3_ACCESS "RW"

◆ DMA_INTF3_BITS

#define DMA_INTF3_BITS _u(0x0000ffff)

◆ DMA_INTF3_LSB

#define DMA_INTF3_LSB _u(0)

◆ DMA_INTF3_MSB

#define DMA_INTF3_MSB _u(15)

◆ DMA_INTF3_OFFSET

#define DMA_INTF3_OFFSET _u(0x00000438)

◆ DMA_INTF3_RESET

#define DMA_INTF3_RESET _u(0x00000000)

◆ DMA_INTR_ACCESS

#define DMA_INTR_ACCESS "WC"

◆ DMA_INTR_BITS

#define DMA_INTR_BITS _u(0x0000ffff)

◆ DMA_INTR_LSB

#define DMA_INTR_LSB _u(0)

◆ DMA_INTR_MSB

#define DMA_INTR_MSB _u(15)

◆ DMA_INTR_OFFSET

#define DMA_INTR_OFFSET _u(0x00000400)

◆ DMA_INTR_RESET

#define DMA_INTR_RESET _u(0x00000000)

◆ DMA_INTS0_ACCESS

#define DMA_INTS0_ACCESS "WC"

◆ DMA_INTS0_BITS

#define DMA_INTS0_BITS _u(0x0000ffff)

◆ DMA_INTS0_LSB

#define DMA_INTS0_LSB _u(0)

◆ DMA_INTS0_MSB

#define DMA_INTS0_MSB _u(15)

◆ DMA_INTS0_OFFSET

#define DMA_INTS0_OFFSET _u(0x0000040c)

◆ DMA_INTS0_RESET

#define DMA_INTS0_RESET _u(0x00000000)

◆ DMA_INTS1_ACCESS

#define DMA_INTS1_ACCESS "WC"

◆ DMA_INTS1_BITS

#define DMA_INTS1_BITS _u(0x0000ffff)

◆ DMA_INTS1_LSB

#define DMA_INTS1_LSB _u(0)

◆ DMA_INTS1_MSB

#define DMA_INTS1_MSB _u(15)

◆ DMA_INTS1_OFFSET

#define DMA_INTS1_OFFSET _u(0x0000041c)

◆ DMA_INTS1_RESET

#define DMA_INTS1_RESET _u(0x00000000)

◆ DMA_INTS2_ACCESS

#define DMA_INTS2_ACCESS "WC"

◆ DMA_INTS2_BITS

#define DMA_INTS2_BITS _u(0x0000ffff)

◆ DMA_INTS2_LSB

#define DMA_INTS2_LSB _u(0)

◆ DMA_INTS2_MSB

#define DMA_INTS2_MSB _u(15)

◆ DMA_INTS2_OFFSET

#define DMA_INTS2_OFFSET _u(0x0000042c)

◆ DMA_INTS2_RESET

#define DMA_INTS2_RESET _u(0x00000000)

◆ DMA_INTS3_ACCESS

#define DMA_INTS3_ACCESS "WC"

◆ DMA_INTS3_BITS

#define DMA_INTS3_BITS _u(0x0000ffff)

◆ DMA_INTS3_LSB

#define DMA_INTS3_LSB _u(0)

◆ DMA_INTS3_MSB

#define DMA_INTS3_MSB _u(15)

◆ DMA_INTS3_OFFSET

#define DMA_INTS3_OFFSET _u(0x0000043c)

◆ DMA_INTS3_RESET

#define DMA_INTS3_RESET _u(0x00000000)

◆ DMA_MPU_BAR0_ADDR_ACCESS

#define DMA_MPU_BAR0_ADDR_ACCESS "RW"

◆ DMA_MPU_BAR0_ADDR_BITS

#define DMA_MPU_BAR0_ADDR_BITS _u(0xffffffe0)

◆ DMA_MPU_BAR0_ADDR_LSB

#define DMA_MPU_BAR0_ADDR_LSB _u(5)

◆ DMA_MPU_BAR0_ADDR_MSB

#define DMA_MPU_BAR0_ADDR_MSB _u(31)

◆ DMA_MPU_BAR0_ADDR_RESET

#define DMA_MPU_BAR0_ADDR_RESET _u(0x0000000)

◆ DMA_MPU_BAR0_BITS

#define DMA_MPU_BAR0_BITS _u(0xffffffe0)

◆ DMA_MPU_BAR0_OFFSET

#define DMA_MPU_BAR0_OFFSET _u(0x00000504)

◆ DMA_MPU_BAR0_RESET

#define DMA_MPU_BAR0_RESET _u(0x00000000)

◆ DMA_MPU_BAR1_ADDR_ACCESS

#define DMA_MPU_BAR1_ADDR_ACCESS "RW"

◆ DMA_MPU_BAR1_ADDR_BITS

#define DMA_MPU_BAR1_ADDR_BITS _u(0xffffffe0)

◆ DMA_MPU_BAR1_ADDR_LSB

#define DMA_MPU_BAR1_ADDR_LSB _u(5)

◆ DMA_MPU_BAR1_ADDR_MSB

#define DMA_MPU_BAR1_ADDR_MSB _u(31)

◆ DMA_MPU_BAR1_ADDR_RESET

#define DMA_MPU_BAR1_ADDR_RESET _u(0x0000000)

◆ DMA_MPU_BAR1_BITS

#define DMA_MPU_BAR1_BITS _u(0xffffffe0)

◆ DMA_MPU_BAR1_OFFSET

#define DMA_MPU_BAR1_OFFSET _u(0x0000050c)

◆ DMA_MPU_BAR1_RESET

#define DMA_MPU_BAR1_RESET _u(0x00000000)

◆ DMA_MPU_BAR2_ADDR_ACCESS

#define DMA_MPU_BAR2_ADDR_ACCESS "RW"

◆ DMA_MPU_BAR2_ADDR_BITS

#define DMA_MPU_BAR2_ADDR_BITS _u(0xffffffe0)

◆ DMA_MPU_BAR2_ADDR_LSB

#define DMA_MPU_BAR2_ADDR_LSB _u(5)

◆ DMA_MPU_BAR2_ADDR_MSB

#define DMA_MPU_BAR2_ADDR_MSB _u(31)

◆ DMA_MPU_BAR2_ADDR_RESET

#define DMA_MPU_BAR2_ADDR_RESET _u(0x0000000)

◆ DMA_MPU_BAR2_BITS

#define DMA_MPU_BAR2_BITS _u(0xffffffe0)

◆ DMA_MPU_BAR2_OFFSET

#define DMA_MPU_BAR2_OFFSET _u(0x00000514)

◆ DMA_MPU_BAR2_RESET

#define DMA_MPU_BAR2_RESET _u(0x00000000)

◆ DMA_MPU_BAR3_ADDR_ACCESS

#define DMA_MPU_BAR3_ADDR_ACCESS "RW"

◆ DMA_MPU_BAR3_ADDR_BITS

#define DMA_MPU_BAR3_ADDR_BITS _u(0xffffffe0)

◆ DMA_MPU_BAR3_ADDR_LSB

#define DMA_MPU_BAR3_ADDR_LSB _u(5)

◆ DMA_MPU_BAR3_ADDR_MSB

#define DMA_MPU_BAR3_ADDR_MSB _u(31)

◆ DMA_MPU_BAR3_ADDR_RESET

#define DMA_MPU_BAR3_ADDR_RESET _u(0x0000000)

◆ DMA_MPU_BAR3_BITS

#define DMA_MPU_BAR3_BITS _u(0xffffffe0)

◆ DMA_MPU_BAR3_OFFSET

#define DMA_MPU_BAR3_OFFSET _u(0x0000051c)

◆ DMA_MPU_BAR3_RESET

#define DMA_MPU_BAR3_RESET _u(0x00000000)

◆ DMA_MPU_BAR4_ADDR_ACCESS

#define DMA_MPU_BAR4_ADDR_ACCESS "RW"

◆ DMA_MPU_BAR4_ADDR_BITS

#define DMA_MPU_BAR4_ADDR_BITS _u(0xffffffe0)

◆ DMA_MPU_BAR4_ADDR_LSB

#define DMA_MPU_BAR4_ADDR_LSB _u(5)

◆ DMA_MPU_BAR4_ADDR_MSB

#define DMA_MPU_BAR4_ADDR_MSB _u(31)

◆ DMA_MPU_BAR4_ADDR_RESET

#define DMA_MPU_BAR4_ADDR_RESET _u(0x0000000)

◆ DMA_MPU_BAR4_BITS

#define DMA_MPU_BAR4_BITS _u(0xffffffe0)

◆ DMA_MPU_BAR4_OFFSET

#define DMA_MPU_BAR4_OFFSET _u(0x00000524)

◆ DMA_MPU_BAR4_RESET

#define DMA_MPU_BAR4_RESET _u(0x00000000)

◆ DMA_MPU_BAR5_ADDR_ACCESS

#define DMA_MPU_BAR5_ADDR_ACCESS "RW"

◆ DMA_MPU_BAR5_ADDR_BITS

#define DMA_MPU_BAR5_ADDR_BITS _u(0xffffffe0)

◆ DMA_MPU_BAR5_ADDR_LSB

#define DMA_MPU_BAR5_ADDR_LSB _u(5)

◆ DMA_MPU_BAR5_ADDR_MSB

#define DMA_MPU_BAR5_ADDR_MSB _u(31)

◆ DMA_MPU_BAR5_ADDR_RESET

#define DMA_MPU_BAR5_ADDR_RESET _u(0x0000000)

◆ DMA_MPU_BAR5_BITS

#define DMA_MPU_BAR5_BITS _u(0xffffffe0)

◆ DMA_MPU_BAR5_OFFSET

#define DMA_MPU_BAR5_OFFSET _u(0x0000052c)

◆ DMA_MPU_BAR5_RESET

#define DMA_MPU_BAR5_RESET _u(0x00000000)

◆ DMA_MPU_BAR6_ADDR_ACCESS

#define DMA_MPU_BAR6_ADDR_ACCESS "RW"

◆ DMA_MPU_BAR6_ADDR_BITS

#define DMA_MPU_BAR6_ADDR_BITS _u(0xffffffe0)

◆ DMA_MPU_BAR6_ADDR_LSB

#define DMA_MPU_BAR6_ADDR_LSB _u(5)

◆ DMA_MPU_BAR6_ADDR_MSB

#define DMA_MPU_BAR6_ADDR_MSB _u(31)

◆ DMA_MPU_BAR6_ADDR_RESET

#define DMA_MPU_BAR6_ADDR_RESET _u(0x0000000)

◆ DMA_MPU_BAR6_BITS

#define DMA_MPU_BAR6_BITS _u(0xffffffe0)

◆ DMA_MPU_BAR6_OFFSET

#define DMA_MPU_BAR6_OFFSET _u(0x00000534)

◆ DMA_MPU_BAR6_RESET

#define DMA_MPU_BAR6_RESET _u(0x00000000)

◆ DMA_MPU_BAR7_ADDR_ACCESS

#define DMA_MPU_BAR7_ADDR_ACCESS "RW"

◆ DMA_MPU_BAR7_ADDR_BITS

#define DMA_MPU_BAR7_ADDR_BITS _u(0xffffffe0)

◆ DMA_MPU_BAR7_ADDR_LSB

#define DMA_MPU_BAR7_ADDR_LSB _u(5)

◆ DMA_MPU_BAR7_ADDR_MSB

#define DMA_MPU_BAR7_ADDR_MSB _u(31)

◆ DMA_MPU_BAR7_ADDR_RESET

#define DMA_MPU_BAR7_ADDR_RESET _u(0x0000000)

◆ DMA_MPU_BAR7_BITS

#define DMA_MPU_BAR7_BITS _u(0xffffffe0)

◆ DMA_MPU_BAR7_OFFSET

#define DMA_MPU_BAR7_OFFSET _u(0x0000053c)

◆ DMA_MPU_BAR7_RESET

#define DMA_MPU_BAR7_RESET _u(0x00000000)

◆ DMA_MPU_CTRL_BITS

#define DMA_MPU_CTRL_BITS _u(0x0000000e)

◆ DMA_MPU_CTRL_NS_HIDE_ADDR_ACCESS

#define DMA_MPU_CTRL_NS_HIDE_ADDR_ACCESS "RW"

◆ DMA_MPU_CTRL_NS_HIDE_ADDR_BITS

#define DMA_MPU_CTRL_NS_HIDE_ADDR_BITS _u(0x00000008)

◆ DMA_MPU_CTRL_NS_HIDE_ADDR_LSB

#define DMA_MPU_CTRL_NS_HIDE_ADDR_LSB _u(3)

◆ DMA_MPU_CTRL_NS_HIDE_ADDR_MSB

#define DMA_MPU_CTRL_NS_HIDE_ADDR_MSB _u(3)

◆ DMA_MPU_CTRL_NS_HIDE_ADDR_RESET

#define DMA_MPU_CTRL_NS_HIDE_ADDR_RESET _u(0x0)

◆ DMA_MPU_CTRL_OFFSET

#define DMA_MPU_CTRL_OFFSET _u(0x00000500)

◆ DMA_MPU_CTRL_P_ACCESS

#define DMA_MPU_CTRL_P_ACCESS "RW"

◆ DMA_MPU_CTRL_P_BITS

#define DMA_MPU_CTRL_P_BITS _u(0x00000002)

◆ DMA_MPU_CTRL_P_LSB

#define DMA_MPU_CTRL_P_LSB _u(1)

◆ DMA_MPU_CTRL_P_MSB

#define DMA_MPU_CTRL_P_MSB _u(1)

◆ DMA_MPU_CTRL_P_RESET

#define DMA_MPU_CTRL_P_RESET _u(0x0)

◆ DMA_MPU_CTRL_RESET

#define DMA_MPU_CTRL_RESET _u(0x00000000)

◆ DMA_MPU_CTRL_S_ACCESS

#define DMA_MPU_CTRL_S_ACCESS "RW"

◆ DMA_MPU_CTRL_S_BITS

#define DMA_MPU_CTRL_S_BITS _u(0x00000004)

◆ DMA_MPU_CTRL_S_LSB

#define DMA_MPU_CTRL_S_LSB _u(2)

◆ DMA_MPU_CTRL_S_MSB

#define DMA_MPU_CTRL_S_MSB _u(2)

◆ DMA_MPU_CTRL_S_RESET

#define DMA_MPU_CTRL_S_RESET _u(0x0)

◆ DMA_MPU_LAR0_ADDR_ACCESS

#define DMA_MPU_LAR0_ADDR_ACCESS "RW"

◆ DMA_MPU_LAR0_ADDR_BITS

#define DMA_MPU_LAR0_ADDR_BITS _u(0xffffffe0)

◆ DMA_MPU_LAR0_ADDR_LSB

#define DMA_MPU_LAR0_ADDR_LSB _u(5)

◆ DMA_MPU_LAR0_ADDR_MSB

#define DMA_MPU_LAR0_ADDR_MSB _u(31)

◆ DMA_MPU_LAR0_ADDR_RESET

#define DMA_MPU_LAR0_ADDR_RESET _u(0x0000000)

◆ DMA_MPU_LAR0_BITS

#define DMA_MPU_LAR0_BITS _u(0xffffffe7)

◆ DMA_MPU_LAR0_EN_ACCESS

#define DMA_MPU_LAR0_EN_ACCESS "RW"

◆ DMA_MPU_LAR0_EN_BITS

#define DMA_MPU_LAR0_EN_BITS _u(0x00000001)

◆ DMA_MPU_LAR0_EN_LSB

#define DMA_MPU_LAR0_EN_LSB _u(0)

◆ DMA_MPU_LAR0_EN_MSB

#define DMA_MPU_LAR0_EN_MSB _u(0)

◆ DMA_MPU_LAR0_EN_RESET

#define DMA_MPU_LAR0_EN_RESET _u(0x0)

◆ DMA_MPU_LAR0_OFFSET

#define DMA_MPU_LAR0_OFFSET _u(0x00000508)

◆ DMA_MPU_LAR0_P_ACCESS

#define DMA_MPU_LAR0_P_ACCESS "RW"

◆ DMA_MPU_LAR0_P_BITS

#define DMA_MPU_LAR0_P_BITS _u(0x00000002)

◆ DMA_MPU_LAR0_P_LSB

#define DMA_MPU_LAR0_P_LSB _u(1)

◆ DMA_MPU_LAR0_P_MSB

#define DMA_MPU_LAR0_P_MSB _u(1)

◆ DMA_MPU_LAR0_P_RESET

#define DMA_MPU_LAR0_P_RESET _u(0x0)

◆ DMA_MPU_LAR0_RESET

#define DMA_MPU_LAR0_RESET _u(0x00000000)

◆ DMA_MPU_LAR0_S_ACCESS

#define DMA_MPU_LAR0_S_ACCESS "RW"

◆ DMA_MPU_LAR0_S_BITS

#define DMA_MPU_LAR0_S_BITS _u(0x00000004)

◆ DMA_MPU_LAR0_S_LSB

#define DMA_MPU_LAR0_S_LSB _u(2)

◆ DMA_MPU_LAR0_S_MSB

#define DMA_MPU_LAR0_S_MSB _u(2)

◆ DMA_MPU_LAR0_S_RESET

#define DMA_MPU_LAR0_S_RESET _u(0x0)

◆ DMA_MPU_LAR1_ADDR_ACCESS

#define DMA_MPU_LAR1_ADDR_ACCESS "RW"

◆ DMA_MPU_LAR1_ADDR_BITS

#define DMA_MPU_LAR1_ADDR_BITS _u(0xffffffe0)

◆ DMA_MPU_LAR1_ADDR_LSB

#define DMA_MPU_LAR1_ADDR_LSB _u(5)

◆ DMA_MPU_LAR1_ADDR_MSB

#define DMA_MPU_LAR1_ADDR_MSB _u(31)

◆ DMA_MPU_LAR1_ADDR_RESET

#define DMA_MPU_LAR1_ADDR_RESET _u(0x0000000)

◆ DMA_MPU_LAR1_BITS

#define DMA_MPU_LAR1_BITS _u(0xffffffe7)

◆ DMA_MPU_LAR1_EN_ACCESS

#define DMA_MPU_LAR1_EN_ACCESS "RW"

◆ DMA_MPU_LAR1_EN_BITS

#define DMA_MPU_LAR1_EN_BITS _u(0x00000001)

◆ DMA_MPU_LAR1_EN_LSB

#define DMA_MPU_LAR1_EN_LSB _u(0)

◆ DMA_MPU_LAR1_EN_MSB

#define DMA_MPU_LAR1_EN_MSB _u(0)

◆ DMA_MPU_LAR1_EN_RESET

#define DMA_MPU_LAR1_EN_RESET _u(0x0)

◆ DMA_MPU_LAR1_OFFSET

#define DMA_MPU_LAR1_OFFSET _u(0x00000510)

◆ DMA_MPU_LAR1_P_ACCESS

#define DMA_MPU_LAR1_P_ACCESS "RW"

◆ DMA_MPU_LAR1_P_BITS

#define DMA_MPU_LAR1_P_BITS _u(0x00000002)

◆ DMA_MPU_LAR1_P_LSB

#define DMA_MPU_LAR1_P_LSB _u(1)

◆ DMA_MPU_LAR1_P_MSB

#define DMA_MPU_LAR1_P_MSB _u(1)

◆ DMA_MPU_LAR1_P_RESET

#define DMA_MPU_LAR1_P_RESET _u(0x0)

◆ DMA_MPU_LAR1_RESET

#define DMA_MPU_LAR1_RESET _u(0x00000000)

◆ DMA_MPU_LAR1_S_ACCESS

#define DMA_MPU_LAR1_S_ACCESS "RW"

◆ DMA_MPU_LAR1_S_BITS

#define DMA_MPU_LAR1_S_BITS _u(0x00000004)

◆ DMA_MPU_LAR1_S_LSB

#define DMA_MPU_LAR1_S_LSB _u(2)

◆ DMA_MPU_LAR1_S_MSB

#define DMA_MPU_LAR1_S_MSB _u(2)

◆ DMA_MPU_LAR1_S_RESET

#define DMA_MPU_LAR1_S_RESET _u(0x0)

◆ DMA_MPU_LAR2_ADDR_ACCESS

#define DMA_MPU_LAR2_ADDR_ACCESS "RW"

◆ DMA_MPU_LAR2_ADDR_BITS

#define DMA_MPU_LAR2_ADDR_BITS _u(0xffffffe0)

◆ DMA_MPU_LAR2_ADDR_LSB

#define DMA_MPU_LAR2_ADDR_LSB _u(5)

◆ DMA_MPU_LAR2_ADDR_MSB

#define DMA_MPU_LAR2_ADDR_MSB _u(31)

◆ DMA_MPU_LAR2_ADDR_RESET

#define DMA_MPU_LAR2_ADDR_RESET _u(0x0000000)

◆ DMA_MPU_LAR2_BITS

#define DMA_MPU_LAR2_BITS _u(0xffffffe7)

◆ DMA_MPU_LAR2_EN_ACCESS

#define DMA_MPU_LAR2_EN_ACCESS "RW"

◆ DMA_MPU_LAR2_EN_BITS

#define DMA_MPU_LAR2_EN_BITS _u(0x00000001)

◆ DMA_MPU_LAR2_EN_LSB

#define DMA_MPU_LAR2_EN_LSB _u(0)

◆ DMA_MPU_LAR2_EN_MSB

#define DMA_MPU_LAR2_EN_MSB _u(0)

◆ DMA_MPU_LAR2_EN_RESET

#define DMA_MPU_LAR2_EN_RESET _u(0x0)

◆ DMA_MPU_LAR2_OFFSET

#define DMA_MPU_LAR2_OFFSET _u(0x00000518)

◆ DMA_MPU_LAR2_P_ACCESS

#define DMA_MPU_LAR2_P_ACCESS "RW"

◆ DMA_MPU_LAR2_P_BITS

#define DMA_MPU_LAR2_P_BITS _u(0x00000002)

◆ DMA_MPU_LAR2_P_LSB

#define DMA_MPU_LAR2_P_LSB _u(1)

◆ DMA_MPU_LAR2_P_MSB

#define DMA_MPU_LAR2_P_MSB _u(1)

◆ DMA_MPU_LAR2_P_RESET

#define DMA_MPU_LAR2_P_RESET _u(0x0)

◆ DMA_MPU_LAR2_RESET

#define DMA_MPU_LAR2_RESET _u(0x00000000)

◆ DMA_MPU_LAR2_S_ACCESS

#define DMA_MPU_LAR2_S_ACCESS "RW"

◆ DMA_MPU_LAR2_S_BITS

#define DMA_MPU_LAR2_S_BITS _u(0x00000004)

◆ DMA_MPU_LAR2_S_LSB

#define DMA_MPU_LAR2_S_LSB _u(2)

◆ DMA_MPU_LAR2_S_MSB

#define DMA_MPU_LAR2_S_MSB _u(2)

◆ DMA_MPU_LAR2_S_RESET

#define DMA_MPU_LAR2_S_RESET _u(0x0)

◆ DMA_MPU_LAR3_ADDR_ACCESS

#define DMA_MPU_LAR3_ADDR_ACCESS "RW"

◆ DMA_MPU_LAR3_ADDR_BITS

#define DMA_MPU_LAR3_ADDR_BITS _u(0xffffffe0)

◆ DMA_MPU_LAR3_ADDR_LSB

#define DMA_MPU_LAR3_ADDR_LSB _u(5)

◆ DMA_MPU_LAR3_ADDR_MSB

#define DMA_MPU_LAR3_ADDR_MSB _u(31)

◆ DMA_MPU_LAR3_ADDR_RESET

#define DMA_MPU_LAR3_ADDR_RESET _u(0x0000000)

◆ DMA_MPU_LAR3_BITS

#define DMA_MPU_LAR3_BITS _u(0xffffffe7)

◆ DMA_MPU_LAR3_EN_ACCESS

#define DMA_MPU_LAR3_EN_ACCESS "RW"

◆ DMA_MPU_LAR3_EN_BITS

#define DMA_MPU_LAR3_EN_BITS _u(0x00000001)

◆ DMA_MPU_LAR3_EN_LSB

#define DMA_MPU_LAR3_EN_LSB _u(0)

◆ DMA_MPU_LAR3_EN_MSB

#define DMA_MPU_LAR3_EN_MSB _u(0)

◆ DMA_MPU_LAR3_EN_RESET

#define DMA_MPU_LAR3_EN_RESET _u(0x0)

◆ DMA_MPU_LAR3_OFFSET

#define DMA_MPU_LAR3_OFFSET _u(0x00000520)

◆ DMA_MPU_LAR3_P_ACCESS

#define DMA_MPU_LAR3_P_ACCESS "RW"

◆ DMA_MPU_LAR3_P_BITS

#define DMA_MPU_LAR3_P_BITS _u(0x00000002)

◆ DMA_MPU_LAR3_P_LSB

#define DMA_MPU_LAR3_P_LSB _u(1)

◆ DMA_MPU_LAR3_P_MSB

#define DMA_MPU_LAR3_P_MSB _u(1)

◆ DMA_MPU_LAR3_P_RESET

#define DMA_MPU_LAR3_P_RESET _u(0x0)

◆ DMA_MPU_LAR3_RESET

#define DMA_MPU_LAR3_RESET _u(0x00000000)

◆ DMA_MPU_LAR3_S_ACCESS

#define DMA_MPU_LAR3_S_ACCESS "RW"

◆ DMA_MPU_LAR3_S_BITS

#define DMA_MPU_LAR3_S_BITS _u(0x00000004)

◆ DMA_MPU_LAR3_S_LSB

#define DMA_MPU_LAR3_S_LSB _u(2)

◆ DMA_MPU_LAR3_S_MSB

#define DMA_MPU_LAR3_S_MSB _u(2)

◆ DMA_MPU_LAR3_S_RESET

#define DMA_MPU_LAR3_S_RESET _u(0x0)

◆ DMA_MPU_LAR4_ADDR_ACCESS

#define DMA_MPU_LAR4_ADDR_ACCESS "RW"

◆ DMA_MPU_LAR4_ADDR_BITS

#define DMA_MPU_LAR4_ADDR_BITS _u(0xffffffe0)

◆ DMA_MPU_LAR4_ADDR_LSB

#define DMA_MPU_LAR4_ADDR_LSB _u(5)

◆ DMA_MPU_LAR4_ADDR_MSB

#define DMA_MPU_LAR4_ADDR_MSB _u(31)

◆ DMA_MPU_LAR4_ADDR_RESET

#define DMA_MPU_LAR4_ADDR_RESET _u(0x0000000)

◆ DMA_MPU_LAR4_BITS

#define DMA_MPU_LAR4_BITS _u(0xffffffe7)

◆ DMA_MPU_LAR4_EN_ACCESS

#define DMA_MPU_LAR4_EN_ACCESS "RW"

◆ DMA_MPU_LAR4_EN_BITS

#define DMA_MPU_LAR4_EN_BITS _u(0x00000001)

◆ DMA_MPU_LAR4_EN_LSB

#define DMA_MPU_LAR4_EN_LSB _u(0)

◆ DMA_MPU_LAR4_EN_MSB

#define DMA_MPU_LAR4_EN_MSB _u(0)

◆ DMA_MPU_LAR4_EN_RESET

#define DMA_MPU_LAR4_EN_RESET _u(0x0)

◆ DMA_MPU_LAR4_OFFSET

#define DMA_MPU_LAR4_OFFSET _u(0x00000528)

◆ DMA_MPU_LAR4_P_ACCESS

#define DMA_MPU_LAR4_P_ACCESS "RW"

◆ DMA_MPU_LAR4_P_BITS

#define DMA_MPU_LAR4_P_BITS _u(0x00000002)

◆ DMA_MPU_LAR4_P_LSB

#define DMA_MPU_LAR4_P_LSB _u(1)

◆ DMA_MPU_LAR4_P_MSB

#define DMA_MPU_LAR4_P_MSB _u(1)

◆ DMA_MPU_LAR4_P_RESET

#define DMA_MPU_LAR4_P_RESET _u(0x0)

◆ DMA_MPU_LAR4_RESET

#define DMA_MPU_LAR4_RESET _u(0x00000000)

◆ DMA_MPU_LAR4_S_ACCESS

#define DMA_MPU_LAR4_S_ACCESS "RW"

◆ DMA_MPU_LAR4_S_BITS

#define DMA_MPU_LAR4_S_BITS _u(0x00000004)

◆ DMA_MPU_LAR4_S_LSB

#define DMA_MPU_LAR4_S_LSB _u(2)

◆ DMA_MPU_LAR4_S_MSB

#define DMA_MPU_LAR4_S_MSB _u(2)

◆ DMA_MPU_LAR4_S_RESET

#define DMA_MPU_LAR4_S_RESET _u(0x0)

◆ DMA_MPU_LAR5_ADDR_ACCESS

#define DMA_MPU_LAR5_ADDR_ACCESS "RW"

◆ DMA_MPU_LAR5_ADDR_BITS

#define DMA_MPU_LAR5_ADDR_BITS _u(0xffffffe0)

◆ DMA_MPU_LAR5_ADDR_LSB

#define DMA_MPU_LAR5_ADDR_LSB _u(5)

◆ DMA_MPU_LAR5_ADDR_MSB

#define DMA_MPU_LAR5_ADDR_MSB _u(31)

◆ DMA_MPU_LAR5_ADDR_RESET

#define DMA_MPU_LAR5_ADDR_RESET _u(0x0000000)

◆ DMA_MPU_LAR5_BITS

#define DMA_MPU_LAR5_BITS _u(0xffffffe7)

◆ DMA_MPU_LAR5_EN_ACCESS

#define DMA_MPU_LAR5_EN_ACCESS "RW"

◆ DMA_MPU_LAR5_EN_BITS

#define DMA_MPU_LAR5_EN_BITS _u(0x00000001)

◆ DMA_MPU_LAR5_EN_LSB

#define DMA_MPU_LAR5_EN_LSB _u(0)

◆ DMA_MPU_LAR5_EN_MSB

#define DMA_MPU_LAR5_EN_MSB _u(0)

◆ DMA_MPU_LAR5_EN_RESET

#define DMA_MPU_LAR5_EN_RESET _u(0x0)

◆ DMA_MPU_LAR5_OFFSET

#define DMA_MPU_LAR5_OFFSET _u(0x00000530)

◆ DMA_MPU_LAR5_P_ACCESS

#define DMA_MPU_LAR5_P_ACCESS "RW"

◆ DMA_MPU_LAR5_P_BITS

#define DMA_MPU_LAR5_P_BITS _u(0x00000002)

◆ DMA_MPU_LAR5_P_LSB

#define DMA_MPU_LAR5_P_LSB _u(1)

◆ DMA_MPU_LAR5_P_MSB

#define DMA_MPU_LAR5_P_MSB _u(1)

◆ DMA_MPU_LAR5_P_RESET

#define DMA_MPU_LAR5_P_RESET _u(0x0)

◆ DMA_MPU_LAR5_RESET

#define DMA_MPU_LAR5_RESET _u(0x00000000)

◆ DMA_MPU_LAR5_S_ACCESS

#define DMA_MPU_LAR5_S_ACCESS "RW"

◆ DMA_MPU_LAR5_S_BITS

#define DMA_MPU_LAR5_S_BITS _u(0x00000004)

◆ DMA_MPU_LAR5_S_LSB

#define DMA_MPU_LAR5_S_LSB _u(2)

◆ DMA_MPU_LAR5_S_MSB

#define DMA_MPU_LAR5_S_MSB _u(2)

◆ DMA_MPU_LAR5_S_RESET

#define DMA_MPU_LAR5_S_RESET _u(0x0)

◆ DMA_MPU_LAR6_ADDR_ACCESS

#define DMA_MPU_LAR6_ADDR_ACCESS "RW"

◆ DMA_MPU_LAR6_ADDR_BITS

#define DMA_MPU_LAR6_ADDR_BITS _u(0xffffffe0)

◆ DMA_MPU_LAR6_ADDR_LSB

#define DMA_MPU_LAR6_ADDR_LSB _u(5)

◆ DMA_MPU_LAR6_ADDR_MSB

#define DMA_MPU_LAR6_ADDR_MSB _u(31)

◆ DMA_MPU_LAR6_ADDR_RESET

#define DMA_MPU_LAR6_ADDR_RESET _u(0x0000000)

◆ DMA_MPU_LAR6_BITS

#define DMA_MPU_LAR6_BITS _u(0xffffffe7)

◆ DMA_MPU_LAR6_EN_ACCESS

#define DMA_MPU_LAR6_EN_ACCESS "RW"

◆ DMA_MPU_LAR6_EN_BITS

#define DMA_MPU_LAR6_EN_BITS _u(0x00000001)

◆ DMA_MPU_LAR6_EN_LSB

#define DMA_MPU_LAR6_EN_LSB _u(0)

◆ DMA_MPU_LAR6_EN_MSB

#define DMA_MPU_LAR6_EN_MSB _u(0)

◆ DMA_MPU_LAR6_EN_RESET

#define DMA_MPU_LAR6_EN_RESET _u(0x0)

◆ DMA_MPU_LAR6_OFFSET

#define DMA_MPU_LAR6_OFFSET _u(0x00000538)

◆ DMA_MPU_LAR6_P_ACCESS

#define DMA_MPU_LAR6_P_ACCESS "RW"

◆ DMA_MPU_LAR6_P_BITS

#define DMA_MPU_LAR6_P_BITS _u(0x00000002)

◆ DMA_MPU_LAR6_P_LSB

#define DMA_MPU_LAR6_P_LSB _u(1)

◆ DMA_MPU_LAR6_P_MSB

#define DMA_MPU_LAR6_P_MSB _u(1)

◆ DMA_MPU_LAR6_P_RESET

#define DMA_MPU_LAR6_P_RESET _u(0x0)

◆ DMA_MPU_LAR6_RESET

#define DMA_MPU_LAR6_RESET _u(0x00000000)

◆ DMA_MPU_LAR6_S_ACCESS

#define DMA_MPU_LAR6_S_ACCESS "RW"

◆ DMA_MPU_LAR6_S_BITS

#define DMA_MPU_LAR6_S_BITS _u(0x00000004)

◆ DMA_MPU_LAR6_S_LSB

#define DMA_MPU_LAR6_S_LSB _u(2)

◆ DMA_MPU_LAR6_S_MSB

#define DMA_MPU_LAR6_S_MSB _u(2)

◆ DMA_MPU_LAR6_S_RESET

#define DMA_MPU_LAR6_S_RESET _u(0x0)

◆ DMA_MPU_LAR7_ADDR_ACCESS

#define DMA_MPU_LAR7_ADDR_ACCESS "RW"

◆ DMA_MPU_LAR7_ADDR_BITS

#define DMA_MPU_LAR7_ADDR_BITS _u(0xffffffe0)

◆ DMA_MPU_LAR7_ADDR_LSB

#define DMA_MPU_LAR7_ADDR_LSB _u(5)

◆ DMA_MPU_LAR7_ADDR_MSB

#define DMA_MPU_LAR7_ADDR_MSB _u(31)

◆ DMA_MPU_LAR7_ADDR_RESET

#define DMA_MPU_LAR7_ADDR_RESET _u(0x0000000)

◆ DMA_MPU_LAR7_BITS

#define DMA_MPU_LAR7_BITS _u(0xffffffe7)

◆ DMA_MPU_LAR7_EN_ACCESS

#define DMA_MPU_LAR7_EN_ACCESS "RW"

◆ DMA_MPU_LAR7_EN_BITS

#define DMA_MPU_LAR7_EN_BITS _u(0x00000001)

◆ DMA_MPU_LAR7_EN_LSB

#define DMA_MPU_LAR7_EN_LSB _u(0)

◆ DMA_MPU_LAR7_EN_MSB

#define DMA_MPU_LAR7_EN_MSB _u(0)

◆ DMA_MPU_LAR7_EN_RESET

#define DMA_MPU_LAR7_EN_RESET _u(0x0)

◆ DMA_MPU_LAR7_OFFSET

#define DMA_MPU_LAR7_OFFSET _u(0x00000540)

◆ DMA_MPU_LAR7_P_ACCESS

#define DMA_MPU_LAR7_P_ACCESS "RW"

◆ DMA_MPU_LAR7_P_BITS

#define DMA_MPU_LAR7_P_BITS _u(0x00000002)

◆ DMA_MPU_LAR7_P_LSB

#define DMA_MPU_LAR7_P_LSB _u(1)

◆ DMA_MPU_LAR7_P_MSB

#define DMA_MPU_LAR7_P_MSB _u(1)

◆ DMA_MPU_LAR7_P_RESET

#define DMA_MPU_LAR7_P_RESET _u(0x0)

◆ DMA_MPU_LAR7_RESET

#define DMA_MPU_LAR7_RESET _u(0x00000000)

◆ DMA_MPU_LAR7_S_ACCESS

#define DMA_MPU_LAR7_S_ACCESS "RW"

◆ DMA_MPU_LAR7_S_BITS

#define DMA_MPU_LAR7_S_BITS _u(0x00000004)

◆ DMA_MPU_LAR7_S_LSB

#define DMA_MPU_LAR7_S_LSB _u(2)

◆ DMA_MPU_LAR7_S_MSB

#define DMA_MPU_LAR7_S_MSB _u(2)

◆ DMA_MPU_LAR7_S_RESET

#define DMA_MPU_LAR7_S_RESET _u(0x0)

◆ DMA_MULTI_CHAN_TRIGGER_ACCESS

#define DMA_MULTI_CHAN_TRIGGER_ACCESS "SC"

◆ DMA_MULTI_CHAN_TRIGGER_BITS

#define DMA_MULTI_CHAN_TRIGGER_BITS _u(0x0000ffff)

◆ DMA_MULTI_CHAN_TRIGGER_LSB

#define DMA_MULTI_CHAN_TRIGGER_LSB _u(0)

◆ DMA_MULTI_CHAN_TRIGGER_MSB

#define DMA_MULTI_CHAN_TRIGGER_MSB _u(15)

◆ DMA_MULTI_CHAN_TRIGGER_OFFSET

#define DMA_MULTI_CHAN_TRIGGER_OFFSET _u(0x00000450)

◆ DMA_MULTI_CHAN_TRIGGER_RESET

#define DMA_MULTI_CHAN_TRIGGER_RESET _u(0x00000000)

◆ DMA_N_CHANNELS_ACCESS

#define DMA_N_CHANNELS_ACCESS "RO"

◆ DMA_N_CHANNELS_BITS

#define DMA_N_CHANNELS_BITS _u(0x0000001f)

◆ DMA_N_CHANNELS_LSB

#define DMA_N_CHANNELS_LSB _u(0)

◆ DMA_N_CHANNELS_MSB

#define DMA_N_CHANNELS_MSB _u(4)

◆ DMA_N_CHANNELS_OFFSET

#define DMA_N_CHANNELS_OFFSET _u(0x00000468)

◆ DMA_N_CHANNELS_RESET

#define DMA_N_CHANNELS_RESET "-"

◆ DMA_SECCFG_CH0_BITS

#define DMA_SECCFG_CH0_BITS _u(0x00000007)

◆ DMA_SECCFG_CH0_LOCK_ACCESS

#define DMA_SECCFG_CH0_LOCK_ACCESS "RW"

◆ DMA_SECCFG_CH0_LOCK_BITS

#define DMA_SECCFG_CH0_LOCK_BITS _u(0x00000004)

◆ DMA_SECCFG_CH0_LOCK_LSB

#define DMA_SECCFG_CH0_LOCK_LSB _u(2)

◆ DMA_SECCFG_CH0_LOCK_MSB

#define DMA_SECCFG_CH0_LOCK_MSB _u(2)

◆ DMA_SECCFG_CH0_LOCK_RESET

#define DMA_SECCFG_CH0_LOCK_RESET _u(0x0)

◆ DMA_SECCFG_CH0_OFFSET

#define DMA_SECCFG_CH0_OFFSET _u(0x00000480)

◆ DMA_SECCFG_CH0_P_ACCESS

#define DMA_SECCFG_CH0_P_ACCESS "RW"

◆ DMA_SECCFG_CH0_P_BITS

#define DMA_SECCFG_CH0_P_BITS _u(0x00000001)

◆ DMA_SECCFG_CH0_P_LSB

#define DMA_SECCFG_CH0_P_LSB _u(0)

◆ DMA_SECCFG_CH0_P_MSB

#define DMA_SECCFG_CH0_P_MSB _u(0)

◆ DMA_SECCFG_CH0_P_RESET

#define DMA_SECCFG_CH0_P_RESET _u(0x1)

◆ DMA_SECCFG_CH0_RESET

#define DMA_SECCFG_CH0_RESET _u(0x00000003)

◆ DMA_SECCFG_CH0_S_ACCESS

#define DMA_SECCFG_CH0_S_ACCESS "RW"

◆ DMA_SECCFG_CH0_S_BITS

#define DMA_SECCFG_CH0_S_BITS _u(0x00000002)

◆ DMA_SECCFG_CH0_S_LSB

#define DMA_SECCFG_CH0_S_LSB _u(1)

◆ DMA_SECCFG_CH0_S_MSB

#define DMA_SECCFG_CH0_S_MSB _u(1)

◆ DMA_SECCFG_CH0_S_RESET

#define DMA_SECCFG_CH0_S_RESET _u(0x1)

◆ DMA_SECCFG_CH10_BITS

#define DMA_SECCFG_CH10_BITS _u(0x00000007)

◆ DMA_SECCFG_CH10_LOCK_ACCESS

#define DMA_SECCFG_CH10_LOCK_ACCESS "RW"

◆ DMA_SECCFG_CH10_LOCK_BITS

#define DMA_SECCFG_CH10_LOCK_BITS _u(0x00000004)

◆ DMA_SECCFG_CH10_LOCK_LSB

#define DMA_SECCFG_CH10_LOCK_LSB _u(2)

◆ DMA_SECCFG_CH10_LOCK_MSB

#define DMA_SECCFG_CH10_LOCK_MSB _u(2)

◆ DMA_SECCFG_CH10_LOCK_RESET

#define DMA_SECCFG_CH10_LOCK_RESET _u(0x0)

◆ DMA_SECCFG_CH10_OFFSET

#define DMA_SECCFG_CH10_OFFSET _u(0x000004a8)

◆ DMA_SECCFG_CH10_P_ACCESS

#define DMA_SECCFG_CH10_P_ACCESS "RW"

◆ DMA_SECCFG_CH10_P_BITS

#define DMA_SECCFG_CH10_P_BITS _u(0x00000001)

◆ DMA_SECCFG_CH10_P_LSB

#define DMA_SECCFG_CH10_P_LSB _u(0)

◆ DMA_SECCFG_CH10_P_MSB

#define DMA_SECCFG_CH10_P_MSB _u(0)

◆ DMA_SECCFG_CH10_P_RESET

#define DMA_SECCFG_CH10_P_RESET _u(0x1)

◆ DMA_SECCFG_CH10_RESET

#define DMA_SECCFG_CH10_RESET _u(0x00000003)

◆ DMA_SECCFG_CH10_S_ACCESS

#define DMA_SECCFG_CH10_S_ACCESS "RW"

◆ DMA_SECCFG_CH10_S_BITS

#define DMA_SECCFG_CH10_S_BITS _u(0x00000002)

◆ DMA_SECCFG_CH10_S_LSB

#define DMA_SECCFG_CH10_S_LSB _u(1)

◆ DMA_SECCFG_CH10_S_MSB

#define DMA_SECCFG_CH10_S_MSB _u(1)

◆ DMA_SECCFG_CH10_S_RESET

#define DMA_SECCFG_CH10_S_RESET _u(0x1)

◆ DMA_SECCFG_CH11_BITS

#define DMA_SECCFG_CH11_BITS _u(0x00000007)

◆ DMA_SECCFG_CH11_LOCK_ACCESS

#define DMA_SECCFG_CH11_LOCK_ACCESS "RW"

◆ DMA_SECCFG_CH11_LOCK_BITS

#define DMA_SECCFG_CH11_LOCK_BITS _u(0x00000004)

◆ DMA_SECCFG_CH11_LOCK_LSB

#define DMA_SECCFG_CH11_LOCK_LSB _u(2)

◆ DMA_SECCFG_CH11_LOCK_MSB

#define DMA_SECCFG_CH11_LOCK_MSB _u(2)

◆ DMA_SECCFG_CH11_LOCK_RESET

#define DMA_SECCFG_CH11_LOCK_RESET _u(0x0)

◆ DMA_SECCFG_CH11_OFFSET

#define DMA_SECCFG_CH11_OFFSET _u(0x000004ac)

◆ DMA_SECCFG_CH11_P_ACCESS

#define DMA_SECCFG_CH11_P_ACCESS "RW"

◆ DMA_SECCFG_CH11_P_BITS

#define DMA_SECCFG_CH11_P_BITS _u(0x00000001)

◆ DMA_SECCFG_CH11_P_LSB

#define DMA_SECCFG_CH11_P_LSB _u(0)

◆ DMA_SECCFG_CH11_P_MSB

#define DMA_SECCFG_CH11_P_MSB _u(0)

◆ DMA_SECCFG_CH11_P_RESET

#define DMA_SECCFG_CH11_P_RESET _u(0x1)

◆ DMA_SECCFG_CH11_RESET

#define DMA_SECCFG_CH11_RESET _u(0x00000003)

◆ DMA_SECCFG_CH11_S_ACCESS

#define DMA_SECCFG_CH11_S_ACCESS "RW"

◆ DMA_SECCFG_CH11_S_BITS

#define DMA_SECCFG_CH11_S_BITS _u(0x00000002)

◆ DMA_SECCFG_CH11_S_LSB

#define DMA_SECCFG_CH11_S_LSB _u(1)

◆ DMA_SECCFG_CH11_S_MSB

#define DMA_SECCFG_CH11_S_MSB _u(1)

◆ DMA_SECCFG_CH11_S_RESET

#define DMA_SECCFG_CH11_S_RESET _u(0x1)

◆ DMA_SECCFG_CH12_BITS

#define DMA_SECCFG_CH12_BITS _u(0x00000007)

◆ DMA_SECCFG_CH12_LOCK_ACCESS

#define DMA_SECCFG_CH12_LOCK_ACCESS "RW"

◆ DMA_SECCFG_CH12_LOCK_BITS

#define DMA_SECCFG_CH12_LOCK_BITS _u(0x00000004)

◆ DMA_SECCFG_CH12_LOCK_LSB

#define DMA_SECCFG_CH12_LOCK_LSB _u(2)

◆ DMA_SECCFG_CH12_LOCK_MSB

#define DMA_SECCFG_CH12_LOCK_MSB _u(2)

◆ DMA_SECCFG_CH12_LOCK_RESET

#define DMA_SECCFG_CH12_LOCK_RESET _u(0x0)

◆ DMA_SECCFG_CH12_OFFSET

#define DMA_SECCFG_CH12_OFFSET _u(0x000004b0)

◆ DMA_SECCFG_CH12_P_ACCESS

#define DMA_SECCFG_CH12_P_ACCESS "RW"

◆ DMA_SECCFG_CH12_P_BITS

#define DMA_SECCFG_CH12_P_BITS _u(0x00000001)

◆ DMA_SECCFG_CH12_P_LSB

#define DMA_SECCFG_CH12_P_LSB _u(0)

◆ DMA_SECCFG_CH12_P_MSB

#define DMA_SECCFG_CH12_P_MSB _u(0)

◆ DMA_SECCFG_CH12_P_RESET

#define DMA_SECCFG_CH12_P_RESET _u(0x1)

◆ DMA_SECCFG_CH12_RESET

#define DMA_SECCFG_CH12_RESET _u(0x00000003)

◆ DMA_SECCFG_CH12_S_ACCESS

#define DMA_SECCFG_CH12_S_ACCESS "RW"

◆ DMA_SECCFG_CH12_S_BITS

#define DMA_SECCFG_CH12_S_BITS _u(0x00000002)

◆ DMA_SECCFG_CH12_S_LSB

#define DMA_SECCFG_CH12_S_LSB _u(1)

◆ DMA_SECCFG_CH12_S_MSB

#define DMA_SECCFG_CH12_S_MSB _u(1)

◆ DMA_SECCFG_CH12_S_RESET

#define DMA_SECCFG_CH12_S_RESET _u(0x1)

◆ DMA_SECCFG_CH13_BITS

#define DMA_SECCFG_CH13_BITS _u(0x00000007)

◆ DMA_SECCFG_CH13_LOCK_ACCESS

#define DMA_SECCFG_CH13_LOCK_ACCESS "RW"

◆ DMA_SECCFG_CH13_LOCK_BITS

#define DMA_SECCFG_CH13_LOCK_BITS _u(0x00000004)

◆ DMA_SECCFG_CH13_LOCK_LSB

#define DMA_SECCFG_CH13_LOCK_LSB _u(2)

◆ DMA_SECCFG_CH13_LOCK_MSB

#define DMA_SECCFG_CH13_LOCK_MSB _u(2)

◆ DMA_SECCFG_CH13_LOCK_RESET

#define DMA_SECCFG_CH13_LOCK_RESET _u(0x0)

◆ DMA_SECCFG_CH13_OFFSET

#define DMA_SECCFG_CH13_OFFSET _u(0x000004b4)

◆ DMA_SECCFG_CH13_P_ACCESS

#define DMA_SECCFG_CH13_P_ACCESS "RW"

◆ DMA_SECCFG_CH13_P_BITS

#define DMA_SECCFG_CH13_P_BITS _u(0x00000001)

◆ DMA_SECCFG_CH13_P_LSB

#define DMA_SECCFG_CH13_P_LSB _u(0)

◆ DMA_SECCFG_CH13_P_MSB

#define DMA_SECCFG_CH13_P_MSB _u(0)

◆ DMA_SECCFG_CH13_P_RESET

#define DMA_SECCFG_CH13_P_RESET _u(0x1)

◆ DMA_SECCFG_CH13_RESET

#define DMA_SECCFG_CH13_RESET _u(0x00000003)

◆ DMA_SECCFG_CH13_S_ACCESS

#define DMA_SECCFG_CH13_S_ACCESS "RW"

◆ DMA_SECCFG_CH13_S_BITS

#define DMA_SECCFG_CH13_S_BITS _u(0x00000002)

◆ DMA_SECCFG_CH13_S_LSB

#define DMA_SECCFG_CH13_S_LSB _u(1)

◆ DMA_SECCFG_CH13_S_MSB

#define DMA_SECCFG_CH13_S_MSB _u(1)

◆ DMA_SECCFG_CH13_S_RESET

#define DMA_SECCFG_CH13_S_RESET _u(0x1)

◆ DMA_SECCFG_CH14_BITS

#define DMA_SECCFG_CH14_BITS _u(0x00000007)

◆ DMA_SECCFG_CH14_LOCK_ACCESS

#define DMA_SECCFG_CH14_LOCK_ACCESS "RW"

◆ DMA_SECCFG_CH14_LOCK_BITS

#define DMA_SECCFG_CH14_LOCK_BITS _u(0x00000004)

◆ DMA_SECCFG_CH14_LOCK_LSB

#define DMA_SECCFG_CH14_LOCK_LSB _u(2)

◆ DMA_SECCFG_CH14_LOCK_MSB

#define DMA_SECCFG_CH14_LOCK_MSB _u(2)

◆ DMA_SECCFG_CH14_LOCK_RESET

#define DMA_SECCFG_CH14_LOCK_RESET _u(0x0)

◆ DMA_SECCFG_CH14_OFFSET

#define DMA_SECCFG_CH14_OFFSET _u(0x000004b8)

◆ DMA_SECCFG_CH14_P_ACCESS

#define DMA_SECCFG_CH14_P_ACCESS "RW"

◆ DMA_SECCFG_CH14_P_BITS

#define DMA_SECCFG_CH14_P_BITS _u(0x00000001)

◆ DMA_SECCFG_CH14_P_LSB

#define DMA_SECCFG_CH14_P_LSB _u(0)

◆ DMA_SECCFG_CH14_P_MSB

#define DMA_SECCFG_CH14_P_MSB _u(0)

◆ DMA_SECCFG_CH14_P_RESET

#define DMA_SECCFG_CH14_P_RESET _u(0x1)

◆ DMA_SECCFG_CH14_RESET

#define DMA_SECCFG_CH14_RESET _u(0x00000003)

◆ DMA_SECCFG_CH14_S_ACCESS

#define DMA_SECCFG_CH14_S_ACCESS "RW"

◆ DMA_SECCFG_CH14_S_BITS

#define DMA_SECCFG_CH14_S_BITS _u(0x00000002)

◆ DMA_SECCFG_CH14_S_LSB

#define DMA_SECCFG_CH14_S_LSB _u(1)

◆ DMA_SECCFG_CH14_S_MSB

#define DMA_SECCFG_CH14_S_MSB _u(1)

◆ DMA_SECCFG_CH14_S_RESET

#define DMA_SECCFG_CH14_S_RESET _u(0x1)

◆ DMA_SECCFG_CH15_BITS

#define DMA_SECCFG_CH15_BITS _u(0x00000007)

◆ DMA_SECCFG_CH15_LOCK_ACCESS

#define DMA_SECCFG_CH15_LOCK_ACCESS "RW"

◆ DMA_SECCFG_CH15_LOCK_BITS

#define DMA_SECCFG_CH15_LOCK_BITS _u(0x00000004)

◆ DMA_SECCFG_CH15_LOCK_LSB

#define DMA_SECCFG_CH15_LOCK_LSB _u(2)

◆ DMA_SECCFG_CH15_LOCK_MSB

#define DMA_SECCFG_CH15_LOCK_MSB _u(2)

◆ DMA_SECCFG_CH15_LOCK_RESET

#define DMA_SECCFG_CH15_LOCK_RESET _u(0x0)

◆ DMA_SECCFG_CH15_OFFSET

#define DMA_SECCFG_CH15_OFFSET _u(0x000004bc)

◆ DMA_SECCFG_CH15_P_ACCESS

#define DMA_SECCFG_CH15_P_ACCESS "RW"

◆ DMA_SECCFG_CH15_P_BITS

#define DMA_SECCFG_CH15_P_BITS _u(0x00000001)

◆ DMA_SECCFG_CH15_P_LSB

#define DMA_SECCFG_CH15_P_LSB _u(0)

◆ DMA_SECCFG_CH15_P_MSB

#define DMA_SECCFG_CH15_P_MSB _u(0)

◆ DMA_SECCFG_CH15_P_RESET

#define DMA_SECCFG_CH15_P_RESET _u(0x1)

◆ DMA_SECCFG_CH15_RESET

#define DMA_SECCFG_CH15_RESET _u(0x00000003)

◆ DMA_SECCFG_CH15_S_ACCESS

#define DMA_SECCFG_CH15_S_ACCESS "RW"

◆ DMA_SECCFG_CH15_S_BITS

#define DMA_SECCFG_CH15_S_BITS _u(0x00000002)

◆ DMA_SECCFG_CH15_S_LSB

#define DMA_SECCFG_CH15_S_LSB _u(1)

◆ DMA_SECCFG_CH15_S_MSB

#define DMA_SECCFG_CH15_S_MSB _u(1)

◆ DMA_SECCFG_CH15_S_RESET

#define DMA_SECCFG_CH15_S_RESET _u(0x1)

◆ DMA_SECCFG_CH1_BITS

#define DMA_SECCFG_CH1_BITS _u(0x00000007)

◆ DMA_SECCFG_CH1_LOCK_ACCESS

#define DMA_SECCFG_CH1_LOCK_ACCESS "RW"

◆ DMA_SECCFG_CH1_LOCK_BITS

#define DMA_SECCFG_CH1_LOCK_BITS _u(0x00000004)

◆ DMA_SECCFG_CH1_LOCK_LSB

#define DMA_SECCFG_CH1_LOCK_LSB _u(2)

◆ DMA_SECCFG_CH1_LOCK_MSB

#define DMA_SECCFG_CH1_LOCK_MSB _u(2)

◆ DMA_SECCFG_CH1_LOCK_RESET

#define DMA_SECCFG_CH1_LOCK_RESET _u(0x0)

◆ DMA_SECCFG_CH1_OFFSET

#define DMA_SECCFG_CH1_OFFSET _u(0x00000484)

◆ DMA_SECCFG_CH1_P_ACCESS

#define DMA_SECCFG_CH1_P_ACCESS "RW"

◆ DMA_SECCFG_CH1_P_BITS

#define DMA_SECCFG_CH1_P_BITS _u(0x00000001)

◆ DMA_SECCFG_CH1_P_LSB

#define DMA_SECCFG_CH1_P_LSB _u(0)

◆ DMA_SECCFG_CH1_P_MSB

#define DMA_SECCFG_CH1_P_MSB _u(0)

◆ DMA_SECCFG_CH1_P_RESET

#define DMA_SECCFG_CH1_P_RESET _u(0x1)

◆ DMA_SECCFG_CH1_RESET

#define DMA_SECCFG_CH1_RESET _u(0x00000003)

◆ DMA_SECCFG_CH1_S_ACCESS

#define DMA_SECCFG_CH1_S_ACCESS "RW"

◆ DMA_SECCFG_CH1_S_BITS

#define DMA_SECCFG_CH1_S_BITS _u(0x00000002)

◆ DMA_SECCFG_CH1_S_LSB

#define DMA_SECCFG_CH1_S_LSB _u(1)

◆ DMA_SECCFG_CH1_S_MSB

#define DMA_SECCFG_CH1_S_MSB _u(1)

◆ DMA_SECCFG_CH1_S_RESET

#define DMA_SECCFG_CH1_S_RESET _u(0x1)

◆ DMA_SECCFG_CH2_BITS

#define DMA_SECCFG_CH2_BITS _u(0x00000007)

◆ DMA_SECCFG_CH2_LOCK_ACCESS

#define DMA_SECCFG_CH2_LOCK_ACCESS "RW"

◆ DMA_SECCFG_CH2_LOCK_BITS

#define DMA_SECCFG_CH2_LOCK_BITS _u(0x00000004)

◆ DMA_SECCFG_CH2_LOCK_LSB

#define DMA_SECCFG_CH2_LOCK_LSB _u(2)

◆ DMA_SECCFG_CH2_LOCK_MSB

#define DMA_SECCFG_CH2_LOCK_MSB _u(2)

◆ DMA_SECCFG_CH2_LOCK_RESET

#define DMA_SECCFG_CH2_LOCK_RESET _u(0x0)

◆ DMA_SECCFG_CH2_OFFSET

#define DMA_SECCFG_CH2_OFFSET _u(0x00000488)

◆ DMA_SECCFG_CH2_P_ACCESS

#define DMA_SECCFG_CH2_P_ACCESS "RW"

◆ DMA_SECCFG_CH2_P_BITS

#define DMA_SECCFG_CH2_P_BITS _u(0x00000001)

◆ DMA_SECCFG_CH2_P_LSB

#define DMA_SECCFG_CH2_P_LSB _u(0)

◆ DMA_SECCFG_CH2_P_MSB

#define DMA_SECCFG_CH2_P_MSB _u(0)

◆ DMA_SECCFG_CH2_P_RESET

#define DMA_SECCFG_CH2_P_RESET _u(0x1)

◆ DMA_SECCFG_CH2_RESET

#define DMA_SECCFG_CH2_RESET _u(0x00000003)

◆ DMA_SECCFG_CH2_S_ACCESS

#define DMA_SECCFG_CH2_S_ACCESS "RW"

◆ DMA_SECCFG_CH2_S_BITS

#define DMA_SECCFG_CH2_S_BITS _u(0x00000002)

◆ DMA_SECCFG_CH2_S_LSB

#define DMA_SECCFG_CH2_S_LSB _u(1)

◆ DMA_SECCFG_CH2_S_MSB

#define DMA_SECCFG_CH2_S_MSB _u(1)

◆ DMA_SECCFG_CH2_S_RESET

#define DMA_SECCFG_CH2_S_RESET _u(0x1)

◆ DMA_SECCFG_CH3_BITS

#define DMA_SECCFG_CH3_BITS _u(0x00000007)

◆ DMA_SECCFG_CH3_LOCK_ACCESS

#define DMA_SECCFG_CH3_LOCK_ACCESS "RW"

◆ DMA_SECCFG_CH3_LOCK_BITS

#define DMA_SECCFG_CH3_LOCK_BITS _u(0x00000004)

◆ DMA_SECCFG_CH3_LOCK_LSB

#define DMA_SECCFG_CH3_LOCK_LSB _u(2)

◆ DMA_SECCFG_CH3_LOCK_MSB

#define DMA_SECCFG_CH3_LOCK_MSB _u(2)

◆ DMA_SECCFG_CH3_LOCK_RESET

#define DMA_SECCFG_CH3_LOCK_RESET _u(0x0)

◆ DMA_SECCFG_CH3_OFFSET

#define DMA_SECCFG_CH3_OFFSET _u(0x0000048c)

◆ DMA_SECCFG_CH3_P_ACCESS

#define DMA_SECCFG_CH3_P_ACCESS "RW"

◆ DMA_SECCFG_CH3_P_BITS

#define DMA_SECCFG_CH3_P_BITS _u(0x00000001)

◆ DMA_SECCFG_CH3_P_LSB

#define DMA_SECCFG_CH3_P_LSB _u(0)

◆ DMA_SECCFG_CH3_P_MSB

#define DMA_SECCFG_CH3_P_MSB _u(0)

◆ DMA_SECCFG_CH3_P_RESET

#define DMA_SECCFG_CH3_P_RESET _u(0x1)

◆ DMA_SECCFG_CH3_RESET

#define DMA_SECCFG_CH3_RESET _u(0x00000003)

◆ DMA_SECCFG_CH3_S_ACCESS

#define DMA_SECCFG_CH3_S_ACCESS "RW"

◆ DMA_SECCFG_CH3_S_BITS

#define DMA_SECCFG_CH3_S_BITS _u(0x00000002)

◆ DMA_SECCFG_CH3_S_LSB

#define DMA_SECCFG_CH3_S_LSB _u(1)

◆ DMA_SECCFG_CH3_S_MSB

#define DMA_SECCFG_CH3_S_MSB _u(1)

◆ DMA_SECCFG_CH3_S_RESET

#define DMA_SECCFG_CH3_S_RESET _u(0x1)

◆ DMA_SECCFG_CH4_BITS

#define DMA_SECCFG_CH4_BITS _u(0x00000007)

◆ DMA_SECCFG_CH4_LOCK_ACCESS

#define DMA_SECCFG_CH4_LOCK_ACCESS "RW"

◆ DMA_SECCFG_CH4_LOCK_BITS

#define DMA_SECCFG_CH4_LOCK_BITS _u(0x00000004)

◆ DMA_SECCFG_CH4_LOCK_LSB

#define DMA_SECCFG_CH4_LOCK_LSB _u(2)

◆ DMA_SECCFG_CH4_LOCK_MSB

#define DMA_SECCFG_CH4_LOCK_MSB _u(2)

◆ DMA_SECCFG_CH4_LOCK_RESET

#define DMA_SECCFG_CH4_LOCK_RESET _u(0x0)

◆ DMA_SECCFG_CH4_OFFSET

#define DMA_SECCFG_CH4_OFFSET _u(0x00000490)

◆ DMA_SECCFG_CH4_P_ACCESS

#define DMA_SECCFG_CH4_P_ACCESS "RW"

◆ DMA_SECCFG_CH4_P_BITS

#define DMA_SECCFG_CH4_P_BITS _u(0x00000001)

◆ DMA_SECCFG_CH4_P_LSB

#define DMA_SECCFG_CH4_P_LSB _u(0)

◆ DMA_SECCFG_CH4_P_MSB

#define DMA_SECCFG_CH4_P_MSB _u(0)

◆ DMA_SECCFG_CH4_P_RESET

#define DMA_SECCFG_CH4_P_RESET _u(0x1)

◆ DMA_SECCFG_CH4_RESET

#define DMA_SECCFG_CH4_RESET _u(0x00000003)

◆ DMA_SECCFG_CH4_S_ACCESS

#define DMA_SECCFG_CH4_S_ACCESS "RW"

◆ DMA_SECCFG_CH4_S_BITS

#define DMA_SECCFG_CH4_S_BITS _u(0x00000002)

◆ DMA_SECCFG_CH4_S_LSB

#define DMA_SECCFG_CH4_S_LSB _u(1)

◆ DMA_SECCFG_CH4_S_MSB

#define DMA_SECCFG_CH4_S_MSB _u(1)

◆ DMA_SECCFG_CH4_S_RESET

#define DMA_SECCFG_CH4_S_RESET _u(0x1)

◆ DMA_SECCFG_CH5_BITS

#define DMA_SECCFG_CH5_BITS _u(0x00000007)

◆ DMA_SECCFG_CH5_LOCK_ACCESS

#define DMA_SECCFG_CH5_LOCK_ACCESS "RW"

◆ DMA_SECCFG_CH5_LOCK_BITS

#define DMA_SECCFG_CH5_LOCK_BITS _u(0x00000004)

◆ DMA_SECCFG_CH5_LOCK_LSB

#define DMA_SECCFG_CH5_LOCK_LSB _u(2)

◆ DMA_SECCFG_CH5_LOCK_MSB

#define DMA_SECCFG_CH5_LOCK_MSB _u(2)

◆ DMA_SECCFG_CH5_LOCK_RESET

#define DMA_SECCFG_CH5_LOCK_RESET _u(0x0)

◆ DMA_SECCFG_CH5_OFFSET

#define DMA_SECCFG_CH5_OFFSET _u(0x00000494)

◆ DMA_SECCFG_CH5_P_ACCESS

#define DMA_SECCFG_CH5_P_ACCESS "RW"

◆ DMA_SECCFG_CH5_P_BITS

#define DMA_SECCFG_CH5_P_BITS _u(0x00000001)

◆ DMA_SECCFG_CH5_P_LSB

#define DMA_SECCFG_CH5_P_LSB _u(0)

◆ DMA_SECCFG_CH5_P_MSB

#define DMA_SECCFG_CH5_P_MSB _u(0)

◆ DMA_SECCFG_CH5_P_RESET

#define DMA_SECCFG_CH5_P_RESET _u(0x1)

◆ DMA_SECCFG_CH5_RESET

#define DMA_SECCFG_CH5_RESET _u(0x00000003)

◆ DMA_SECCFG_CH5_S_ACCESS

#define DMA_SECCFG_CH5_S_ACCESS "RW"

◆ DMA_SECCFG_CH5_S_BITS

#define DMA_SECCFG_CH5_S_BITS _u(0x00000002)

◆ DMA_SECCFG_CH5_S_LSB

#define DMA_SECCFG_CH5_S_LSB _u(1)

◆ DMA_SECCFG_CH5_S_MSB

#define DMA_SECCFG_CH5_S_MSB _u(1)

◆ DMA_SECCFG_CH5_S_RESET

#define DMA_SECCFG_CH5_S_RESET _u(0x1)

◆ DMA_SECCFG_CH6_BITS

#define DMA_SECCFG_CH6_BITS _u(0x00000007)

◆ DMA_SECCFG_CH6_LOCK_ACCESS

#define DMA_SECCFG_CH6_LOCK_ACCESS "RW"

◆ DMA_SECCFG_CH6_LOCK_BITS

#define DMA_SECCFG_CH6_LOCK_BITS _u(0x00000004)

◆ DMA_SECCFG_CH6_LOCK_LSB

#define DMA_SECCFG_CH6_LOCK_LSB _u(2)

◆ DMA_SECCFG_CH6_LOCK_MSB

#define DMA_SECCFG_CH6_LOCK_MSB _u(2)

◆ DMA_SECCFG_CH6_LOCK_RESET

#define DMA_SECCFG_CH6_LOCK_RESET _u(0x0)

◆ DMA_SECCFG_CH6_OFFSET

#define DMA_SECCFG_CH6_OFFSET _u(0x00000498)

◆ DMA_SECCFG_CH6_P_ACCESS

#define DMA_SECCFG_CH6_P_ACCESS "RW"

◆ DMA_SECCFG_CH6_P_BITS

#define DMA_SECCFG_CH6_P_BITS _u(0x00000001)

◆ DMA_SECCFG_CH6_P_LSB

#define DMA_SECCFG_CH6_P_LSB _u(0)

◆ DMA_SECCFG_CH6_P_MSB

#define DMA_SECCFG_CH6_P_MSB _u(0)

◆ DMA_SECCFG_CH6_P_RESET

#define DMA_SECCFG_CH6_P_RESET _u(0x1)

◆ DMA_SECCFG_CH6_RESET

#define DMA_SECCFG_CH6_RESET _u(0x00000003)

◆ DMA_SECCFG_CH6_S_ACCESS

#define DMA_SECCFG_CH6_S_ACCESS "RW"

◆ DMA_SECCFG_CH6_S_BITS

#define DMA_SECCFG_CH6_S_BITS _u(0x00000002)

◆ DMA_SECCFG_CH6_S_LSB

#define DMA_SECCFG_CH6_S_LSB _u(1)

◆ DMA_SECCFG_CH6_S_MSB

#define DMA_SECCFG_CH6_S_MSB _u(1)

◆ DMA_SECCFG_CH6_S_RESET

#define DMA_SECCFG_CH6_S_RESET _u(0x1)

◆ DMA_SECCFG_CH7_BITS

#define DMA_SECCFG_CH7_BITS _u(0x00000007)

◆ DMA_SECCFG_CH7_LOCK_ACCESS

#define DMA_SECCFG_CH7_LOCK_ACCESS "RW"

◆ DMA_SECCFG_CH7_LOCK_BITS

#define DMA_SECCFG_CH7_LOCK_BITS _u(0x00000004)

◆ DMA_SECCFG_CH7_LOCK_LSB

#define DMA_SECCFG_CH7_LOCK_LSB _u(2)

◆ DMA_SECCFG_CH7_LOCK_MSB

#define DMA_SECCFG_CH7_LOCK_MSB _u(2)

◆ DMA_SECCFG_CH7_LOCK_RESET

#define DMA_SECCFG_CH7_LOCK_RESET _u(0x0)

◆ DMA_SECCFG_CH7_OFFSET

#define DMA_SECCFG_CH7_OFFSET _u(0x0000049c)

◆ DMA_SECCFG_CH7_P_ACCESS

#define DMA_SECCFG_CH7_P_ACCESS "RW"

◆ DMA_SECCFG_CH7_P_BITS

#define DMA_SECCFG_CH7_P_BITS _u(0x00000001)

◆ DMA_SECCFG_CH7_P_LSB

#define DMA_SECCFG_CH7_P_LSB _u(0)

◆ DMA_SECCFG_CH7_P_MSB

#define DMA_SECCFG_CH7_P_MSB _u(0)

◆ DMA_SECCFG_CH7_P_RESET

#define DMA_SECCFG_CH7_P_RESET _u(0x1)

◆ DMA_SECCFG_CH7_RESET

#define DMA_SECCFG_CH7_RESET _u(0x00000003)

◆ DMA_SECCFG_CH7_S_ACCESS

#define DMA_SECCFG_CH7_S_ACCESS "RW"

◆ DMA_SECCFG_CH7_S_BITS

#define DMA_SECCFG_CH7_S_BITS _u(0x00000002)

◆ DMA_SECCFG_CH7_S_LSB

#define DMA_SECCFG_CH7_S_LSB _u(1)

◆ DMA_SECCFG_CH7_S_MSB

#define DMA_SECCFG_CH7_S_MSB _u(1)

◆ DMA_SECCFG_CH7_S_RESET

#define DMA_SECCFG_CH7_S_RESET _u(0x1)

◆ DMA_SECCFG_CH8_BITS

#define DMA_SECCFG_CH8_BITS _u(0x00000007)

◆ DMA_SECCFG_CH8_LOCK_ACCESS

#define DMA_SECCFG_CH8_LOCK_ACCESS "RW"

◆ DMA_SECCFG_CH8_LOCK_BITS

#define DMA_SECCFG_CH8_LOCK_BITS _u(0x00000004)

◆ DMA_SECCFG_CH8_LOCK_LSB

#define DMA_SECCFG_CH8_LOCK_LSB _u(2)

◆ DMA_SECCFG_CH8_LOCK_MSB

#define DMA_SECCFG_CH8_LOCK_MSB _u(2)

◆ DMA_SECCFG_CH8_LOCK_RESET

#define DMA_SECCFG_CH8_LOCK_RESET _u(0x0)

◆ DMA_SECCFG_CH8_OFFSET

#define DMA_SECCFG_CH8_OFFSET _u(0x000004a0)

◆ DMA_SECCFG_CH8_P_ACCESS

#define DMA_SECCFG_CH8_P_ACCESS "RW"

◆ DMA_SECCFG_CH8_P_BITS

#define DMA_SECCFG_CH8_P_BITS _u(0x00000001)

◆ DMA_SECCFG_CH8_P_LSB

#define DMA_SECCFG_CH8_P_LSB _u(0)

◆ DMA_SECCFG_CH8_P_MSB

#define DMA_SECCFG_CH8_P_MSB _u(0)

◆ DMA_SECCFG_CH8_P_RESET

#define DMA_SECCFG_CH8_P_RESET _u(0x1)

◆ DMA_SECCFG_CH8_RESET

#define DMA_SECCFG_CH8_RESET _u(0x00000003)

◆ DMA_SECCFG_CH8_S_ACCESS

#define DMA_SECCFG_CH8_S_ACCESS "RW"

◆ DMA_SECCFG_CH8_S_BITS

#define DMA_SECCFG_CH8_S_BITS _u(0x00000002)

◆ DMA_SECCFG_CH8_S_LSB

#define DMA_SECCFG_CH8_S_LSB _u(1)

◆ DMA_SECCFG_CH8_S_MSB

#define DMA_SECCFG_CH8_S_MSB _u(1)

◆ DMA_SECCFG_CH8_S_RESET

#define DMA_SECCFG_CH8_S_RESET _u(0x1)

◆ DMA_SECCFG_CH9_BITS

#define DMA_SECCFG_CH9_BITS _u(0x00000007)

◆ DMA_SECCFG_CH9_LOCK_ACCESS

#define DMA_SECCFG_CH9_LOCK_ACCESS "RW"

◆ DMA_SECCFG_CH9_LOCK_BITS

#define DMA_SECCFG_CH9_LOCK_BITS _u(0x00000004)

◆ DMA_SECCFG_CH9_LOCK_LSB

#define DMA_SECCFG_CH9_LOCK_LSB _u(2)

◆ DMA_SECCFG_CH9_LOCK_MSB

#define DMA_SECCFG_CH9_LOCK_MSB _u(2)

◆ DMA_SECCFG_CH9_LOCK_RESET

#define DMA_SECCFG_CH9_LOCK_RESET _u(0x0)

◆ DMA_SECCFG_CH9_OFFSET

#define DMA_SECCFG_CH9_OFFSET _u(0x000004a4)

◆ DMA_SECCFG_CH9_P_ACCESS

#define DMA_SECCFG_CH9_P_ACCESS "RW"

◆ DMA_SECCFG_CH9_P_BITS

#define DMA_SECCFG_CH9_P_BITS _u(0x00000001)

◆ DMA_SECCFG_CH9_P_LSB

#define DMA_SECCFG_CH9_P_LSB _u(0)

◆ DMA_SECCFG_CH9_P_MSB

#define DMA_SECCFG_CH9_P_MSB _u(0)

◆ DMA_SECCFG_CH9_P_RESET

#define DMA_SECCFG_CH9_P_RESET _u(0x1)

◆ DMA_SECCFG_CH9_RESET

#define DMA_SECCFG_CH9_RESET _u(0x00000003)

◆ DMA_SECCFG_CH9_S_ACCESS

#define DMA_SECCFG_CH9_S_ACCESS "RW"

◆ DMA_SECCFG_CH9_S_BITS

#define DMA_SECCFG_CH9_S_BITS _u(0x00000002)

◆ DMA_SECCFG_CH9_S_LSB

#define DMA_SECCFG_CH9_S_LSB _u(1)

◆ DMA_SECCFG_CH9_S_MSB

#define DMA_SECCFG_CH9_S_MSB _u(1)

◆ DMA_SECCFG_CH9_S_RESET

#define DMA_SECCFG_CH9_S_RESET _u(0x1)

◆ DMA_SECCFG_IRQ0_BITS

#define DMA_SECCFG_IRQ0_BITS _u(0x00000003)

◆ DMA_SECCFG_IRQ0_OFFSET

#define DMA_SECCFG_IRQ0_OFFSET _u(0x000004c0)

◆ DMA_SECCFG_IRQ0_P_ACCESS

#define DMA_SECCFG_IRQ0_P_ACCESS "RW"

◆ DMA_SECCFG_IRQ0_P_BITS

#define DMA_SECCFG_IRQ0_P_BITS _u(0x00000001)

◆ DMA_SECCFG_IRQ0_P_LSB

#define DMA_SECCFG_IRQ0_P_LSB _u(0)

◆ DMA_SECCFG_IRQ0_P_MSB

#define DMA_SECCFG_IRQ0_P_MSB _u(0)

◆ DMA_SECCFG_IRQ0_P_RESET

#define DMA_SECCFG_IRQ0_P_RESET _u(0x1)

◆ DMA_SECCFG_IRQ0_RESET

#define DMA_SECCFG_IRQ0_RESET _u(0x00000003)

◆ DMA_SECCFG_IRQ0_S_ACCESS

#define DMA_SECCFG_IRQ0_S_ACCESS "RW"

◆ DMA_SECCFG_IRQ0_S_BITS

#define DMA_SECCFG_IRQ0_S_BITS _u(0x00000002)

◆ DMA_SECCFG_IRQ0_S_LSB

#define DMA_SECCFG_IRQ0_S_LSB _u(1)

◆ DMA_SECCFG_IRQ0_S_MSB

#define DMA_SECCFG_IRQ0_S_MSB _u(1)

◆ DMA_SECCFG_IRQ0_S_RESET

#define DMA_SECCFG_IRQ0_S_RESET _u(0x1)

◆ DMA_SECCFG_IRQ1_BITS

#define DMA_SECCFG_IRQ1_BITS _u(0x00000003)

◆ DMA_SECCFG_IRQ1_OFFSET

#define DMA_SECCFG_IRQ1_OFFSET _u(0x000004c4)

◆ DMA_SECCFG_IRQ1_P_ACCESS

#define DMA_SECCFG_IRQ1_P_ACCESS "RW"

◆ DMA_SECCFG_IRQ1_P_BITS

#define DMA_SECCFG_IRQ1_P_BITS _u(0x00000001)

◆ DMA_SECCFG_IRQ1_P_LSB

#define DMA_SECCFG_IRQ1_P_LSB _u(0)

◆ DMA_SECCFG_IRQ1_P_MSB

#define DMA_SECCFG_IRQ1_P_MSB _u(0)

◆ DMA_SECCFG_IRQ1_P_RESET

#define DMA_SECCFG_IRQ1_P_RESET _u(0x1)

◆ DMA_SECCFG_IRQ1_RESET

#define DMA_SECCFG_IRQ1_RESET _u(0x00000003)

◆ DMA_SECCFG_IRQ1_S_ACCESS

#define DMA_SECCFG_IRQ1_S_ACCESS "RW"

◆ DMA_SECCFG_IRQ1_S_BITS

#define DMA_SECCFG_IRQ1_S_BITS _u(0x00000002)

◆ DMA_SECCFG_IRQ1_S_LSB

#define DMA_SECCFG_IRQ1_S_LSB _u(1)

◆ DMA_SECCFG_IRQ1_S_MSB

#define DMA_SECCFG_IRQ1_S_MSB _u(1)

◆ DMA_SECCFG_IRQ1_S_RESET

#define DMA_SECCFG_IRQ1_S_RESET _u(0x1)

◆ DMA_SECCFG_IRQ2_BITS

#define DMA_SECCFG_IRQ2_BITS _u(0x00000003)

◆ DMA_SECCFG_IRQ2_OFFSET

#define DMA_SECCFG_IRQ2_OFFSET _u(0x000004c8)

◆ DMA_SECCFG_IRQ2_P_ACCESS

#define DMA_SECCFG_IRQ2_P_ACCESS "RW"

◆ DMA_SECCFG_IRQ2_P_BITS

#define DMA_SECCFG_IRQ2_P_BITS _u(0x00000001)

◆ DMA_SECCFG_IRQ2_P_LSB

#define DMA_SECCFG_IRQ2_P_LSB _u(0)

◆ DMA_SECCFG_IRQ2_P_MSB

#define DMA_SECCFG_IRQ2_P_MSB _u(0)

◆ DMA_SECCFG_IRQ2_P_RESET

#define DMA_SECCFG_IRQ2_P_RESET _u(0x1)

◆ DMA_SECCFG_IRQ2_RESET

#define DMA_SECCFG_IRQ2_RESET _u(0x00000003)

◆ DMA_SECCFG_IRQ2_S_ACCESS

#define DMA_SECCFG_IRQ2_S_ACCESS "RW"

◆ DMA_SECCFG_IRQ2_S_BITS

#define DMA_SECCFG_IRQ2_S_BITS _u(0x00000002)

◆ DMA_SECCFG_IRQ2_S_LSB

#define DMA_SECCFG_IRQ2_S_LSB _u(1)

◆ DMA_SECCFG_IRQ2_S_MSB

#define DMA_SECCFG_IRQ2_S_MSB _u(1)

◆ DMA_SECCFG_IRQ2_S_RESET

#define DMA_SECCFG_IRQ2_S_RESET _u(0x1)

◆ DMA_SECCFG_IRQ3_BITS

#define DMA_SECCFG_IRQ3_BITS _u(0x00000003)

◆ DMA_SECCFG_IRQ3_OFFSET

#define DMA_SECCFG_IRQ3_OFFSET _u(0x000004cc)

◆ DMA_SECCFG_IRQ3_P_ACCESS

#define DMA_SECCFG_IRQ3_P_ACCESS "RW"

◆ DMA_SECCFG_IRQ3_P_BITS

#define DMA_SECCFG_IRQ3_P_BITS _u(0x00000001)

◆ DMA_SECCFG_IRQ3_P_LSB

#define DMA_SECCFG_IRQ3_P_LSB _u(0)

◆ DMA_SECCFG_IRQ3_P_MSB

#define DMA_SECCFG_IRQ3_P_MSB _u(0)

◆ DMA_SECCFG_IRQ3_P_RESET

#define DMA_SECCFG_IRQ3_P_RESET _u(0x1)

◆ DMA_SECCFG_IRQ3_RESET

#define DMA_SECCFG_IRQ3_RESET _u(0x00000003)

◆ DMA_SECCFG_IRQ3_S_ACCESS

#define DMA_SECCFG_IRQ3_S_ACCESS "RW"

◆ DMA_SECCFG_IRQ3_S_BITS

#define DMA_SECCFG_IRQ3_S_BITS _u(0x00000002)

◆ DMA_SECCFG_IRQ3_S_LSB

#define DMA_SECCFG_IRQ3_S_LSB _u(1)

◆ DMA_SECCFG_IRQ3_S_MSB

#define DMA_SECCFG_IRQ3_S_MSB _u(1)

◆ DMA_SECCFG_IRQ3_S_RESET

#define DMA_SECCFG_IRQ3_S_RESET _u(0x1)

◆ DMA_SECCFG_MISC_BITS

#define DMA_SECCFG_MISC_BITS _u(0x000003ff)

◆ DMA_SECCFG_MISC_OFFSET

#define DMA_SECCFG_MISC_OFFSET _u(0x000004d0)

◆ DMA_SECCFG_MISC_RESET

#define DMA_SECCFG_MISC_RESET _u(0x000003ff)

◆ DMA_SECCFG_MISC_SNIFF_P_ACCESS

#define DMA_SECCFG_MISC_SNIFF_P_ACCESS "RW"

◆ DMA_SECCFG_MISC_SNIFF_P_BITS

#define DMA_SECCFG_MISC_SNIFF_P_BITS _u(0x00000001)

◆ DMA_SECCFG_MISC_SNIFF_P_LSB

#define DMA_SECCFG_MISC_SNIFF_P_LSB _u(0)

◆ DMA_SECCFG_MISC_SNIFF_P_MSB

#define DMA_SECCFG_MISC_SNIFF_P_MSB _u(0)

◆ DMA_SECCFG_MISC_SNIFF_P_RESET

#define DMA_SECCFG_MISC_SNIFF_P_RESET _u(0x1)

◆ DMA_SECCFG_MISC_SNIFF_S_ACCESS

#define DMA_SECCFG_MISC_SNIFF_S_ACCESS "RW"

◆ DMA_SECCFG_MISC_SNIFF_S_BITS

#define DMA_SECCFG_MISC_SNIFF_S_BITS _u(0x00000002)

◆ DMA_SECCFG_MISC_SNIFF_S_LSB

#define DMA_SECCFG_MISC_SNIFF_S_LSB _u(1)

◆ DMA_SECCFG_MISC_SNIFF_S_MSB

#define DMA_SECCFG_MISC_SNIFF_S_MSB _u(1)

◆ DMA_SECCFG_MISC_SNIFF_S_RESET

#define DMA_SECCFG_MISC_SNIFF_S_RESET _u(0x1)

◆ DMA_SECCFG_MISC_TIMER0_P_ACCESS

#define DMA_SECCFG_MISC_TIMER0_P_ACCESS "RW"

◆ DMA_SECCFG_MISC_TIMER0_P_BITS

#define DMA_SECCFG_MISC_TIMER0_P_BITS _u(0x00000004)

◆ DMA_SECCFG_MISC_TIMER0_P_LSB

#define DMA_SECCFG_MISC_TIMER0_P_LSB _u(2)

◆ DMA_SECCFG_MISC_TIMER0_P_MSB

#define DMA_SECCFG_MISC_TIMER0_P_MSB _u(2)

◆ DMA_SECCFG_MISC_TIMER0_P_RESET

#define DMA_SECCFG_MISC_TIMER0_P_RESET _u(0x1)

◆ DMA_SECCFG_MISC_TIMER0_S_ACCESS

#define DMA_SECCFG_MISC_TIMER0_S_ACCESS "RW"

◆ DMA_SECCFG_MISC_TIMER0_S_BITS

#define DMA_SECCFG_MISC_TIMER0_S_BITS _u(0x00000008)

◆ DMA_SECCFG_MISC_TIMER0_S_LSB

#define DMA_SECCFG_MISC_TIMER0_S_LSB _u(3)

◆ DMA_SECCFG_MISC_TIMER0_S_MSB

#define DMA_SECCFG_MISC_TIMER0_S_MSB _u(3)

◆ DMA_SECCFG_MISC_TIMER0_S_RESET

#define DMA_SECCFG_MISC_TIMER0_S_RESET _u(0x1)

◆ DMA_SECCFG_MISC_TIMER1_P_ACCESS

#define DMA_SECCFG_MISC_TIMER1_P_ACCESS "RW"

◆ DMA_SECCFG_MISC_TIMER1_P_BITS

#define DMA_SECCFG_MISC_TIMER1_P_BITS _u(0x00000010)

◆ DMA_SECCFG_MISC_TIMER1_P_LSB

#define DMA_SECCFG_MISC_TIMER1_P_LSB _u(4)

◆ DMA_SECCFG_MISC_TIMER1_P_MSB

#define DMA_SECCFG_MISC_TIMER1_P_MSB _u(4)

◆ DMA_SECCFG_MISC_TIMER1_P_RESET

#define DMA_SECCFG_MISC_TIMER1_P_RESET _u(0x1)

◆ DMA_SECCFG_MISC_TIMER1_S_ACCESS

#define DMA_SECCFG_MISC_TIMER1_S_ACCESS "RW"

◆ DMA_SECCFG_MISC_TIMER1_S_BITS

#define DMA_SECCFG_MISC_TIMER1_S_BITS _u(0x00000020)

◆ DMA_SECCFG_MISC_TIMER1_S_LSB

#define DMA_SECCFG_MISC_TIMER1_S_LSB _u(5)

◆ DMA_SECCFG_MISC_TIMER1_S_MSB

#define DMA_SECCFG_MISC_TIMER1_S_MSB _u(5)

◆ DMA_SECCFG_MISC_TIMER1_S_RESET

#define DMA_SECCFG_MISC_TIMER1_S_RESET _u(0x1)

◆ DMA_SECCFG_MISC_TIMER2_P_ACCESS

#define DMA_SECCFG_MISC_TIMER2_P_ACCESS "RW"

◆ DMA_SECCFG_MISC_TIMER2_P_BITS

#define DMA_SECCFG_MISC_TIMER2_P_BITS _u(0x00000040)

◆ DMA_SECCFG_MISC_TIMER2_P_LSB

#define DMA_SECCFG_MISC_TIMER2_P_LSB _u(6)

◆ DMA_SECCFG_MISC_TIMER2_P_MSB

#define DMA_SECCFG_MISC_TIMER2_P_MSB _u(6)

◆ DMA_SECCFG_MISC_TIMER2_P_RESET

#define DMA_SECCFG_MISC_TIMER2_P_RESET _u(0x1)

◆ DMA_SECCFG_MISC_TIMER2_S_ACCESS

#define DMA_SECCFG_MISC_TIMER2_S_ACCESS "RW"

◆ DMA_SECCFG_MISC_TIMER2_S_BITS

#define DMA_SECCFG_MISC_TIMER2_S_BITS _u(0x00000080)

◆ DMA_SECCFG_MISC_TIMER2_S_LSB

#define DMA_SECCFG_MISC_TIMER2_S_LSB _u(7)

◆ DMA_SECCFG_MISC_TIMER2_S_MSB

#define DMA_SECCFG_MISC_TIMER2_S_MSB _u(7)

◆ DMA_SECCFG_MISC_TIMER2_S_RESET

#define DMA_SECCFG_MISC_TIMER2_S_RESET _u(0x1)

◆ DMA_SECCFG_MISC_TIMER3_P_ACCESS

#define DMA_SECCFG_MISC_TIMER3_P_ACCESS "RW"

◆ DMA_SECCFG_MISC_TIMER3_P_BITS

#define DMA_SECCFG_MISC_TIMER3_P_BITS _u(0x00000100)

◆ DMA_SECCFG_MISC_TIMER3_P_LSB

#define DMA_SECCFG_MISC_TIMER3_P_LSB _u(8)

◆ DMA_SECCFG_MISC_TIMER3_P_MSB

#define DMA_SECCFG_MISC_TIMER3_P_MSB _u(8)

◆ DMA_SECCFG_MISC_TIMER3_P_RESET

#define DMA_SECCFG_MISC_TIMER3_P_RESET _u(0x1)

◆ DMA_SECCFG_MISC_TIMER3_S_ACCESS

#define DMA_SECCFG_MISC_TIMER3_S_ACCESS "RW"

◆ DMA_SECCFG_MISC_TIMER3_S_BITS

#define DMA_SECCFG_MISC_TIMER3_S_BITS _u(0x00000200)

◆ DMA_SECCFG_MISC_TIMER3_S_LSB

#define DMA_SECCFG_MISC_TIMER3_S_LSB _u(9)

◆ DMA_SECCFG_MISC_TIMER3_S_MSB

#define DMA_SECCFG_MISC_TIMER3_S_MSB _u(9)

◆ DMA_SECCFG_MISC_TIMER3_S_RESET

#define DMA_SECCFG_MISC_TIMER3_S_RESET _u(0x1)

◆ DMA_SNIFF_CTRL_BITS

#define DMA_SNIFF_CTRL_BITS _u(0x00000fff)

◆ DMA_SNIFF_CTRL_BSWAP_ACCESS

#define DMA_SNIFF_CTRL_BSWAP_ACCESS "RW"

◆ DMA_SNIFF_CTRL_BSWAP_BITS

#define DMA_SNIFF_CTRL_BSWAP_BITS _u(0x00000200)

◆ DMA_SNIFF_CTRL_BSWAP_LSB

#define DMA_SNIFF_CTRL_BSWAP_LSB _u(9)

◆ DMA_SNIFF_CTRL_BSWAP_MSB

#define DMA_SNIFF_CTRL_BSWAP_MSB _u(9)

◆ DMA_SNIFF_CTRL_BSWAP_RESET

#define DMA_SNIFF_CTRL_BSWAP_RESET _u(0x0)

◆ DMA_SNIFF_CTRL_CALC_ACCESS

#define DMA_SNIFF_CTRL_CALC_ACCESS "RW"

◆ DMA_SNIFF_CTRL_CALC_BITS

#define DMA_SNIFF_CTRL_CALC_BITS _u(0x000001e0)

◆ DMA_SNIFF_CTRL_CALC_LSB

#define DMA_SNIFF_CTRL_CALC_LSB _u(5)

◆ DMA_SNIFF_CTRL_CALC_MSB

#define DMA_SNIFF_CTRL_CALC_MSB _u(8)

◆ DMA_SNIFF_CTRL_CALC_RESET

#define DMA_SNIFF_CTRL_CALC_RESET _u(0x0)

◆ DMA_SNIFF_CTRL_CALC_VALUE_CRC16

#define DMA_SNIFF_CTRL_CALC_VALUE_CRC16 _u(0x2)

◆ DMA_SNIFF_CTRL_CALC_VALUE_CRC16R

#define DMA_SNIFF_CTRL_CALC_VALUE_CRC16R _u(0x3)

◆ DMA_SNIFF_CTRL_CALC_VALUE_CRC32

#define DMA_SNIFF_CTRL_CALC_VALUE_CRC32 _u(0x0)

◆ DMA_SNIFF_CTRL_CALC_VALUE_CRC32R

#define DMA_SNIFF_CTRL_CALC_VALUE_CRC32R _u(0x1)

◆ DMA_SNIFF_CTRL_CALC_VALUE_EVEN

#define DMA_SNIFF_CTRL_CALC_VALUE_EVEN _u(0xe)

◆ DMA_SNIFF_CTRL_CALC_VALUE_SUM

#define DMA_SNIFF_CTRL_CALC_VALUE_SUM _u(0xf)

◆ DMA_SNIFF_CTRL_DMACH_ACCESS

#define DMA_SNIFF_CTRL_DMACH_ACCESS "RW"

◆ DMA_SNIFF_CTRL_DMACH_BITS

#define DMA_SNIFF_CTRL_DMACH_BITS _u(0x0000001e)

◆ DMA_SNIFF_CTRL_DMACH_LSB

#define DMA_SNIFF_CTRL_DMACH_LSB _u(1)

◆ DMA_SNIFF_CTRL_DMACH_MSB

#define DMA_SNIFF_CTRL_DMACH_MSB _u(4)

◆ DMA_SNIFF_CTRL_DMACH_RESET

#define DMA_SNIFF_CTRL_DMACH_RESET _u(0x0)

◆ DMA_SNIFF_CTRL_EN_ACCESS

#define DMA_SNIFF_CTRL_EN_ACCESS "RW"

◆ DMA_SNIFF_CTRL_EN_BITS

#define DMA_SNIFF_CTRL_EN_BITS _u(0x00000001)

◆ DMA_SNIFF_CTRL_EN_LSB

#define DMA_SNIFF_CTRL_EN_LSB _u(0)

◆ DMA_SNIFF_CTRL_EN_MSB

#define DMA_SNIFF_CTRL_EN_MSB _u(0)

◆ DMA_SNIFF_CTRL_EN_RESET

#define DMA_SNIFF_CTRL_EN_RESET _u(0x0)

◆ DMA_SNIFF_CTRL_OFFSET

#define DMA_SNIFF_CTRL_OFFSET _u(0x00000454)

◆ DMA_SNIFF_CTRL_OUT_INV_ACCESS

#define DMA_SNIFF_CTRL_OUT_INV_ACCESS "RW"

◆ DMA_SNIFF_CTRL_OUT_INV_BITS

#define DMA_SNIFF_CTRL_OUT_INV_BITS _u(0x00000800)

◆ DMA_SNIFF_CTRL_OUT_INV_LSB

#define DMA_SNIFF_CTRL_OUT_INV_LSB _u(11)

◆ DMA_SNIFF_CTRL_OUT_INV_MSB

#define DMA_SNIFF_CTRL_OUT_INV_MSB _u(11)

◆ DMA_SNIFF_CTRL_OUT_INV_RESET

#define DMA_SNIFF_CTRL_OUT_INV_RESET _u(0x0)

◆ DMA_SNIFF_CTRL_OUT_REV_ACCESS

#define DMA_SNIFF_CTRL_OUT_REV_ACCESS "RW"

◆ DMA_SNIFF_CTRL_OUT_REV_BITS

#define DMA_SNIFF_CTRL_OUT_REV_BITS _u(0x00000400)

◆ DMA_SNIFF_CTRL_OUT_REV_LSB

#define DMA_SNIFF_CTRL_OUT_REV_LSB _u(10)

◆ DMA_SNIFF_CTRL_OUT_REV_MSB

#define DMA_SNIFF_CTRL_OUT_REV_MSB _u(10)

◆ DMA_SNIFF_CTRL_OUT_REV_RESET

#define DMA_SNIFF_CTRL_OUT_REV_RESET _u(0x0)

◆ DMA_SNIFF_CTRL_RESET

#define DMA_SNIFF_CTRL_RESET _u(0x00000000)

◆ DMA_SNIFF_DATA_ACCESS

#define DMA_SNIFF_DATA_ACCESS "RW"

◆ DMA_SNIFF_DATA_BITS

#define DMA_SNIFF_DATA_BITS _u(0xffffffff)

◆ DMA_SNIFF_DATA_LSB

#define DMA_SNIFF_DATA_LSB _u(0)

◆ DMA_SNIFF_DATA_MSB

#define DMA_SNIFF_DATA_MSB _u(31)

◆ DMA_SNIFF_DATA_OFFSET

#define DMA_SNIFF_DATA_OFFSET _u(0x00000458)

◆ DMA_SNIFF_DATA_RESET

#define DMA_SNIFF_DATA_RESET _u(0x00000000)

◆ DMA_TIMER0_BITS

#define DMA_TIMER0_BITS _u(0xffffffff)

◆ DMA_TIMER0_OFFSET

#define DMA_TIMER0_OFFSET _u(0x00000440)

◆ DMA_TIMER0_RESET

#define DMA_TIMER0_RESET _u(0x00000000)

◆ DMA_TIMER0_X_ACCESS

#define DMA_TIMER0_X_ACCESS "RW"

◆ DMA_TIMER0_X_BITS

#define DMA_TIMER0_X_BITS _u(0xffff0000)

◆ DMA_TIMER0_X_LSB

#define DMA_TIMER0_X_LSB _u(16)

◆ DMA_TIMER0_X_MSB

#define DMA_TIMER0_X_MSB _u(31)

◆ DMA_TIMER0_X_RESET

#define DMA_TIMER0_X_RESET _u(0x0000)

◆ DMA_TIMER0_Y_ACCESS

#define DMA_TIMER0_Y_ACCESS "RW"

◆ DMA_TIMER0_Y_BITS

#define DMA_TIMER0_Y_BITS _u(0x0000ffff)

◆ DMA_TIMER0_Y_LSB

#define DMA_TIMER0_Y_LSB _u(0)

◆ DMA_TIMER0_Y_MSB

#define DMA_TIMER0_Y_MSB _u(15)

◆ DMA_TIMER0_Y_RESET

#define DMA_TIMER0_Y_RESET _u(0x0000)

◆ DMA_TIMER1_BITS

#define DMA_TIMER1_BITS _u(0xffffffff)

◆ DMA_TIMER1_OFFSET

#define DMA_TIMER1_OFFSET _u(0x00000444)

◆ DMA_TIMER1_RESET

#define DMA_TIMER1_RESET _u(0x00000000)

◆ DMA_TIMER1_X_ACCESS

#define DMA_TIMER1_X_ACCESS "RW"

◆ DMA_TIMER1_X_BITS

#define DMA_TIMER1_X_BITS _u(0xffff0000)

◆ DMA_TIMER1_X_LSB

#define DMA_TIMER1_X_LSB _u(16)

◆ DMA_TIMER1_X_MSB

#define DMA_TIMER1_X_MSB _u(31)

◆ DMA_TIMER1_X_RESET

#define DMA_TIMER1_X_RESET _u(0x0000)

◆ DMA_TIMER1_Y_ACCESS

#define DMA_TIMER1_Y_ACCESS "RW"

◆ DMA_TIMER1_Y_BITS

#define DMA_TIMER1_Y_BITS _u(0x0000ffff)

◆ DMA_TIMER1_Y_LSB

#define DMA_TIMER1_Y_LSB _u(0)

◆ DMA_TIMER1_Y_MSB

#define DMA_TIMER1_Y_MSB _u(15)

◆ DMA_TIMER1_Y_RESET

#define DMA_TIMER1_Y_RESET _u(0x0000)

◆ DMA_TIMER2_BITS

#define DMA_TIMER2_BITS _u(0xffffffff)

◆ DMA_TIMER2_OFFSET

#define DMA_TIMER2_OFFSET _u(0x00000448)

◆ DMA_TIMER2_RESET

#define DMA_TIMER2_RESET _u(0x00000000)

◆ DMA_TIMER2_X_ACCESS

#define DMA_TIMER2_X_ACCESS "RW"

◆ DMA_TIMER2_X_BITS

#define DMA_TIMER2_X_BITS _u(0xffff0000)

◆ DMA_TIMER2_X_LSB

#define DMA_TIMER2_X_LSB _u(16)

◆ DMA_TIMER2_X_MSB

#define DMA_TIMER2_X_MSB _u(31)

◆ DMA_TIMER2_X_RESET

#define DMA_TIMER2_X_RESET _u(0x0000)

◆ DMA_TIMER2_Y_ACCESS

#define DMA_TIMER2_Y_ACCESS "RW"

◆ DMA_TIMER2_Y_BITS

#define DMA_TIMER2_Y_BITS _u(0x0000ffff)

◆ DMA_TIMER2_Y_LSB

#define DMA_TIMER2_Y_LSB _u(0)

◆ DMA_TIMER2_Y_MSB

#define DMA_TIMER2_Y_MSB _u(15)

◆ DMA_TIMER2_Y_RESET

#define DMA_TIMER2_Y_RESET _u(0x0000)

◆ DMA_TIMER3_BITS

#define DMA_TIMER3_BITS _u(0xffffffff)

◆ DMA_TIMER3_OFFSET

#define DMA_TIMER3_OFFSET _u(0x0000044c)

◆ DMA_TIMER3_RESET

#define DMA_TIMER3_RESET _u(0x00000000)

◆ DMA_TIMER3_X_ACCESS

#define DMA_TIMER3_X_ACCESS "RW"

◆ DMA_TIMER3_X_BITS

#define DMA_TIMER3_X_BITS _u(0xffff0000)

◆ DMA_TIMER3_X_LSB

#define DMA_TIMER3_X_LSB _u(16)

◆ DMA_TIMER3_X_MSB

#define DMA_TIMER3_X_MSB _u(31)

◆ DMA_TIMER3_X_RESET

#define DMA_TIMER3_X_RESET _u(0x0000)

◆ DMA_TIMER3_Y_ACCESS

#define DMA_TIMER3_Y_ACCESS "RW"

◆ DMA_TIMER3_Y_BITS

#define DMA_TIMER3_Y_BITS _u(0x0000ffff)

◆ DMA_TIMER3_Y_LSB

#define DMA_TIMER3_Y_LSB _u(0)

◆ DMA_TIMER3_Y_MSB

#define DMA_TIMER3_Y_MSB _u(15)

◆ DMA_TIMER3_Y_RESET

#define DMA_TIMER3_Y_RESET _u(0x0000)

Macros