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RP2040 OLED SSD1306
Driver/Exemplos para display OLED SSD1306 no RP2040
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| #define DMA_CH0_AL1_CTRL_ACCESS "RW" |
| #define DMA_CH0_AL1_CTRL_RESET "-" |
| #define DMA_CH0_AL1_READ_ADDR_ACCESS "RW" |
| #define DMA_CH0_AL1_READ_ADDR_RESET "-" |
| #define DMA_CH0_AL1_TRANS_COUNT_TRIG_ACCESS "RW" |
| #define DMA_CH0_AL1_TRANS_COUNT_TRIG_RESET "-" |
| #define DMA_CH0_AL1_WRITE_ADDR_ACCESS "RW" |
| #define DMA_CH0_AL1_WRITE_ADDR_RESET "-" |
| #define DMA_CH0_AL2_CTRL_ACCESS "RW" |
| #define DMA_CH0_AL2_CTRL_RESET "-" |
| #define DMA_CH0_AL2_READ_ADDR_ACCESS "RW" |
| #define DMA_CH0_AL2_READ_ADDR_RESET "-" |
| #define DMA_CH0_AL2_TRANS_COUNT_ACCESS "RW" |
| #define DMA_CH0_AL2_TRANS_COUNT_RESET "-" |
| #define DMA_CH0_AL2_WRITE_ADDR_TRIG_ACCESS "RW" |
| #define DMA_CH0_AL2_WRITE_ADDR_TRIG_RESET "-" |
| #define DMA_CH0_AL3_CTRL_ACCESS "RW" |
| #define DMA_CH0_AL3_CTRL_RESET "-" |
| #define DMA_CH0_AL3_READ_ADDR_TRIG_ACCESS "RW" |
| #define DMA_CH0_AL3_READ_ADDR_TRIG_RESET "-" |
| #define DMA_CH0_AL3_TRANS_COUNT_ACCESS "RW" |
| #define DMA_CH0_AL3_TRANS_COUNT_RESET "-" |
| #define DMA_CH0_AL3_WRITE_ADDR_ACCESS "RW" |
| #define DMA_CH0_AL3_WRITE_ADDR_RESET "-" |
| #define DMA_CH0_CTRL_TRIG_AHB_ERROR_ACCESS "RO" |
| #define DMA_CH0_CTRL_TRIG_BSWAP_ACCESS "RW" |
| #define DMA_CH0_CTRL_TRIG_BUSY_ACCESS "RO" |
| #define DMA_CH0_CTRL_TRIG_CHAIN_TO_ACCESS "RW" |
| #define DMA_CH0_CTRL_TRIG_DATA_SIZE_ACCESS "RW" |
| #define DMA_CH0_CTRL_TRIG_EN_ACCESS "RW" |
| #define DMA_CH0_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" |
| #define DMA_CH0_CTRL_TRIG_INCR_READ_ACCESS "RW" |
| #define DMA_CH0_CTRL_TRIG_INCR_READ_REV_ACCESS "RW" |
| #define DMA_CH0_CTRL_TRIG_INCR_WRITE_ACCESS "RW" |
| #define DMA_CH0_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW" |
| #define DMA_CH0_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" |
| #define DMA_CH0_CTRL_TRIG_READ_ERROR_ACCESS "WC" |
| #define DMA_CH0_CTRL_TRIG_RING_SEL_ACCESS "RW" |
| #define DMA_CH0_CTRL_TRIG_RING_SIZE_ACCESS "RW" |
| #define DMA_CH0_CTRL_TRIG_SNIFF_EN_ACCESS "RW" |
| #define DMA_CH0_CTRL_TRIG_TREQ_SEL_ACCESS "RW" |
| #define DMA_CH0_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" |
| #define DMA_CH0_DBG_CTDREQ_ACCESS "WC" |
| #define DMA_CH0_DBG_TCR_ACCESS "RO" |
| #define DMA_CH0_READ_ADDR_ACCESS "RW" |
Copyright (c) 2024 Raspberry Pi Ltd.
SPDX-License-Identifier: BSD-3-Clause
| #define DMA_CH0_TRANS_COUNT_COUNT_ACCESS "RW" |
| #define DMA_CH0_TRANS_COUNT_MODE_ACCESS "RW" |
| #define DMA_CH0_WRITE_ADDR_ACCESS "RW" |
| #define DMA_CH10_AL1_CTRL_ACCESS "RW" |
| #define DMA_CH10_AL1_CTRL_RESET "-" |
| #define DMA_CH10_AL1_READ_ADDR_ACCESS "RW" |
| #define DMA_CH10_AL1_READ_ADDR_RESET "-" |
| #define DMA_CH10_AL1_TRANS_COUNT_TRIG_ACCESS "RW" |
| #define DMA_CH10_AL1_TRANS_COUNT_TRIG_RESET "-" |
| #define DMA_CH10_AL1_WRITE_ADDR_ACCESS "RW" |
| #define DMA_CH10_AL1_WRITE_ADDR_RESET "-" |
| #define DMA_CH10_AL2_CTRL_ACCESS "RW" |
| #define DMA_CH10_AL2_CTRL_RESET "-" |
| #define DMA_CH10_AL2_READ_ADDR_ACCESS "RW" |
| #define DMA_CH10_AL2_READ_ADDR_RESET "-" |
| #define DMA_CH10_AL2_TRANS_COUNT_ACCESS "RW" |
| #define DMA_CH10_AL2_TRANS_COUNT_RESET "-" |
| #define DMA_CH10_AL2_WRITE_ADDR_TRIG_ACCESS "RW" |
| #define DMA_CH10_AL2_WRITE_ADDR_TRIG_RESET "-" |
| #define DMA_CH10_AL3_CTRL_ACCESS "RW" |
| #define DMA_CH10_AL3_CTRL_RESET "-" |
| #define DMA_CH10_AL3_READ_ADDR_TRIG_ACCESS "RW" |
| #define DMA_CH10_AL3_READ_ADDR_TRIG_RESET "-" |
| #define DMA_CH10_AL3_TRANS_COUNT_ACCESS "RW" |
| #define DMA_CH10_AL3_TRANS_COUNT_RESET "-" |
| #define DMA_CH10_AL3_WRITE_ADDR_ACCESS "RW" |
| #define DMA_CH10_AL3_WRITE_ADDR_RESET "-" |
| #define DMA_CH10_CTRL_TRIG_AHB_ERROR_ACCESS "RO" |
| #define DMA_CH10_CTRL_TRIG_BSWAP_ACCESS "RW" |
| #define DMA_CH10_CTRL_TRIG_BUSY_ACCESS "RO" |
| #define DMA_CH10_CTRL_TRIG_CHAIN_TO_ACCESS "RW" |
| #define DMA_CH10_CTRL_TRIG_DATA_SIZE_ACCESS "RW" |
| #define DMA_CH10_CTRL_TRIG_EN_ACCESS "RW" |
| #define DMA_CH10_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" |
| #define DMA_CH10_CTRL_TRIG_INCR_READ_ACCESS "RW" |
| #define DMA_CH10_CTRL_TRIG_INCR_READ_REV_ACCESS "RW" |
| #define DMA_CH10_CTRL_TRIG_INCR_WRITE_ACCESS "RW" |
| #define DMA_CH10_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW" |
| #define DMA_CH10_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" |
| #define DMA_CH10_CTRL_TRIG_READ_ERROR_ACCESS "WC" |
| #define DMA_CH10_CTRL_TRIG_RING_SEL_ACCESS "RW" |
| #define DMA_CH10_CTRL_TRIG_RING_SIZE_ACCESS "RW" |
| #define DMA_CH10_CTRL_TRIG_SNIFF_EN_ACCESS "RW" |
| #define DMA_CH10_CTRL_TRIG_TREQ_SEL_ACCESS "RW" |
| #define DMA_CH10_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" |
| #define DMA_CH10_DBG_CTDREQ_ACCESS "WC" |
| #define DMA_CH10_DBG_TCR_ACCESS "RO" |
| #define DMA_CH10_READ_ADDR_ACCESS "RW" |
| #define DMA_CH10_TRANS_COUNT_COUNT_ACCESS "RW" |
| #define DMA_CH10_TRANS_COUNT_MODE_ACCESS "RW" |
| #define DMA_CH10_WRITE_ADDR_ACCESS "RW" |
| #define DMA_CH11_AL1_CTRL_ACCESS "RW" |
| #define DMA_CH11_AL1_CTRL_RESET "-" |
| #define DMA_CH11_AL1_READ_ADDR_ACCESS "RW" |
| #define DMA_CH11_AL1_READ_ADDR_RESET "-" |
| #define DMA_CH11_AL1_TRANS_COUNT_TRIG_ACCESS "RW" |
| #define DMA_CH11_AL1_TRANS_COUNT_TRIG_RESET "-" |
| #define DMA_CH11_AL1_WRITE_ADDR_ACCESS "RW" |
| #define DMA_CH11_AL1_WRITE_ADDR_RESET "-" |
| #define DMA_CH11_AL2_CTRL_ACCESS "RW" |
| #define DMA_CH11_AL2_CTRL_RESET "-" |
| #define DMA_CH11_AL2_READ_ADDR_ACCESS "RW" |
| #define DMA_CH11_AL2_READ_ADDR_RESET "-" |
| #define DMA_CH11_AL2_TRANS_COUNT_ACCESS "RW" |
| #define DMA_CH11_AL2_TRANS_COUNT_RESET "-" |
| #define DMA_CH11_AL2_WRITE_ADDR_TRIG_ACCESS "RW" |
| #define DMA_CH11_AL2_WRITE_ADDR_TRIG_RESET "-" |
| #define DMA_CH11_AL3_CTRL_ACCESS "RW" |
| #define DMA_CH11_AL3_CTRL_RESET "-" |
| #define DMA_CH11_AL3_READ_ADDR_TRIG_ACCESS "RW" |
| #define DMA_CH11_AL3_READ_ADDR_TRIG_RESET "-" |
| #define DMA_CH11_AL3_TRANS_COUNT_ACCESS "RW" |
| #define DMA_CH11_AL3_TRANS_COUNT_RESET "-" |
| #define DMA_CH11_AL3_WRITE_ADDR_ACCESS "RW" |
| #define DMA_CH11_AL3_WRITE_ADDR_RESET "-" |
| #define DMA_CH11_CTRL_TRIG_AHB_ERROR_ACCESS "RO" |
| #define DMA_CH11_CTRL_TRIG_BSWAP_ACCESS "RW" |
| #define DMA_CH11_CTRL_TRIG_BUSY_ACCESS "RO" |
| #define DMA_CH11_CTRL_TRIG_CHAIN_TO_ACCESS "RW" |
| #define DMA_CH11_CTRL_TRIG_DATA_SIZE_ACCESS "RW" |
| #define DMA_CH11_CTRL_TRIG_EN_ACCESS "RW" |
| #define DMA_CH11_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" |
| #define DMA_CH11_CTRL_TRIG_INCR_READ_ACCESS "RW" |
| #define DMA_CH11_CTRL_TRIG_INCR_READ_REV_ACCESS "RW" |
| #define DMA_CH11_CTRL_TRIG_INCR_WRITE_ACCESS "RW" |
| #define DMA_CH11_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW" |
| #define DMA_CH11_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" |
| #define DMA_CH11_CTRL_TRIG_READ_ERROR_ACCESS "WC" |
| #define DMA_CH11_CTRL_TRIG_RING_SEL_ACCESS "RW" |
| #define DMA_CH11_CTRL_TRIG_RING_SIZE_ACCESS "RW" |
| #define DMA_CH11_CTRL_TRIG_SNIFF_EN_ACCESS "RW" |
| #define DMA_CH11_CTRL_TRIG_TREQ_SEL_ACCESS "RW" |
| #define DMA_CH11_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" |
| #define DMA_CH11_DBG_CTDREQ_ACCESS "WC" |
| #define DMA_CH11_DBG_TCR_ACCESS "RO" |
| #define DMA_CH11_READ_ADDR_ACCESS "RW" |
| #define DMA_CH11_TRANS_COUNT_COUNT_ACCESS "RW" |
| #define DMA_CH11_TRANS_COUNT_MODE_ACCESS "RW" |
| #define DMA_CH11_WRITE_ADDR_ACCESS "RW" |
| #define DMA_CH12_AL1_CTRL_ACCESS "RW" |
| #define DMA_CH12_AL1_CTRL_RESET "-" |
| #define DMA_CH12_AL1_READ_ADDR_ACCESS "RW" |
| #define DMA_CH12_AL1_READ_ADDR_RESET "-" |
| #define DMA_CH12_AL1_TRANS_COUNT_TRIG_ACCESS "RW" |
| #define DMA_CH12_AL1_TRANS_COUNT_TRIG_RESET "-" |
| #define DMA_CH12_AL1_WRITE_ADDR_ACCESS "RW" |
| #define DMA_CH12_AL1_WRITE_ADDR_RESET "-" |
| #define DMA_CH12_AL2_CTRL_ACCESS "RW" |
| #define DMA_CH12_AL2_CTRL_RESET "-" |
| #define DMA_CH12_AL2_READ_ADDR_ACCESS "RW" |
| #define DMA_CH12_AL2_READ_ADDR_RESET "-" |
| #define DMA_CH12_AL2_TRANS_COUNT_ACCESS "RW" |
| #define DMA_CH12_AL2_TRANS_COUNT_RESET "-" |
| #define DMA_CH12_AL2_WRITE_ADDR_TRIG_ACCESS "RW" |
| #define DMA_CH12_AL2_WRITE_ADDR_TRIG_RESET "-" |
| #define DMA_CH12_AL3_CTRL_ACCESS "RW" |
| #define DMA_CH12_AL3_CTRL_RESET "-" |
| #define DMA_CH12_AL3_READ_ADDR_TRIG_ACCESS "RW" |
| #define DMA_CH12_AL3_READ_ADDR_TRIG_RESET "-" |
| #define DMA_CH12_AL3_TRANS_COUNT_ACCESS "RW" |
| #define DMA_CH12_AL3_TRANS_COUNT_RESET "-" |
| #define DMA_CH12_AL3_WRITE_ADDR_ACCESS "RW" |
| #define DMA_CH12_AL3_WRITE_ADDR_RESET "-" |
| #define DMA_CH12_CTRL_TRIG_AHB_ERROR_ACCESS "RO" |
| #define DMA_CH12_CTRL_TRIG_BSWAP_ACCESS "RW" |
| #define DMA_CH12_CTRL_TRIG_BUSY_ACCESS "RO" |
| #define DMA_CH12_CTRL_TRIG_CHAIN_TO_ACCESS "RW" |
| #define DMA_CH12_CTRL_TRIG_DATA_SIZE_ACCESS "RW" |
| #define DMA_CH12_CTRL_TRIG_EN_ACCESS "RW" |
| #define DMA_CH12_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" |
| #define DMA_CH12_CTRL_TRIG_INCR_READ_ACCESS "RW" |
| #define DMA_CH12_CTRL_TRIG_INCR_READ_REV_ACCESS "RW" |
| #define DMA_CH12_CTRL_TRIG_INCR_WRITE_ACCESS "RW" |
| #define DMA_CH12_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW" |
| #define DMA_CH12_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" |
| #define DMA_CH12_CTRL_TRIG_READ_ERROR_ACCESS "WC" |
| #define DMA_CH12_CTRL_TRIG_RING_SEL_ACCESS "RW" |
| #define DMA_CH12_CTRL_TRIG_RING_SIZE_ACCESS "RW" |
| #define DMA_CH12_CTRL_TRIG_SNIFF_EN_ACCESS "RW" |
| #define DMA_CH12_CTRL_TRIG_TREQ_SEL_ACCESS "RW" |
| #define DMA_CH12_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" |
| #define DMA_CH12_DBG_CTDREQ_ACCESS "WC" |
| #define DMA_CH12_DBG_TCR_ACCESS "RO" |
| #define DMA_CH12_READ_ADDR_ACCESS "RW" |
| #define DMA_CH12_TRANS_COUNT_COUNT_ACCESS "RW" |
| #define DMA_CH12_TRANS_COUNT_MODE_ACCESS "RW" |
| #define DMA_CH12_WRITE_ADDR_ACCESS "RW" |
| #define DMA_CH13_AL1_CTRL_ACCESS "RW" |
| #define DMA_CH13_AL1_CTRL_RESET "-" |
| #define DMA_CH13_AL1_READ_ADDR_ACCESS "RW" |
| #define DMA_CH13_AL1_READ_ADDR_RESET "-" |
| #define DMA_CH13_AL1_TRANS_COUNT_TRIG_ACCESS "RW" |
| #define DMA_CH13_AL1_TRANS_COUNT_TRIG_RESET "-" |
| #define DMA_CH13_AL1_WRITE_ADDR_ACCESS "RW" |
| #define DMA_CH13_AL1_WRITE_ADDR_RESET "-" |
| #define DMA_CH13_AL2_CTRL_ACCESS "RW" |
| #define DMA_CH13_AL2_CTRL_RESET "-" |
| #define DMA_CH13_AL2_READ_ADDR_ACCESS "RW" |
| #define DMA_CH13_AL2_READ_ADDR_RESET "-" |
| #define DMA_CH13_AL2_TRANS_COUNT_ACCESS "RW" |
| #define DMA_CH13_AL2_TRANS_COUNT_RESET "-" |
| #define DMA_CH13_AL2_WRITE_ADDR_TRIG_ACCESS "RW" |
| #define DMA_CH13_AL2_WRITE_ADDR_TRIG_RESET "-" |
| #define DMA_CH13_AL3_CTRL_ACCESS "RW" |
| #define DMA_CH13_AL3_CTRL_RESET "-" |
| #define DMA_CH13_AL3_READ_ADDR_TRIG_ACCESS "RW" |
| #define DMA_CH13_AL3_READ_ADDR_TRIG_RESET "-" |
| #define DMA_CH13_AL3_TRANS_COUNT_ACCESS "RW" |
| #define DMA_CH13_AL3_TRANS_COUNT_RESET "-" |
| #define DMA_CH13_AL3_WRITE_ADDR_ACCESS "RW" |
| #define DMA_CH13_AL3_WRITE_ADDR_RESET "-" |
| #define DMA_CH13_CTRL_TRIG_AHB_ERROR_ACCESS "RO" |
| #define DMA_CH13_CTRL_TRIG_BSWAP_ACCESS "RW" |
| #define DMA_CH13_CTRL_TRIG_BUSY_ACCESS "RO" |
| #define DMA_CH13_CTRL_TRIG_CHAIN_TO_ACCESS "RW" |
| #define DMA_CH13_CTRL_TRIG_DATA_SIZE_ACCESS "RW" |
| #define DMA_CH13_CTRL_TRIG_EN_ACCESS "RW" |
| #define DMA_CH13_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" |
| #define DMA_CH13_CTRL_TRIG_INCR_READ_ACCESS "RW" |
| #define DMA_CH13_CTRL_TRIG_INCR_READ_REV_ACCESS "RW" |
| #define DMA_CH13_CTRL_TRIG_INCR_WRITE_ACCESS "RW" |
| #define DMA_CH13_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW" |
| #define DMA_CH13_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" |
| #define DMA_CH13_CTRL_TRIG_READ_ERROR_ACCESS "WC" |
| #define DMA_CH13_CTRL_TRIG_RING_SEL_ACCESS "RW" |
| #define DMA_CH13_CTRL_TRIG_RING_SIZE_ACCESS "RW" |
| #define DMA_CH13_CTRL_TRIG_SNIFF_EN_ACCESS "RW" |
| #define DMA_CH13_CTRL_TRIG_TREQ_SEL_ACCESS "RW" |
| #define DMA_CH13_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" |
| #define DMA_CH13_DBG_CTDREQ_ACCESS "WC" |
| #define DMA_CH13_DBG_TCR_ACCESS "RO" |
| #define DMA_CH13_READ_ADDR_ACCESS "RW" |
| #define DMA_CH13_TRANS_COUNT_COUNT_ACCESS "RW" |
| #define DMA_CH13_TRANS_COUNT_MODE_ACCESS "RW" |
| #define DMA_CH13_WRITE_ADDR_ACCESS "RW" |
| #define DMA_CH14_AL1_CTRL_ACCESS "RW" |
| #define DMA_CH14_AL1_CTRL_RESET "-" |
| #define DMA_CH14_AL1_READ_ADDR_ACCESS "RW" |
| #define DMA_CH14_AL1_READ_ADDR_RESET "-" |
| #define DMA_CH14_AL1_TRANS_COUNT_TRIG_ACCESS "RW" |
| #define DMA_CH14_AL1_TRANS_COUNT_TRIG_RESET "-" |
| #define DMA_CH14_AL1_WRITE_ADDR_ACCESS "RW" |
| #define DMA_CH14_AL1_WRITE_ADDR_RESET "-" |
| #define DMA_CH14_AL2_CTRL_ACCESS "RW" |
| #define DMA_CH14_AL2_CTRL_RESET "-" |
| #define DMA_CH14_AL2_READ_ADDR_ACCESS "RW" |
| #define DMA_CH14_AL2_READ_ADDR_RESET "-" |
| #define DMA_CH14_AL2_TRANS_COUNT_ACCESS "RW" |
| #define DMA_CH14_AL2_TRANS_COUNT_RESET "-" |
| #define DMA_CH14_AL2_WRITE_ADDR_TRIG_ACCESS "RW" |
| #define DMA_CH14_AL2_WRITE_ADDR_TRIG_RESET "-" |
| #define DMA_CH14_AL3_CTRL_ACCESS "RW" |
| #define DMA_CH14_AL3_CTRL_RESET "-" |
| #define DMA_CH14_AL3_READ_ADDR_TRIG_ACCESS "RW" |
| #define DMA_CH14_AL3_READ_ADDR_TRIG_RESET "-" |
| #define DMA_CH14_AL3_TRANS_COUNT_ACCESS "RW" |
| #define DMA_CH14_AL3_TRANS_COUNT_RESET "-" |
| #define DMA_CH14_AL3_WRITE_ADDR_ACCESS "RW" |
| #define DMA_CH14_AL3_WRITE_ADDR_RESET "-" |
| #define DMA_CH14_CTRL_TRIG_AHB_ERROR_ACCESS "RO" |
| #define DMA_CH14_CTRL_TRIG_BSWAP_ACCESS "RW" |
| #define DMA_CH14_CTRL_TRIG_BUSY_ACCESS "RO" |
| #define DMA_CH14_CTRL_TRIG_CHAIN_TO_ACCESS "RW" |
| #define DMA_CH14_CTRL_TRIG_DATA_SIZE_ACCESS "RW" |
| #define DMA_CH14_CTRL_TRIG_EN_ACCESS "RW" |
| #define DMA_CH14_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" |
| #define DMA_CH14_CTRL_TRIG_INCR_READ_ACCESS "RW" |
| #define DMA_CH14_CTRL_TRIG_INCR_READ_REV_ACCESS "RW" |
| #define DMA_CH14_CTRL_TRIG_INCR_WRITE_ACCESS "RW" |
| #define DMA_CH14_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW" |
| #define DMA_CH14_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" |
| #define DMA_CH14_CTRL_TRIG_READ_ERROR_ACCESS "WC" |
| #define DMA_CH14_CTRL_TRIG_RING_SEL_ACCESS "RW" |
| #define DMA_CH14_CTRL_TRIG_RING_SIZE_ACCESS "RW" |
| #define DMA_CH14_CTRL_TRIG_SNIFF_EN_ACCESS "RW" |
| #define DMA_CH14_CTRL_TRIG_TREQ_SEL_ACCESS "RW" |
| #define DMA_CH14_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" |
| #define DMA_CH14_DBG_CTDREQ_ACCESS "WC" |
| #define DMA_CH14_DBG_TCR_ACCESS "RO" |
| #define DMA_CH14_READ_ADDR_ACCESS "RW" |
| #define DMA_CH14_TRANS_COUNT_COUNT_ACCESS "RW" |
| #define DMA_CH14_TRANS_COUNT_MODE_ACCESS "RW" |
| #define DMA_CH14_WRITE_ADDR_ACCESS "RW" |
| #define DMA_CH15_AL1_CTRL_ACCESS "RW" |
| #define DMA_CH15_AL1_CTRL_RESET "-" |
| #define DMA_CH15_AL1_READ_ADDR_ACCESS "RW" |
| #define DMA_CH15_AL1_READ_ADDR_RESET "-" |
| #define DMA_CH15_AL1_TRANS_COUNT_TRIG_ACCESS "RW" |
| #define DMA_CH15_AL1_TRANS_COUNT_TRIG_RESET "-" |
| #define DMA_CH15_AL1_WRITE_ADDR_ACCESS "RW" |
| #define DMA_CH15_AL1_WRITE_ADDR_RESET "-" |
| #define DMA_CH15_AL2_CTRL_ACCESS "RW" |
| #define DMA_CH15_AL2_CTRL_RESET "-" |
| #define DMA_CH15_AL2_READ_ADDR_ACCESS "RW" |
| #define DMA_CH15_AL2_READ_ADDR_RESET "-" |
| #define DMA_CH15_AL2_TRANS_COUNT_ACCESS "RW" |
| #define DMA_CH15_AL2_TRANS_COUNT_RESET "-" |
| #define DMA_CH15_AL2_WRITE_ADDR_TRIG_ACCESS "RW" |
| #define DMA_CH15_AL2_WRITE_ADDR_TRIG_RESET "-" |
| #define DMA_CH15_AL3_CTRL_ACCESS "RW" |
| #define DMA_CH15_AL3_CTRL_RESET "-" |
| #define DMA_CH15_AL3_READ_ADDR_TRIG_ACCESS "RW" |
| #define DMA_CH15_AL3_READ_ADDR_TRIG_RESET "-" |
| #define DMA_CH15_AL3_TRANS_COUNT_ACCESS "RW" |
| #define DMA_CH15_AL3_TRANS_COUNT_RESET "-" |
| #define DMA_CH15_AL3_WRITE_ADDR_ACCESS "RW" |
| #define DMA_CH15_AL3_WRITE_ADDR_RESET "-" |
| #define DMA_CH15_CTRL_TRIG_AHB_ERROR_ACCESS "RO" |
| #define DMA_CH15_CTRL_TRIG_BSWAP_ACCESS "RW" |
| #define DMA_CH15_CTRL_TRIG_BUSY_ACCESS "RO" |
| #define DMA_CH15_CTRL_TRIG_CHAIN_TO_ACCESS "RW" |
| #define DMA_CH15_CTRL_TRIG_DATA_SIZE_ACCESS "RW" |
| #define DMA_CH15_CTRL_TRIG_EN_ACCESS "RW" |
| #define DMA_CH15_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" |
| #define DMA_CH15_CTRL_TRIG_INCR_READ_ACCESS "RW" |
| #define DMA_CH15_CTRL_TRIG_INCR_READ_REV_ACCESS "RW" |
| #define DMA_CH15_CTRL_TRIG_INCR_WRITE_ACCESS "RW" |
| #define DMA_CH15_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW" |
| #define DMA_CH15_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" |
| #define DMA_CH15_CTRL_TRIG_READ_ERROR_ACCESS "WC" |
| #define DMA_CH15_CTRL_TRIG_RING_SEL_ACCESS "RW" |
| #define DMA_CH15_CTRL_TRIG_RING_SIZE_ACCESS "RW" |
| #define DMA_CH15_CTRL_TRIG_SNIFF_EN_ACCESS "RW" |
| #define DMA_CH15_CTRL_TRIG_TREQ_SEL_ACCESS "RW" |
| #define DMA_CH15_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" |
| #define DMA_CH15_DBG_CTDREQ_ACCESS "WC" |
| #define DMA_CH15_DBG_TCR_ACCESS "RO" |
| #define DMA_CH15_READ_ADDR_ACCESS "RW" |
| #define DMA_CH15_TRANS_COUNT_COUNT_ACCESS "RW" |
| #define DMA_CH15_TRANS_COUNT_MODE_ACCESS "RW" |
| #define DMA_CH15_WRITE_ADDR_ACCESS "RW" |
| #define DMA_CH1_AL1_CTRL_ACCESS "RW" |
| #define DMA_CH1_AL1_CTRL_RESET "-" |
| #define DMA_CH1_AL1_READ_ADDR_ACCESS "RW" |
| #define DMA_CH1_AL1_READ_ADDR_RESET "-" |
| #define DMA_CH1_AL1_TRANS_COUNT_TRIG_ACCESS "RW" |
| #define DMA_CH1_AL1_TRANS_COUNT_TRIG_RESET "-" |
| #define DMA_CH1_AL1_WRITE_ADDR_ACCESS "RW" |
| #define DMA_CH1_AL1_WRITE_ADDR_RESET "-" |
| #define DMA_CH1_AL2_CTRL_ACCESS "RW" |
| #define DMA_CH1_AL2_CTRL_RESET "-" |
| #define DMA_CH1_AL2_READ_ADDR_ACCESS "RW" |
| #define DMA_CH1_AL2_READ_ADDR_RESET "-" |
| #define DMA_CH1_AL2_TRANS_COUNT_ACCESS "RW" |
| #define DMA_CH1_AL2_TRANS_COUNT_RESET "-" |
| #define DMA_CH1_AL2_WRITE_ADDR_TRIG_ACCESS "RW" |
| #define DMA_CH1_AL2_WRITE_ADDR_TRIG_RESET "-" |
| #define DMA_CH1_AL3_CTRL_ACCESS "RW" |
| #define DMA_CH1_AL3_CTRL_RESET "-" |
| #define DMA_CH1_AL3_READ_ADDR_TRIG_ACCESS "RW" |
| #define DMA_CH1_AL3_READ_ADDR_TRIG_RESET "-" |
| #define DMA_CH1_AL3_TRANS_COUNT_ACCESS "RW" |
| #define DMA_CH1_AL3_TRANS_COUNT_RESET "-" |
| #define DMA_CH1_AL3_WRITE_ADDR_ACCESS "RW" |
| #define DMA_CH1_AL3_WRITE_ADDR_RESET "-" |
| #define DMA_CH1_CTRL_TRIG_AHB_ERROR_ACCESS "RO" |
| #define DMA_CH1_CTRL_TRIG_BSWAP_ACCESS "RW" |
| #define DMA_CH1_CTRL_TRIG_BUSY_ACCESS "RO" |
| #define DMA_CH1_CTRL_TRIG_CHAIN_TO_ACCESS "RW" |
| #define DMA_CH1_CTRL_TRIG_DATA_SIZE_ACCESS "RW" |
| #define DMA_CH1_CTRL_TRIG_EN_ACCESS "RW" |
| #define DMA_CH1_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" |
| #define DMA_CH1_CTRL_TRIG_INCR_READ_ACCESS "RW" |
| #define DMA_CH1_CTRL_TRIG_INCR_READ_REV_ACCESS "RW" |
| #define DMA_CH1_CTRL_TRIG_INCR_WRITE_ACCESS "RW" |
| #define DMA_CH1_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW" |
| #define DMA_CH1_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" |
| #define DMA_CH1_CTRL_TRIG_READ_ERROR_ACCESS "WC" |
| #define DMA_CH1_CTRL_TRIG_RING_SEL_ACCESS "RW" |
| #define DMA_CH1_CTRL_TRIG_RING_SIZE_ACCESS "RW" |
| #define DMA_CH1_CTRL_TRIG_SNIFF_EN_ACCESS "RW" |
| #define DMA_CH1_CTRL_TRIG_TREQ_SEL_ACCESS "RW" |
| #define DMA_CH1_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" |
| #define DMA_CH1_DBG_CTDREQ_ACCESS "WC" |
| #define DMA_CH1_DBG_TCR_ACCESS "RO" |
| #define DMA_CH1_READ_ADDR_ACCESS "RW" |
| #define DMA_CH1_TRANS_COUNT_COUNT_ACCESS "RW" |
| #define DMA_CH1_TRANS_COUNT_MODE_ACCESS "RW" |
| #define DMA_CH1_WRITE_ADDR_ACCESS "RW" |
| #define DMA_CH2_AL1_CTRL_ACCESS "RW" |
| #define DMA_CH2_AL1_CTRL_RESET "-" |
| #define DMA_CH2_AL1_READ_ADDR_ACCESS "RW" |
| #define DMA_CH2_AL1_READ_ADDR_RESET "-" |
| #define DMA_CH2_AL1_TRANS_COUNT_TRIG_ACCESS "RW" |
| #define DMA_CH2_AL1_TRANS_COUNT_TRIG_RESET "-" |
| #define DMA_CH2_AL1_WRITE_ADDR_ACCESS "RW" |
| #define DMA_CH2_AL1_WRITE_ADDR_RESET "-" |
| #define DMA_CH2_AL2_CTRL_ACCESS "RW" |
| #define DMA_CH2_AL2_CTRL_RESET "-" |
| #define DMA_CH2_AL2_READ_ADDR_ACCESS "RW" |
| #define DMA_CH2_AL2_READ_ADDR_RESET "-" |
| #define DMA_CH2_AL2_TRANS_COUNT_ACCESS "RW" |
| #define DMA_CH2_AL2_TRANS_COUNT_RESET "-" |
| #define DMA_CH2_AL2_WRITE_ADDR_TRIG_ACCESS "RW" |
| #define DMA_CH2_AL2_WRITE_ADDR_TRIG_RESET "-" |
| #define DMA_CH2_AL3_CTRL_ACCESS "RW" |
| #define DMA_CH2_AL3_CTRL_RESET "-" |
| #define DMA_CH2_AL3_READ_ADDR_TRIG_ACCESS "RW" |
| #define DMA_CH2_AL3_READ_ADDR_TRIG_RESET "-" |
| #define DMA_CH2_AL3_TRANS_COUNT_ACCESS "RW" |
| #define DMA_CH2_AL3_TRANS_COUNT_RESET "-" |
| #define DMA_CH2_AL3_WRITE_ADDR_ACCESS "RW" |
| #define DMA_CH2_AL3_WRITE_ADDR_RESET "-" |
| #define DMA_CH2_CTRL_TRIG_AHB_ERROR_ACCESS "RO" |
| #define DMA_CH2_CTRL_TRIG_BSWAP_ACCESS "RW" |
| #define DMA_CH2_CTRL_TRIG_BUSY_ACCESS "RO" |
| #define DMA_CH2_CTRL_TRIG_CHAIN_TO_ACCESS "RW" |
| #define DMA_CH2_CTRL_TRIG_DATA_SIZE_ACCESS "RW" |
| #define DMA_CH2_CTRL_TRIG_EN_ACCESS "RW" |
| #define DMA_CH2_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" |
| #define DMA_CH2_CTRL_TRIG_INCR_READ_ACCESS "RW" |
| #define DMA_CH2_CTRL_TRIG_INCR_READ_REV_ACCESS "RW" |
| #define DMA_CH2_CTRL_TRIG_INCR_WRITE_ACCESS "RW" |
| #define DMA_CH2_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW" |
| #define DMA_CH2_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" |
| #define DMA_CH2_CTRL_TRIG_READ_ERROR_ACCESS "WC" |
| #define DMA_CH2_CTRL_TRIG_RING_SEL_ACCESS "RW" |
| #define DMA_CH2_CTRL_TRIG_RING_SIZE_ACCESS "RW" |
| #define DMA_CH2_CTRL_TRIG_SNIFF_EN_ACCESS "RW" |
| #define DMA_CH2_CTRL_TRIG_TREQ_SEL_ACCESS "RW" |
| #define DMA_CH2_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" |
| #define DMA_CH2_DBG_CTDREQ_ACCESS "WC" |
| #define DMA_CH2_DBG_TCR_ACCESS "RO" |
| #define DMA_CH2_READ_ADDR_ACCESS "RW" |
| #define DMA_CH2_TRANS_COUNT_COUNT_ACCESS "RW" |
| #define DMA_CH2_TRANS_COUNT_MODE_ACCESS "RW" |
| #define DMA_CH2_WRITE_ADDR_ACCESS "RW" |
| #define DMA_CH3_AL1_CTRL_ACCESS "RW" |
| #define DMA_CH3_AL1_CTRL_RESET "-" |
| #define DMA_CH3_AL1_READ_ADDR_ACCESS "RW" |
| #define DMA_CH3_AL1_READ_ADDR_RESET "-" |
| #define DMA_CH3_AL1_TRANS_COUNT_TRIG_ACCESS "RW" |
| #define DMA_CH3_AL1_TRANS_COUNT_TRIG_RESET "-" |
| #define DMA_CH3_AL1_WRITE_ADDR_ACCESS "RW" |
| #define DMA_CH3_AL1_WRITE_ADDR_RESET "-" |
| #define DMA_CH3_AL2_CTRL_ACCESS "RW" |
| #define DMA_CH3_AL2_CTRL_RESET "-" |
| #define DMA_CH3_AL2_READ_ADDR_ACCESS "RW" |
| #define DMA_CH3_AL2_READ_ADDR_RESET "-" |
| #define DMA_CH3_AL2_TRANS_COUNT_ACCESS "RW" |
| #define DMA_CH3_AL2_TRANS_COUNT_RESET "-" |
| #define DMA_CH3_AL2_WRITE_ADDR_TRIG_ACCESS "RW" |
| #define DMA_CH3_AL2_WRITE_ADDR_TRIG_RESET "-" |
| #define DMA_CH3_AL3_CTRL_ACCESS "RW" |
| #define DMA_CH3_AL3_CTRL_RESET "-" |
| #define DMA_CH3_AL3_READ_ADDR_TRIG_ACCESS "RW" |
| #define DMA_CH3_AL3_READ_ADDR_TRIG_RESET "-" |
| #define DMA_CH3_AL3_TRANS_COUNT_ACCESS "RW" |
| #define DMA_CH3_AL3_TRANS_COUNT_RESET "-" |
| #define DMA_CH3_AL3_WRITE_ADDR_ACCESS "RW" |
| #define DMA_CH3_AL3_WRITE_ADDR_RESET "-" |
| #define DMA_CH3_CTRL_TRIG_AHB_ERROR_ACCESS "RO" |
| #define DMA_CH3_CTRL_TRIG_BSWAP_ACCESS "RW" |
| #define DMA_CH3_CTRL_TRIG_BUSY_ACCESS "RO" |
| #define DMA_CH3_CTRL_TRIG_CHAIN_TO_ACCESS "RW" |
| #define DMA_CH3_CTRL_TRIG_DATA_SIZE_ACCESS "RW" |
| #define DMA_CH3_CTRL_TRIG_EN_ACCESS "RW" |
| #define DMA_CH3_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" |
| #define DMA_CH3_CTRL_TRIG_INCR_READ_ACCESS "RW" |
| #define DMA_CH3_CTRL_TRIG_INCR_READ_REV_ACCESS "RW" |
| #define DMA_CH3_CTRL_TRIG_INCR_WRITE_ACCESS "RW" |
| #define DMA_CH3_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW" |
| #define DMA_CH3_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" |
| #define DMA_CH3_CTRL_TRIG_READ_ERROR_ACCESS "WC" |
| #define DMA_CH3_CTRL_TRIG_RING_SEL_ACCESS "RW" |
| #define DMA_CH3_CTRL_TRIG_RING_SIZE_ACCESS "RW" |
| #define DMA_CH3_CTRL_TRIG_SNIFF_EN_ACCESS "RW" |
| #define DMA_CH3_CTRL_TRIG_TREQ_SEL_ACCESS "RW" |
| #define DMA_CH3_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" |
| #define DMA_CH3_DBG_CTDREQ_ACCESS "WC" |
| #define DMA_CH3_DBG_TCR_ACCESS "RO" |
| #define DMA_CH3_READ_ADDR_ACCESS "RW" |
| #define DMA_CH3_TRANS_COUNT_COUNT_ACCESS "RW" |
| #define DMA_CH3_TRANS_COUNT_MODE_ACCESS "RW" |
| #define DMA_CH3_WRITE_ADDR_ACCESS "RW" |
| #define DMA_CH4_AL1_CTRL_ACCESS "RW" |
| #define DMA_CH4_AL1_CTRL_RESET "-" |
| #define DMA_CH4_AL1_READ_ADDR_ACCESS "RW" |
| #define DMA_CH4_AL1_READ_ADDR_RESET "-" |
| #define DMA_CH4_AL1_TRANS_COUNT_TRIG_ACCESS "RW" |
| #define DMA_CH4_AL1_TRANS_COUNT_TRIG_RESET "-" |
| #define DMA_CH4_AL1_WRITE_ADDR_ACCESS "RW" |
| #define DMA_CH4_AL1_WRITE_ADDR_RESET "-" |
| #define DMA_CH4_AL2_CTRL_ACCESS "RW" |
| #define DMA_CH4_AL2_CTRL_RESET "-" |
| #define DMA_CH4_AL2_READ_ADDR_ACCESS "RW" |
| #define DMA_CH4_AL2_READ_ADDR_RESET "-" |
| #define DMA_CH4_AL2_TRANS_COUNT_ACCESS "RW" |
| #define DMA_CH4_AL2_TRANS_COUNT_RESET "-" |
| #define DMA_CH4_AL2_WRITE_ADDR_TRIG_ACCESS "RW" |
| #define DMA_CH4_AL2_WRITE_ADDR_TRIG_RESET "-" |
| #define DMA_CH4_AL3_CTRL_ACCESS "RW" |
| #define DMA_CH4_AL3_CTRL_RESET "-" |
| #define DMA_CH4_AL3_READ_ADDR_TRIG_ACCESS "RW" |
| #define DMA_CH4_AL3_READ_ADDR_TRIG_RESET "-" |
| #define DMA_CH4_AL3_TRANS_COUNT_ACCESS "RW" |
| #define DMA_CH4_AL3_TRANS_COUNT_RESET "-" |
| #define DMA_CH4_AL3_WRITE_ADDR_ACCESS "RW" |
| #define DMA_CH4_AL3_WRITE_ADDR_RESET "-" |
| #define DMA_CH4_CTRL_TRIG_AHB_ERROR_ACCESS "RO" |
| #define DMA_CH4_CTRL_TRIG_BSWAP_ACCESS "RW" |
| #define DMA_CH4_CTRL_TRIG_BUSY_ACCESS "RO" |
| #define DMA_CH4_CTRL_TRIG_CHAIN_TO_ACCESS "RW" |
| #define DMA_CH4_CTRL_TRIG_DATA_SIZE_ACCESS "RW" |
| #define DMA_CH4_CTRL_TRIG_EN_ACCESS "RW" |
| #define DMA_CH4_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" |
| #define DMA_CH4_CTRL_TRIG_INCR_READ_ACCESS "RW" |
| #define DMA_CH4_CTRL_TRIG_INCR_READ_REV_ACCESS "RW" |
| #define DMA_CH4_CTRL_TRIG_INCR_WRITE_ACCESS "RW" |
| #define DMA_CH4_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW" |
| #define DMA_CH4_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" |
| #define DMA_CH4_CTRL_TRIG_READ_ERROR_ACCESS "WC" |
| #define DMA_CH4_CTRL_TRIG_RING_SEL_ACCESS "RW" |
| #define DMA_CH4_CTRL_TRIG_RING_SIZE_ACCESS "RW" |
| #define DMA_CH4_CTRL_TRIG_SNIFF_EN_ACCESS "RW" |
| #define DMA_CH4_CTRL_TRIG_TREQ_SEL_ACCESS "RW" |
| #define DMA_CH4_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" |
| #define DMA_CH4_DBG_CTDREQ_ACCESS "WC" |
| #define DMA_CH4_DBG_TCR_ACCESS "RO" |
| #define DMA_CH4_READ_ADDR_ACCESS "RW" |
| #define DMA_CH4_TRANS_COUNT_COUNT_ACCESS "RW" |
| #define DMA_CH4_TRANS_COUNT_MODE_ACCESS "RW" |
| #define DMA_CH4_WRITE_ADDR_ACCESS "RW" |
| #define DMA_CH5_AL1_CTRL_ACCESS "RW" |
| #define DMA_CH5_AL1_CTRL_RESET "-" |
| #define DMA_CH5_AL1_READ_ADDR_ACCESS "RW" |
| #define DMA_CH5_AL1_READ_ADDR_RESET "-" |
| #define DMA_CH5_AL1_TRANS_COUNT_TRIG_ACCESS "RW" |
| #define DMA_CH5_AL1_TRANS_COUNT_TRIG_RESET "-" |
| #define DMA_CH5_AL1_WRITE_ADDR_ACCESS "RW" |
| #define DMA_CH5_AL1_WRITE_ADDR_RESET "-" |
| #define DMA_CH5_AL2_CTRL_ACCESS "RW" |
| #define DMA_CH5_AL2_CTRL_RESET "-" |
| #define DMA_CH5_AL2_READ_ADDR_ACCESS "RW" |
| #define DMA_CH5_AL2_READ_ADDR_RESET "-" |
| #define DMA_CH5_AL2_TRANS_COUNT_ACCESS "RW" |
| #define DMA_CH5_AL2_TRANS_COUNT_RESET "-" |
| #define DMA_CH5_AL2_WRITE_ADDR_TRIG_ACCESS "RW" |
| #define DMA_CH5_AL2_WRITE_ADDR_TRIG_RESET "-" |
| #define DMA_CH5_AL3_CTRL_ACCESS "RW" |
| #define DMA_CH5_AL3_CTRL_RESET "-" |
| #define DMA_CH5_AL3_READ_ADDR_TRIG_ACCESS "RW" |
| #define DMA_CH5_AL3_READ_ADDR_TRIG_RESET "-" |
| #define DMA_CH5_AL3_TRANS_COUNT_ACCESS "RW" |
| #define DMA_CH5_AL3_TRANS_COUNT_RESET "-" |
| #define DMA_CH5_AL3_WRITE_ADDR_ACCESS "RW" |
| #define DMA_CH5_AL3_WRITE_ADDR_RESET "-" |
| #define DMA_CH5_CTRL_TRIG_AHB_ERROR_ACCESS "RO" |
| #define DMA_CH5_CTRL_TRIG_BSWAP_ACCESS "RW" |
| #define DMA_CH5_CTRL_TRIG_BUSY_ACCESS "RO" |
| #define DMA_CH5_CTRL_TRIG_CHAIN_TO_ACCESS "RW" |
| #define DMA_CH5_CTRL_TRIG_DATA_SIZE_ACCESS "RW" |
| #define DMA_CH5_CTRL_TRIG_EN_ACCESS "RW" |
| #define DMA_CH5_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" |
| #define DMA_CH5_CTRL_TRIG_INCR_READ_ACCESS "RW" |
| #define DMA_CH5_CTRL_TRIG_INCR_READ_REV_ACCESS "RW" |
| #define DMA_CH5_CTRL_TRIG_INCR_WRITE_ACCESS "RW" |
| #define DMA_CH5_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW" |
| #define DMA_CH5_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" |
| #define DMA_CH5_CTRL_TRIG_READ_ERROR_ACCESS "WC" |
| #define DMA_CH5_CTRL_TRIG_RING_SEL_ACCESS "RW" |
| #define DMA_CH5_CTRL_TRIG_RING_SIZE_ACCESS "RW" |
| #define DMA_CH5_CTRL_TRIG_SNIFF_EN_ACCESS "RW" |
| #define DMA_CH5_CTRL_TRIG_TREQ_SEL_ACCESS "RW" |
| #define DMA_CH5_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" |
| #define DMA_CH5_DBG_CTDREQ_ACCESS "WC" |
| #define DMA_CH5_DBG_TCR_ACCESS "RO" |
| #define DMA_CH5_READ_ADDR_ACCESS "RW" |
| #define DMA_CH5_TRANS_COUNT_COUNT_ACCESS "RW" |
| #define DMA_CH5_TRANS_COUNT_MODE_ACCESS "RW" |
| #define DMA_CH5_WRITE_ADDR_ACCESS "RW" |
| #define DMA_CH6_AL1_CTRL_ACCESS "RW" |
| #define DMA_CH6_AL1_CTRL_RESET "-" |
| #define DMA_CH6_AL1_READ_ADDR_ACCESS "RW" |
| #define DMA_CH6_AL1_READ_ADDR_RESET "-" |
| #define DMA_CH6_AL1_TRANS_COUNT_TRIG_ACCESS "RW" |
| #define DMA_CH6_AL1_TRANS_COUNT_TRIG_RESET "-" |
| #define DMA_CH6_AL1_WRITE_ADDR_ACCESS "RW" |
| #define DMA_CH6_AL1_WRITE_ADDR_RESET "-" |
| #define DMA_CH6_AL2_CTRL_ACCESS "RW" |
| #define DMA_CH6_AL2_CTRL_RESET "-" |
| #define DMA_CH6_AL2_READ_ADDR_ACCESS "RW" |
| #define DMA_CH6_AL2_READ_ADDR_RESET "-" |
| #define DMA_CH6_AL2_TRANS_COUNT_ACCESS "RW" |
| #define DMA_CH6_AL2_TRANS_COUNT_RESET "-" |
| #define DMA_CH6_AL2_WRITE_ADDR_TRIG_ACCESS "RW" |
| #define DMA_CH6_AL2_WRITE_ADDR_TRIG_RESET "-" |
| #define DMA_CH6_AL3_CTRL_ACCESS "RW" |
| #define DMA_CH6_AL3_CTRL_RESET "-" |
| #define DMA_CH6_AL3_READ_ADDR_TRIG_ACCESS "RW" |
| #define DMA_CH6_AL3_READ_ADDR_TRIG_RESET "-" |
| #define DMA_CH6_AL3_TRANS_COUNT_ACCESS "RW" |
| #define DMA_CH6_AL3_TRANS_COUNT_RESET "-" |
| #define DMA_CH6_AL3_WRITE_ADDR_ACCESS "RW" |
| #define DMA_CH6_AL3_WRITE_ADDR_RESET "-" |
| #define DMA_CH6_CTRL_TRIG_AHB_ERROR_ACCESS "RO" |
| #define DMA_CH6_CTRL_TRIG_BSWAP_ACCESS "RW" |
| #define DMA_CH6_CTRL_TRIG_BUSY_ACCESS "RO" |
| #define DMA_CH6_CTRL_TRIG_CHAIN_TO_ACCESS "RW" |
| #define DMA_CH6_CTRL_TRIG_DATA_SIZE_ACCESS "RW" |
| #define DMA_CH6_CTRL_TRIG_EN_ACCESS "RW" |
| #define DMA_CH6_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" |
| #define DMA_CH6_CTRL_TRIG_INCR_READ_ACCESS "RW" |
| #define DMA_CH6_CTRL_TRIG_INCR_READ_REV_ACCESS "RW" |
| #define DMA_CH6_CTRL_TRIG_INCR_WRITE_ACCESS "RW" |
| #define DMA_CH6_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW" |
| #define DMA_CH6_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" |
| #define DMA_CH6_CTRL_TRIG_READ_ERROR_ACCESS "WC" |
| #define DMA_CH6_CTRL_TRIG_RING_SEL_ACCESS "RW" |
| #define DMA_CH6_CTRL_TRIG_RING_SIZE_ACCESS "RW" |
| #define DMA_CH6_CTRL_TRIG_SNIFF_EN_ACCESS "RW" |
| #define DMA_CH6_CTRL_TRIG_TREQ_SEL_ACCESS "RW" |
| #define DMA_CH6_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" |
| #define DMA_CH6_DBG_CTDREQ_ACCESS "WC" |
| #define DMA_CH6_DBG_TCR_ACCESS "RO" |
| #define DMA_CH6_READ_ADDR_ACCESS "RW" |
| #define DMA_CH6_TRANS_COUNT_COUNT_ACCESS "RW" |
| #define DMA_CH6_TRANS_COUNT_MODE_ACCESS "RW" |
| #define DMA_CH6_WRITE_ADDR_ACCESS "RW" |
| #define DMA_CH7_AL1_CTRL_ACCESS "RW" |
| #define DMA_CH7_AL1_CTRL_RESET "-" |
| #define DMA_CH7_AL1_READ_ADDR_ACCESS "RW" |
| #define DMA_CH7_AL1_READ_ADDR_RESET "-" |
| #define DMA_CH7_AL1_TRANS_COUNT_TRIG_ACCESS "RW" |
| #define DMA_CH7_AL1_TRANS_COUNT_TRIG_RESET "-" |
| #define DMA_CH7_AL1_WRITE_ADDR_ACCESS "RW" |
| #define DMA_CH7_AL1_WRITE_ADDR_RESET "-" |
| #define DMA_CH7_AL2_CTRL_ACCESS "RW" |
| #define DMA_CH7_AL2_CTRL_RESET "-" |
| #define DMA_CH7_AL2_READ_ADDR_ACCESS "RW" |
| #define DMA_CH7_AL2_READ_ADDR_RESET "-" |
| #define DMA_CH7_AL2_TRANS_COUNT_ACCESS "RW" |
| #define DMA_CH7_AL2_TRANS_COUNT_RESET "-" |
| #define DMA_CH7_AL2_WRITE_ADDR_TRIG_ACCESS "RW" |
| #define DMA_CH7_AL2_WRITE_ADDR_TRIG_RESET "-" |
| #define DMA_CH7_AL3_CTRL_ACCESS "RW" |
| #define DMA_CH7_AL3_CTRL_RESET "-" |
| #define DMA_CH7_AL3_READ_ADDR_TRIG_ACCESS "RW" |
| #define DMA_CH7_AL3_READ_ADDR_TRIG_RESET "-" |
| #define DMA_CH7_AL3_TRANS_COUNT_ACCESS "RW" |
| #define DMA_CH7_AL3_TRANS_COUNT_RESET "-" |
| #define DMA_CH7_AL3_WRITE_ADDR_ACCESS "RW" |
| #define DMA_CH7_AL3_WRITE_ADDR_RESET "-" |
| #define DMA_CH7_CTRL_TRIG_AHB_ERROR_ACCESS "RO" |
| #define DMA_CH7_CTRL_TRIG_BSWAP_ACCESS "RW" |
| #define DMA_CH7_CTRL_TRIG_BUSY_ACCESS "RO" |
| #define DMA_CH7_CTRL_TRIG_CHAIN_TO_ACCESS "RW" |
| #define DMA_CH7_CTRL_TRIG_DATA_SIZE_ACCESS "RW" |
| #define DMA_CH7_CTRL_TRIG_EN_ACCESS "RW" |
| #define DMA_CH7_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" |
| #define DMA_CH7_CTRL_TRIG_INCR_READ_ACCESS "RW" |
| #define DMA_CH7_CTRL_TRIG_INCR_READ_REV_ACCESS "RW" |
| #define DMA_CH7_CTRL_TRIG_INCR_WRITE_ACCESS "RW" |
| #define DMA_CH7_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW" |
| #define DMA_CH7_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" |
| #define DMA_CH7_CTRL_TRIG_READ_ERROR_ACCESS "WC" |
| #define DMA_CH7_CTRL_TRIG_RING_SEL_ACCESS "RW" |
| #define DMA_CH7_CTRL_TRIG_RING_SIZE_ACCESS "RW" |
| #define DMA_CH7_CTRL_TRIG_SNIFF_EN_ACCESS "RW" |
| #define DMA_CH7_CTRL_TRIG_TREQ_SEL_ACCESS "RW" |
| #define DMA_CH7_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" |
| #define DMA_CH7_DBG_CTDREQ_ACCESS "WC" |
| #define DMA_CH7_DBG_TCR_ACCESS "RO" |
| #define DMA_CH7_READ_ADDR_ACCESS "RW" |
| #define DMA_CH7_TRANS_COUNT_COUNT_ACCESS "RW" |
| #define DMA_CH7_TRANS_COUNT_MODE_ACCESS "RW" |
| #define DMA_CH7_WRITE_ADDR_ACCESS "RW" |
| #define DMA_CH8_AL1_CTRL_ACCESS "RW" |
| #define DMA_CH8_AL1_CTRL_RESET "-" |
| #define DMA_CH8_AL1_READ_ADDR_ACCESS "RW" |
| #define DMA_CH8_AL1_READ_ADDR_RESET "-" |
| #define DMA_CH8_AL1_TRANS_COUNT_TRIG_ACCESS "RW" |
| #define DMA_CH8_AL1_TRANS_COUNT_TRIG_RESET "-" |
| #define DMA_CH8_AL1_WRITE_ADDR_ACCESS "RW" |
| #define DMA_CH8_AL1_WRITE_ADDR_RESET "-" |
| #define DMA_CH8_AL2_CTRL_ACCESS "RW" |
| #define DMA_CH8_AL2_CTRL_RESET "-" |
| #define DMA_CH8_AL2_READ_ADDR_ACCESS "RW" |
| #define DMA_CH8_AL2_READ_ADDR_RESET "-" |
| #define DMA_CH8_AL2_TRANS_COUNT_ACCESS "RW" |
| #define DMA_CH8_AL2_TRANS_COUNT_RESET "-" |
| #define DMA_CH8_AL2_WRITE_ADDR_TRIG_ACCESS "RW" |
| #define DMA_CH8_AL2_WRITE_ADDR_TRIG_RESET "-" |
| #define DMA_CH8_AL3_CTRL_ACCESS "RW" |
| #define DMA_CH8_AL3_CTRL_RESET "-" |
| #define DMA_CH8_AL3_READ_ADDR_TRIG_ACCESS "RW" |
| #define DMA_CH8_AL3_READ_ADDR_TRIG_RESET "-" |
| #define DMA_CH8_AL3_TRANS_COUNT_ACCESS "RW" |
| #define DMA_CH8_AL3_TRANS_COUNT_RESET "-" |
| #define DMA_CH8_AL3_WRITE_ADDR_ACCESS "RW" |
| #define DMA_CH8_AL3_WRITE_ADDR_RESET "-" |
| #define DMA_CH8_CTRL_TRIG_AHB_ERROR_ACCESS "RO" |
| #define DMA_CH8_CTRL_TRIG_BSWAP_ACCESS "RW" |
| #define DMA_CH8_CTRL_TRIG_BUSY_ACCESS "RO" |
| #define DMA_CH8_CTRL_TRIG_CHAIN_TO_ACCESS "RW" |
| #define DMA_CH8_CTRL_TRIG_DATA_SIZE_ACCESS "RW" |
| #define DMA_CH8_CTRL_TRIG_EN_ACCESS "RW" |
| #define DMA_CH8_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" |
| #define DMA_CH8_CTRL_TRIG_INCR_READ_ACCESS "RW" |
| #define DMA_CH8_CTRL_TRIG_INCR_READ_REV_ACCESS "RW" |
| #define DMA_CH8_CTRL_TRIG_INCR_WRITE_ACCESS "RW" |
| #define DMA_CH8_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW" |
| #define DMA_CH8_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" |
| #define DMA_CH8_CTRL_TRIG_READ_ERROR_ACCESS "WC" |
| #define DMA_CH8_CTRL_TRIG_RING_SEL_ACCESS "RW" |
| #define DMA_CH8_CTRL_TRIG_RING_SIZE_ACCESS "RW" |
| #define DMA_CH8_CTRL_TRIG_SNIFF_EN_ACCESS "RW" |
| #define DMA_CH8_CTRL_TRIG_TREQ_SEL_ACCESS "RW" |
| #define DMA_CH8_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" |
| #define DMA_CH8_DBG_CTDREQ_ACCESS "WC" |
| #define DMA_CH8_DBG_TCR_ACCESS "RO" |
| #define DMA_CH8_READ_ADDR_ACCESS "RW" |
| #define DMA_CH8_TRANS_COUNT_COUNT_ACCESS "RW" |
| #define DMA_CH8_TRANS_COUNT_MODE_ACCESS "RW" |
| #define DMA_CH8_WRITE_ADDR_ACCESS "RW" |
| #define DMA_CH9_AL1_CTRL_ACCESS "RW" |
| #define DMA_CH9_AL1_CTRL_RESET "-" |
| #define DMA_CH9_AL1_READ_ADDR_ACCESS "RW" |
| #define DMA_CH9_AL1_READ_ADDR_RESET "-" |
| #define DMA_CH9_AL1_TRANS_COUNT_TRIG_ACCESS "RW" |
| #define DMA_CH9_AL1_TRANS_COUNT_TRIG_RESET "-" |
| #define DMA_CH9_AL1_WRITE_ADDR_ACCESS "RW" |
| #define DMA_CH9_AL1_WRITE_ADDR_RESET "-" |
| #define DMA_CH9_AL2_CTRL_ACCESS "RW" |
| #define DMA_CH9_AL2_CTRL_RESET "-" |
| #define DMA_CH9_AL2_READ_ADDR_ACCESS "RW" |
| #define DMA_CH9_AL2_READ_ADDR_RESET "-" |
| #define DMA_CH9_AL2_TRANS_COUNT_ACCESS "RW" |
| #define DMA_CH9_AL2_TRANS_COUNT_RESET "-" |
| #define DMA_CH9_AL2_WRITE_ADDR_TRIG_ACCESS "RW" |
| #define DMA_CH9_AL2_WRITE_ADDR_TRIG_RESET "-" |
| #define DMA_CH9_AL3_CTRL_ACCESS "RW" |
| #define DMA_CH9_AL3_CTRL_RESET "-" |
| #define DMA_CH9_AL3_READ_ADDR_TRIG_ACCESS "RW" |
| #define DMA_CH9_AL3_READ_ADDR_TRIG_RESET "-" |
| #define DMA_CH9_AL3_TRANS_COUNT_ACCESS "RW" |
| #define DMA_CH9_AL3_TRANS_COUNT_RESET "-" |
| #define DMA_CH9_AL3_WRITE_ADDR_ACCESS "RW" |
| #define DMA_CH9_AL3_WRITE_ADDR_RESET "-" |
| #define DMA_CH9_CTRL_TRIG_AHB_ERROR_ACCESS "RO" |
| #define DMA_CH9_CTRL_TRIG_BSWAP_ACCESS "RW" |
| #define DMA_CH9_CTRL_TRIG_BUSY_ACCESS "RO" |
| #define DMA_CH9_CTRL_TRIG_CHAIN_TO_ACCESS "RW" |
| #define DMA_CH9_CTRL_TRIG_DATA_SIZE_ACCESS "RW" |
| #define DMA_CH9_CTRL_TRIG_EN_ACCESS "RW" |
| #define DMA_CH9_CTRL_TRIG_HIGH_PRIORITY_ACCESS "RW" |
| #define DMA_CH9_CTRL_TRIG_INCR_READ_ACCESS "RW" |
| #define DMA_CH9_CTRL_TRIG_INCR_READ_REV_ACCESS "RW" |
| #define DMA_CH9_CTRL_TRIG_INCR_WRITE_ACCESS "RW" |
| #define DMA_CH9_CTRL_TRIG_INCR_WRITE_REV_ACCESS "RW" |
| #define DMA_CH9_CTRL_TRIG_IRQ_QUIET_ACCESS "RW" |
| #define DMA_CH9_CTRL_TRIG_READ_ERROR_ACCESS "WC" |
| #define DMA_CH9_CTRL_TRIG_RING_SEL_ACCESS "RW" |
| #define DMA_CH9_CTRL_TRIG_RING_SIZE_ACCESS "RW" |
| #define DMA_CH9_CTRL_TRIG_SNIFF_EN_ACCESS "RW" |
| #define DMA_CH9_CTRL_TRIG_TREQ_SEL_ACCESS "RW" |
| #define DMA_CH9_CTRL_TRIG_WRITE_ERROR_ACCESS "WC" |
| #define DMA_CH9_DBG_CTDREQ_ACCESS "WC" |
| #define DMA_CH9_DBG_TCR_ACCESS "RO" |
| #define DMA_CH9_READ_ADDR_ACCESS "RW" |
| #define DMA_CH9_TRANS_COUNT_COUNT_ACCESS "RW" |
| #define DMA_CH9_TRANS_COUNT_MODE_ACCESS "RW" |
| #define DMA_CH9_WRITE_ADDR_ACCESS "RW" |
| #define DMA_CHAN_ABORT_ACCESS "SC" |
| #define DMA_FIFO_LEVELS_RAF_LVL_ACCESS "RO" |
| #define DMA_FIFO_LEVELS_TDF_LVL_ACCESS "RO" |
| #define DMA_FIFO_LEVELS_WAF_LVL_ACCESS "RO" |
| #define DMA_INTE0_ACCESS "RW" |
| #define DMA_INTE1_ACCESS "RW" |
| #define DMA_INTE2_ACCESS "RW" |
| #define DMA_INTE3_ACCESS "RW" |
| #define DMA_INTF0_ACCESS "RW" |
| #define DMA_INTF1_ACCESS "RW" |
| #define DMA_INTF2_ACCESS "RW" |
| #define DMA_INTF3_ACCESS "RW" |
| #define DMA_INTR_ACCESS "WC" |
| #define DMA_INTS0_ACCESS "WC" |
| #define DMA_INTS1_ACCESS "WC" |
| #define DMA_INTS2_ACCESS "WC" |
| #define DMA_INTS3_ACCESS "WC" |
| #define DMA_MPU_BAR0_ADDR_ACCESS "RW" |
| #define DMA_MPU_BAR1_ADDR_ACCESS "RW" |
| #define DMA_MPU_BAR2_ADDR_ACCESS "RW" |
| #define DMA_MPU_BAR3_ADDR_ACCESS "RW" |
| #define DMA_MPU_BAR4_ADDR_ACCESS "RW" |
| #define DMA_MPU_BAR5_ADDR_ACCESS "RW" |
| #define DMA_MPU_BAR6_ADDR_ACCESS "RW" |
| #define DMA_MPU_BAR7_ADDR_ACCESS "RW" |
| #define DMA_MPU_CTRL_NS_HIDE_ADDR_ACCESS "RW" |
| #define DMA_MPU_CTRL_P_ACCESS "RW" |
| #define DMA_MPU_CTRL_S_ACCESS "RW" |
| #define DMA_MPU_LAR0_ADDR_ACCESS "RW" |
| #define DMA_MPU_LAR0_EN_ACCESS "RW" |
| #define DMA_MPU_LAR0_P_ACCESS "RW" |
| #define DMA_MPU_LAR0_S_ACCESS "RW" |
| #define DMA_MPU_LAR1_ADDR_ACCESS "RW" |
| #define DMA_MPU_LAR1_EN_ACCESS "RW" |
| #define DMA_MPU_LAR1_P_ACCESS "RW" |
| #define DMA_MPU_LAR1_S_ACCESS "RW" |
| #define DMA_MPU_LAR2_ADDR_ACCESS "RW" |
| #define DMA_MPU_LAR2_EN_ACCESS "RW" |
| #define DMA_MPU_LAR2_P_ACCESS "RW" |
| #define DMA_MPU_LAR2_S_ACCESS "RW" |
| #define DMA_MPU_LAR3_ADDR_ACCESS "RW" |
| #define DMA_MPU_LAR3_EN_ACCESS "RW" |
| #define DMA_MPU_LAR3_P_ACCESS "RW" |
| #define DMA_MPU_LAR3_S_ACCESS "RW" |
| #define DMA_MPU_LAR4_ADDR_ACCESS "RW" |
| #define DMA_MPU_LAR4_EN_ACCESS "RW" |
| #define DMA_MPU_LAR4_P_ACCESS "RW" |
| #define DMA_MPU_LAR4_S_ACCESS "RW" |
| #define DMA_MPU_LAR5_ADDR_ACCESS "RW" |
| #define DMA_MPU_LAR5_EN_ACCESS "RW" |
| #define DMA_MPU_LAR5_P_ACCESS "RW" |
| #define DMA_MPU_LAR5_S_ACCESS "RW" |
| #define DMA_MPU_LAR6_ADDR_ACCESS "RW" |
| #define DMA_MPU_LAR6_EN_ACCESS "RW" |
| #define DMA_MPU_LAR6_P_ACCESS "RW" |
| #define DMA_MPU_LAR6_S_ACCESS "RW" |
| #define DMA_MPU_LAR7_ADDR_ACCESS "RW" |
| #define DMA_MPU_LAR7_EN_ACCESS "RW" |
| #define DMA_MPU_LAR7_P_ACCESS "RW" |
| #define DMA_MPU_LAR7_S_ACCESS "RW" |
| #define DMA_MULTI_CHAN_TRIGGER_ACCESS "SC" |
| #define DMA_N_CHANNELS_ACCESS "RO" |
| #define DMA_N_CHANNELS_RESET "-" |
| #define DMA_SECCFG_CH0_LOCK_ACCESS "RW" |
| #define DMA_SECCFG_CH0_P_ACCESS "RW" |
| #define DMA_SECCFG_CH0_S_ACCESS "RW" |
| #define DMA_SECCFG_CH10_LOCK_ACCESS "RW" |
| #define DMA_SECCFG_CH10_P_ACCESS "RW" |
| #define DMA_SECCFG_CH10_S_ACCESS "RW" |
| #define DMA_SECCFG_CH11_LOCK_ACCESS "RW" |
| #define DMA_SECCFG_CH11_P_ACCESS "RW" |
| #define DMA_SECCFG_CH11_S_ACCESS "RW" |
| #define DMA_SECCFG_CH12_LOCK_ACCESS "RW" |
| #define DMA_SECCFG_CH12_P_ACCESS "RW" |
| #define DMA_SECCFG_CH12_S_ACCESS "RW" |
| #define DMA_SECCFG_CH13_LOCK_ACCESS "RW" |
| #define DMA_SECCFG_CH13_P_ACCESS "RW" |
| #define DMA_SECCFG_CH13_S_ACCESS "RW" |
| #define DMA_SECCFG_CH14_LOCK_ACCESS "RW" |
| #define DMA_SECCFG_CH14_P_ACCESS "RW" |
| #define DMA_SECCFG_CH14_S_ACCESS "RW" |
| #define DMA_SECCFG_CH15_LOCK_ACCESS "RW" |
| #define DMA_SECCFG_CH15_P_ACCESS "RW" |
| #define DMA_SECCFG_CH15_S_ACCESS "RW" |
| #define DMA_SECCFG_CH1_LOCK_ACCESS "RW" |
| #define DMA_SECCFG_CH1_P_ACCESS "RW" |
| #define DMA_SECCFG_CH1_S_ACCESS "RW" |
| #define DMA_SECCFG_CH2_LOCK_ACCESS "RW" |
| #define DMA_SECCFG_CH2_P_ACCESS "RW" |
| #define DMA_SECCFG_CH2_S_ACCESS "RW" |
| #define DMA_SECCFG_CH3_LOCK_ACCESS "RW" |
| #define DMA_SECCFG_CH3_P_ACCESS "RW" |
| #define DMA_SECCFG_CH3_S_ACCESS "RW" |
| #define DMA_SECCFG_CH4_LOCK_ACCESS "RW" |
| #define DMA_SECCFG_CH4_P_ACCESS "RW" |
| #define DMA_SECCFG_CH4_S_ACCESS "RW" |
| #define DMA_SECCFG_CH5_LOCK_ACCESS "RW" |
| #define DMA_SECCFG_CH5_P_ACCESS "RW" |
| #define DMA_SECCFG_CH5_S_ACCESS "RW" |
| #define DMA_SECCFG_CH6_LOCK_ACCESS "RW" |
| #define DMA_SECCFG_CH6_P_ACCESS "RW" |
| #define DMA_SECCFG_CH6_S_ACCESS "RW" |
| #define DMA_SECCFG_CH7_LOCK_ACCESS "RW" |
| #define DMA_SECCFG_CH7_P_ACCESS "RW" |
| #define DMA_SECCFG_CH7_S_ACCESS "RW" |
| #define DMA_SECCFG_CH8_LOCK_ACCESS "RW" |
| #define DMA_SECCFG_CH8_P_ACCESS "RW" |
| #define DMA_SECCFG_CH8_S_ACCESS "RW" |
| #define DMA_SECCFG_CH9_LOCK_ACCESS "RW" |
| #define DMA_SECCFG_CH9_P_ACCESS "RW" |
| #define DMA_SECCFG_CH9_S_ACCESS "RW" |
| #define DMA_SECCFG_IRQ0_P_ACCESS "RW" |
| #define DMA_SECCFG_IRQ0_S_ACCESS "RW" |
| #define DMA_SECCFG_IRQ1_P_ACCESS "RW" |
| #define DMA_SECCFG_IRQ1_S_ACCESS "RW" |
| #define DMA_SECCFG_IRQ2_P_ACCESS "RW" |
| #define DMA_SECCFG_IRQ2_S_ACCESS "RW" |
| #define DMA_SECCFG_IRQ3_P_ACCESS "RW" |
| #define DMA_SECCFG_IRQ3_S_ACCESS "RW" |
| #define DMA_SECCFG_MISC_SNIFF_P_ACCESS "RW" |
| #define DMA_SECCFG_MISC_SNIFF_S_ACCESS "RW" |
| #define DMA_SECCFG_MISC_TIMER0_P_ACCESS "RW" |
| #define DMA_SECCFG_MISC_TIMER0_S_ACCESS "RW" |
| #define DMA_SECCFG_MISC_TIMER1_P_ACCESS "RW" |
| #define DMA_SECCFG_MISC_TIMER1_S_ACCESS "RW" |
| #define DMA_SECCFG_MISC_TIMER2_P_ACCESS "RW" |
| #define DMA_SECCFG_MISC_TIMER2_S_ACCESS "RW" |
| #define DMA_SECCFG_MISC_TIMER3_P_ACCESS "RW" |
| #define DMA_SECCFG_MISC_TIMER3_S_ACCESS "RW" |
| #define DMA_SNIFF_CTRL_BSWAP_ACCESS "RW" |
| #define DMA_SNIFF_CTRL_CALC_ACCESS "RW" |
| #define DMA_SNIFF_CTRL_DMACH_ACCESS "RW" |
| #define DMA_SNIFF_CTRL_EN_ACCESS "RW" |
| #define DMA_SNIFF_CTRL_OUT_INV_ACCESS "RW" |
| #define DMA_SNIFF_CTRL_OUT_REV_ACCESS "RW" |
| #define DMA_SNIFF_DATA_ACCESS "RW" |
| #define DMA_TIMER0_X_ACCESS "RW" |
| #define DMA_TIMER0_Y_ACCESS "RW" |
| #define DMA_TIMER1_X_ACCESS "RW" |
| #define DMA_TIMER1_Y_ACCESS "RW" |
| #define DMA_TIMER2_X_ACCESS "RW" |
| #define DMA_TIMER2_Y_ACCESS "RW" |
| #define DMA_TIMER3_X_ACCESS "RW" |
| #define DMA_TIMER3_Y_ACCESS "RW" |